cpu.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/ahb.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/flow.h>
  12. #include <asm/arch/pinmux.h>
  13. #include <asm/arch/tegra.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <asm/arch-tegra/pmc.h>
  16. #include <asm/arch-tegra/ap.h>
  17. #include <linux/delay.h>
  18. #include "../cpu.h"
  19. /* Tegra124-specific CPU init code */
  20. static void enable_cpu_power_rail(void)
  21. {
  22. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  23. debug("%s entry\n", __func__);
  24. /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
  25. pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
  26. pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
  27. pmic_enable_cpu_vdd();
  28. /*
  29. * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
  30. * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
  31. */
  32. writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
  33. /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
  34. clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
  35. setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
  36. }
  37. static void enable_cpu_clocks(void)
  38. {
  39. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  40. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
  41. u32 reg;
  42. debug("%s entry\n", __func__);
  43. /* Wait for PLL-X to lock */
  44. do {
  45. reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
  46. debug("%s: PLLX base = 0x%08X\n", __func__, reg);
  47. } while ((reg & (1 << pllinfo->lock_det)) == 0);
  48. debug("%s: PLLX locked, delay for stable clocks\n", __func__);
  49. /* Wait until all clocks are stable */
  50. udelay(PLL_STABILIZATION_DELAY);
  51. debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
  52. writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
  53. writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
  54. debug("%s: Enabling clock to all CPUs\n", __func__);
  55. /* Enable the clock to all CPUs */
  56. reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
  57. CLR_CPU0_CLK_STP;
  58. writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
  59. debug("%s: Enabling main CPU complex clocks\n", __func__);
  60. /* Always enable the main CPU complex clocks */
  61. clock_enable(PERIPH_ID_CPU);
  62. clock_enable(PERIPH_ID_CPULP);
  63. clock_enable(PERIPH_ID_CPUG);
  64. debug("%s: Done\n", __func__);
  65. }
  66. static void remove_cpu_resets(void)
  67. {
  68. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  69. u32 reg;
  70. debug("%s entry\n", __func__);
  71. /* Take the slow and fast partitions out of reset */
  72. reg = CLR_NONCPURESET;
  73. writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
  74. writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
  75. /* Clear the SW-controlled reset of the slow cluster */
  76. reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
  77. CLR_L2RESET | CLR_PRESETDBG;
  78. writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
  79. /* Clear the SW-controlled reset of the fast cluster */
  80. reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
  81. CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
  82. CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
  83. CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
  84. CLR_L2RESET | CLR_PRESETDBG;
  85. writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
  86. }
  87. static void tegra124_ram_repair(void)
  88. {
  89. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  90. u32 ram_repair_timeout; /*usec*/
  91. u32 val;
  92. /*
  93. * Request the Flow Controller perform RAM repair whenever it turns on
  94. * a power rail that requires RAM repair.
  95. */
  96. clrbits_le32(&flow->ram_repair, RAM_REPAIR_BYPASS_EN);
  97. /* Request SW trigerred RAM repair by setting req bit */
  98. /* cluster 0 */
  99. setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ);
  100. /* Wait for completion (status == 0) */
  101. ram_repair_timeout = 500;
  102. do {
  103. udelay(1);
  104. val = readl(&flow->ram_repair);
  105. } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
  106. if (!ram_repair_timeout)
  107. debug("Ram Repair cluster0 failed\n");
  108. /* cluster 1 */
  109. setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ);
  110. /* Wait for completion (status == 0) */
  111. ram_repair_timeout = 500;
  112. do {
  113. udelay(1);
  114. val = readl(&flow->ram_repair_cluster1);
  115. } while (!(val & RAM_REPAIR_STS) && ram_repair_timeout--);
  116. if (!ram_repair_timeout)
  117. debug("Ram Repair cluster1 failed\n");
  118. }
  119. /**
  120. * Tegra124 requires some special clock initialization, including setting up
  121. * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
  122. */
  123. void tegra124_init_clocks(void)
  124. {
  125. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  126. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  127. struct clk_rst_ctlr *clkrst =
  128. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  129. u32 val;
  130. debug("%s entry\n", __func__);
  131. /* Set active CPU cluster to G */
  132. clrbits_le32(&flow->cluster_control, 1);
  133. /* Change the oscillator drive strength */
  134. val = readl(&clkrst->crc_osc_ctrl);
  135. val &= ~OSC_XOFS_MASK;
  136. val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
  137. writel(val, &clkrst->crc_osc_ctrl);
  138. /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
  139. val = readl(&pmc->pmc_osc_edpd_over);
  140. val &= ~PMC_XOFS_MASK;
  141. val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
  142. writel(val, &pmc->pmc_osc_edpd_over);
  143. /* Set HOLD_CKE_LOW_EN to 1 */
  144. setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
  145. debug("Setting up PLLX\n");
  146. init_pllx();
  147. val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
  148. writel(val, &clkrst->crc_clk_sys_rate);
  149. /* Enable clocks to required peripherals. TBD - minimize this list */
  150. debug("Enabling clocks\n");
  151. clock_set_enable(PERIPH_ID_CACHE2, 1);
  152. clock_set_enable(PERIPH_ID_GPIO, 1);
  153. clock_set_enable(PERIPH_ID_TMR, 1);
  154. clock_set_enable(PERIPH_ID_CPU, 1);
  155. clock_set_enable(PERIPH_ID_EMC, 1);
  156. clock_set_enable(PERIPH_ID_I2C5, 1);
  157. clock_set_enable(PERIPH_ID_APBDMA, 1);
  158. clock_set_enable(PERIPH_ID_MEM, 1);
  159. clock_set_enable(PERIPH_ID_CORESIGHT, 1);
  160. clock_set_enable(PERIPH_ID_MSELECT, 1);
  161. clock_set_enable(PERIPH_ID_DVFS, 1);
  162. /*
  163. * Set MSELECT clock source as PLLP (00), and ask for a clock
  164. * divider that would set the MSELECT clock at 102MHz for a
  165. * PLLP base of 408MHz.
  166. */
  167. clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
  168. CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
  169. /* Give clock time to stabilize */
  170. udelay(IO_STABILIZATION_DELAY);
  171. /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
  172. clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
  173. /* Give clock time to stabilize */
  174. udelay(IO_STABILIZATION_DELAY);
  175. /* Take required peripherals out of reset */
  176. debug("Taking periphs out of reset\n");
  177. reset_set_enable(PERIPH_ID_CACHE2, 0);
  178. reset_set_enable(PERIPH_ID_GPIO, 0);
  179. reset_set_enable(PERIPH_ID_TMR, 0);
  180. reset_set_enable(PERIPH_ID_COP, 0);
  181. reset_set_enable(PERIPH_ID_EMC, 0);
  182. reset_set_enable(PERIPH_ID_I2C5, 0);
  183. reset_set_enable(PERIPH_ID_APBDMA, 0);
  184. reset_set_enable(PERIPH_ID_MEM, 0);
  185. reset_set_enable(PERIPH_ID_CORESIGHT, 0);
  186. reset_set_enable(PERIPH_ID_MSELECT, 0);
  187. reset_set_enable(PERIPH_ID_DVFS, 0);
  188. debug("%s exit\n", __func__);
  189. }
  190. static bool is_partition_powered(u32 partid)
  191. {
  192. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  193. u32 reg;
  194. /* Get power gate status */
  195. reg = readl(&pmc->pmc_pwrgate_status);
  196. return !!(reg & (1 << partid));
  197. }
  198. static void unpower_partition(u32 partid)
  199. {
  200. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  201. debug("%s: part ID = %08X\n", __func__, partid);
  202. /* Is the partition on? */
  203. if (is_partition_powered(partid)) {
  204. /* Yes, toggle the partition power state (ON -> OFF) */
  205. debug("power_partition, toggling state\n");
  206. writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
  207. /* Wait for the power to come down */
  208. while (is_partition_powered(partid))
  209. ;
  210. /* Give I/O signals time to stabilize */
  211. udelay(IO_STABILIZATION_DELAY);
  212. }
  213. }
  214. void unpower_cpus(void)
  215. {
  216. debug("%s entry: G cluster\n", __func__);
  217. /* Power down the fast cluster rail partition */
  218. debug("%s: CRAIL\n", __func__);
  219. unpower_partition(CRAIL);
  220. /* Power down the fast cluster non-CPU partition */
  221. debug("%s: C0NC\n", __func__);
  222. unpower_partition(C0NC);
  223. /* Power down the fast cluster CPU0 partition */
  224. debug("%s: CE0\n", __func__);
  225. unpower_partition(CE0);
  226. debug("%s: done\n", __func__);
  227. }
  228. static void power_partition(u32 partid)
  229. {
  230. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  231. debug("%s: part ID = %08X\n", __func__, partid);
  232. /* Is the partition already on? */
  233. if (!is_partition_powered(partid)) {
  234. /* No, toggle the partition power state (OFF -> ON) */
  235. debug("power_partition, toggling state\n");
  236. writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
  237. /* Wait for the power to come up */
  238. while (!is_partition_powered(partid))
  239. ;
  240. /* Give I/O signals time to stabilize */
  241. udelay(IO_STABILIZATION_DELAY);
  242. }
  243. }
  244. void powerup_cpus(void)
  245. {
  246. /* We boot to the fast cluster */
  247. debug("%s entry: G cluster\n", __func__);
  248. /* Power up the fast cluster rail partition */
  249. debug("%s: CRAIL\n", __func__);
  250. power_partition(CRAIL);
  251. /* Power up the fast cluster non-CPU partition */
  252. debug("%s: C0NC\n", __func__);
  253. power_partition(C0NC);
  254. /* Power up the fast cluster CPU0 partition */
  255. debug("%s: CE0\n", __func__);
  256. power_partition(CE0);
  257. debug("%s: done\n", __func__);
  258. }
  259. void start_cpu(u32 reset_vector)
  260. {
  261. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  262. debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
  263. /*
  264. * High power clusters are on after software reset,
  265. * it may interfere with tegra124_ram_repair.
  266. * unpower them.
  267. */
  268. unpower_cpus();
  269. tegra124_init_clocks();
  270. /* Set power-gating timer multiplier */
  271. writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
  272. &pmc->pmc_pwrgate_timer_mult);
  273. enable_cpu_power_rail();
  274. powerup_cpus();
  275. tegra124_ram_repair();
  276. enable_cpu_clocks();
  277. clock_enable_coresight(1);
  278. writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
  279. remove_cpu_resets();
  280. debug("%s exit, should continue @ reset_vector\n", __func__);
  281. }