cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/gp_padctrl.h>
  10. #include <asm/arch/pinmux.h>
  11. #include <asm/arch/tegra.h>
  12. #include <asm/arch-tegra/clk_rst.h>
  13. #include <asm/arch-tegra/pmc.h>
  14. #include <asm/arch-tegra/scu.h>
  15. #include <linux/delay.h>
  16. #include "cpu.h"
  17. int get_num_cpus(void)
  18. {
  19. struct apb_misc_gp_ctlr *gp;
  20. uint rev;
  21. debug("%s entry\n", __func__);
  22. gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
  23. rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
  24. switch (rev) {
  25. case CHIPID_TEGRA20:
  26. return 2;
  27. break;
  28. case CHIPID_TEGRA30:
  29. case CHIPID_TEGRA114:
  30. case CHIPID_TEGRA124:
  31. case CHIPID_TEGRA210:
  32. default:
  33. return 4;
  34. break;
  35. }
  36. }
  37. /*
  38. * Timing tables for each SOC for all four oscillator options.
  39. */
  40. struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
  41. /*
  42. * T20: 1 GHz
  43. *
  44. * Register Field Bits Width
  45. * ------------------------------
  46. * PLLX_BASE p 22:20 3
  47. * PLLX_BASE n 17: 8 10
  48. * PLLX_BASE m 4: 0 5
  49. * PLLX_MISC cpcon 11: 8 4
  50. */
  51. {
  52. { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  53. { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  54. { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  55. { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  56. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  57. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  58. },
  59. /*
  60. * T25: 1.2 GHz
  61. *
  62. * Register Field Bits Width
  63. * ------------------------------
  64. * PLLX_BASE p 22:20 3
  65. * PLLX_BASE n 17: 8 10
  66. * PLLX_BASE m 4: 0 5
  67. * PLLX_MISC cpcon 11: 8 4
  68. */
  69. {
  70. { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
  71. { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  72. { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
  73. { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
  74. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  75. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  76. },
  77. /*
  78. * T30: 600 MHz
  79. *
  80. * Register Field Bits Width
  81. * ------------------------------
  82. * PLLX_BASE p 22:20 3
  83. * PLLX_BASE n 17: 8 10
  84. * PLLX_BASE m 4: 0 5
  85. * PLLX_MISC cpcon 11: 8 4
  86. */
  87. {
  88. { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
  89. { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  90. { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
  91. { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
  92. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
  93. { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
  94. },
  95. /*
  96. * T114: 700 MHz
  97. *
  98. * Register Field Bits Width
  99. * ------------------------------
  100. * PLLX_BASE p 23:20 4
  101. * PLLX_BASE n 15: 8 8
  102. * PLLX_BASE m 7: 0 8
  103. */
  104. {
  105. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
  106. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
  107. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
  108. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
  109. { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
  110. { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
  111. },
  112. /*
  113. * T124: 700 MHz
  114. *
  115. * Register Field Bits Width
  116. * ------------------------------
  117. * PLLX_BASE p 23:20 4
  118. * PLLX_BASE n 15: 8 8
  119. * PLLX_BASE m 7: 0 8
  120. */
  121. {
  122. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
  123. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
  124. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
  125. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
  126. { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
  127. { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
  128. },
  129. /*
  130. * T210: 700 MHz
  131. *
  132. * Register Field Bits Width
  133. * ------------------------------
  134. * PLLX_BASE p 24:20 5
  135. * PLLX_BASE n 15: 8 8
  136. * PLLX_BASE m 7: 0 8
  137. */
  138. {
  139. { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
  140. { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
  141. { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
  142. { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
  143. { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
  144. { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
  145. },
  146. };
  147. static inline void pllx_set_iddq(void)
  148. {
  149. #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
  150. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  151. u32 reg;
  152. debug("%s entry\n", __func__);
  153. /* Disable IDDQ */
  154. reg = readl(&clkrst->crc_pllx_misc3);
  155. reg &= ~PLLX_IDDQ_MASK;
  156. writel(reg, &clkrst->crc_pllx_misc3);
  157. udelay(2);
  158. debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
  159. readl(&clkrst->crc_pllx_misc3));
  160. #endif
  161. }
  162. int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
  163. u32 divp, u32 cpcon)
  164. {
  165. struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
  166. int chip = tegra_get_chip();
  167. u32 reg;
  168. debug("%s entry\n", __func__);
  169. /* If PLLX is already enabled, just return */
  170. if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
  171. debug("%s: PLLX already enabled, returning\n", __func__);
  172. return 0;
  173. }
  174. pllx_set_iddq();
  175. /* Set BYPASS, m, n and p to PLLX_BASE */
  176. reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
  177. reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
  178. writel(reg, &pll->pll_base);
  179. /* Set cpcon to PLLX_MISC */
  180. if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
  181. reg = (cpcon << pllinfo->kcp_shift);
  182. else
  183. reg = 0;
  184. /*
  185. * TODO(twarren@nvidia.com) Check which SoCs use DCCON
  186. * and add to pllinfo table if needed!
  187. */
  188. /* Set dccon to PLLX_MISC if freq > 600MHz */
  189. if (divn > 600)
  190. reg |= (1 << PLL_DCCON_SHIFT);
  191. writel(reg, &pll->pll_misc);
  192. /* Disable BYPASS */
  193. reg = readl(&pll->pll_base);
  194. reg &= ~PLL_BYPASS_MASK;
  195. writel(reg, &pll->pll_base);
  196. debug("%s: base = 0x%08X\n", __func__, reg);
  197. /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
  198. reg = readl(&pll->pll_misc);
  199. if (pllinfo->lock_ena < 32)
  200. reg |= (1 << pllinfo->lock_ena);
  201. writel(reg, &pll->pll_misc);
  202. debug("%s: misc = 0x%08X\n", __func__, reg);
  203. /* Enable PLLX last, once it's all configured */
  204. reg = readl(&pll->pll_base);
  205. reg |= PLL_ENABLE_MASK;
  206. writel(reg, &pll->pll_base);
  207. debug("%s: base final = 0x%08X\n", __func__, reg);
  208. return 0;
  209. }
  210. void init_pllx(void)
  211. {
  212. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  213. struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
  214. int soc_type, sku_info, chip_sku;
  215. enum clock_osc_freq osc;
  216. struct clk_pll_table *sel;
  217. debug("%s entry\n", __func__);
  218. /* get SOC (chip) type */
  219. soc_type = tegra_get_chip();
  220. debug("%s: SoC = 0x%02X\n", __func__, soc_type);
  221. /* get SKU info */
  222. sku_info = tegra_get_sku_info();
  223. debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
  224. /* get chip SKU, combo of the above info */
  225. chip_sku = tegra_get_chip_sku();
  226. debug("%s: Chip SKU = %d\n", __func__, chip_sku);
  227. /* get osc freq */
  228. osc = clock_get_osc_freq();
  229. debug("%s: osc = %d\n", __func__, osc);
  230. /* set pllx */
  231. sel = &tegra_pll_x_table[chip_sku][osc];
  232. pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
  233. }
  234. void enable_cpu_clock(int enable)
  235. {
  236. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  237. u32 clk;
  238. debug("%s entry\n", __func__);
  239. /*
  240. * NOTE:
  241. * Regardless of whether the request is to enable or disable the CPU
  242. * clock, every processor in the CPU complex except the master (CPU 0)
  243. * will have it's clock stopped because the AVP only talks to the
  244. * master.
  245. */
  246. if (enable) {
  247. /* Initialize PLLX */
  248. init_pllx();
  249. /* Wait until all clocks are stable */
  250. udelay(PLL_STABILIZATION_DELAY);
  251. writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
  252. writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
  253. }
  254. /*
  255. * Read the register containing the individual CPU clock enables and
  256. * always stop the clocks to CPUs > 0.
  257. */
  258. clk = readl(&clkrst->crc_clk_cpu_cmplx);
  259. clk |= 1 << CPU1_CLK_STP_SHIFT;
  260. if (get_num_cpus() == 4)
  261. clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
  262. /* Stop/Unstop the CPU clock */
  263. clk &= ~CPU0_CLK_STP_MASK;
  264. clk |= !enable << CPU0_CLK_STP_SHIFT;
  265. writel(clk, &clkrst->crc_clk_cpu_cmplx);
  266. clock_enable(PERIPH_ID_CPU);
  267. }
  268. static int is_cpu_powered(void)
  269. {
  270. return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
  271. pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
  272. }
  273. static void remove_cpu_io_clamps(void)
  274. {
  275. u32 reg;
  276. debug("%s entry\n", __func__);
  277. /* Remove the clamps on the CPU I/O signals */
  278. reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
  279. reg |= CPU_CLMP;
  280. tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
  281. /* Give I/O signals time to stabilize */
  282. udelay(IO_STABILIZATION_DELAY);
  283. }
  284. void powerup_cpu(void)
  285. {
  286. u32 reg;
  287. int timeout = IO_STABILIZATION_DELAY;
  288. debug("%s entry\n", __func__);
  289. if (!is_cpu_powered()) {
  290. /* Toggle the CPU power state (OFF -> ON) */
  291. reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
  292. pmc_pwrgate_toggle));
  293. reg &= PARTID_CP;
  294. reg |= START_CP;
  295. tegra_pmc_writel(reg,
  296. offsetof(struct pmc_ctlr,
  297. pmc_pwrgate_toggle));
  298. /* Wait for the power to come up */
  299. while (!is_cpu_powered()) {
  300. if (timeout-- == 0)
  301. printf("CPU failed to power up!\n");
  302. else
  303. udelay(10);
  304. }
  305. /*
  306. * Remove the I/O clamps from CPU power partition.
  307. * Recommended only on a Warm boot, if the CPU partition gets
  308. * power gated. Shouldn't cause any harm when called after a
  309. * cold boot according to HW, probably just redundant.
  310. */
  311. remove_cpu_io_clamps();
  312. }
  313. }
  314. void reset_A9_cpu(int reset)
  315. {
  316. /*
  317. * NOTE: Regardless of whether the request is to hold the CPU in reset
  318. * or take it out of reset, every processor in the CPU complex
  319. * except the master (CPU 0) will be held in reset because the
  320. * AVP only talks to the master. The AVP does not know that there
  321. * are multiple processors in the CPU complex.
  322. */
  323. int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
  324. int num_cpus = get_num_cpus();
  325. int cpu;
  326. debug("%s entry\n", __func__);
  327. /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
  328. for (cpu = 1; cpu < num_cpus; cpu++)
  329. reset_cmplx_set_enable(cpu, mask, 1);
  330. reset_cmplx_set_enable(0, mask, reset);
  331. /* Enable/Disable master CPU reset */
  332. reset_set_enable(PERIPH_ID_CPU, reset);
  333. }
  334. void clock_enable_coresight(int enable)
  335. {
  336. u32 rst, src = 2;
  337. debug("%s entry\n", __func__);
  338. clock_set_enable(PERIPH_ID_CORESIGHT, enable);
  339. reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
  340. if (enable) {
  341. /*
  342. * Put CoreSight on PLLP_OUT0 and divide it down as per
  343. * PLLP base frequency based on SoC type (T20/T30+).
  344. * Clock divider request would setup CSITE clock as 144MHz
  345. * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
  346. */
  347. src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
  348. clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
  349. /* Unlock the CPU CoreSight interfaces */
  350. rst = CORESIGHT_UNLOCK;
  351. writel(rst, CSITE_CPU_DBG0_LAR);
  352. writel(rst, CSITE_CPU_DBG1_LAR);
  353. if (get_num_cpus() == 4) {
  354. writel(rst, CSITE_CPU_DBG2_LAR);
  355. writel(rst, CSITE_CPU_DBG3_LAR);
  356. }
  357. }
  358. }
  359. void halt_avp(void)
  360. {
  361. debug("%s entry\n", __func__);
  362. for (;;) {
  363. writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
  364. FLOW_CTLR_HALT_COP_EVENTS);
  365. }
  366. }