spl_spi_sunxi.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <image.h>
  7. #include <log.h>
  8. #include <spl.h>
  9. #include <asm/gpio.h>
  10. #include <asm/io.h>
  11. #include <linux/delay.h>
  12. #include <linux/libfdt.h>
  13. #ifdef CONFIG_SPL_OS_BOOT
  14. #error CONFIG_SPL_OS_BOOT is not supported yet
  15. #endif
  16. /*
  17. * This is a very simple U-Boot image loading implementation, trying to
  18. * replicate what the boot ROM is doing when loading the SPL. Because we
  19. * know the exact pins where the SPI Flash is connected and also know
  20. * that the Read Data Bytes (03h) command is supported, the hardware
  21. * configuration is very simple and we don't need the extra flexibility
  22. * of the SPI framework. Moreover, we rely on the default settings of
  23. * the SPI controler hardware registers and only adjust what needs to
  24. * be changed. This is good for the code size and this implementation
  25. * adds less than 400 bytes to the SPL.
  26. *
  27. * There are two variants of the SPI controller in Allwinner SoCs:
  28. * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  29. * Both of them are supported.
  30. *
  31. * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  32. * supported at the moment.
  33. */
  34. /*****************************************************************************/
  35. /* SUN4I variant of the SPI controller */
  36. /*****************************************************************************/
  37. #define SUN4I_SPI0_CCTL 0x1C
  38. #define SUN4I_SPI0_CTL 0x08
  39. #define SUN4I_SPI0_RX 0x00
  40. #define SUN4I_SPI0_TX 0x04
  41. #define SUN4I_SPI0_FIFO_STA 0x28
  42. #define SUN4I_SPI0_BC 0x20
  43. #define SUN4I_SPI0_TC 0x24
  44. #define SUN4I_CTL_ENABLE BIT(0)
  45. #define SUN4I_CTL_MASTER BIT(1)
  46. #define SUN4I_CTL_TF_RST BIT(8)
  47. #define SUN4I_CTL_RF_RST BIT(9)
  48. #define SUN4I_CTL_XCH BIT(10)
  49. /*****************************************************************************/
  50. /* SUN6I variant of the SPI controller */
  51. /*****************************************************************************/
  52. #define SUN6I_SPI0_CCTL 0x24
  53. #define SUN6I_SPI0_GCR 0x04
  54. #define SUN6I_SPI0_TCR 0x08
  55. #define SUN6I_SPI0_FIFO_STA 0x1C
  56. #define SUN6I_SPI0_MBC 0x30
  57. #define SUN6I_SPI0_MTC 0x34
  58. #define SUN6I_SPI0_BCC 0x38
  59. #define SUN6I_SPI0_TXD 0x200
  60. #define SUN6I_SPI0_RXD 0x300
  61. #define SUN6I_CTL_ENABLE BIT(0)
  62. #define SUN6I_CTL_MASTER BIT(1)
  63. #define SUN6I_CTL_SRST BIT(31)
  64. #define SUN6I_TCR_XCH BIT(31)
  65. /*****************************************************************************/
  66. #define CCM_AHB_GATING0 (0x01C20000 + 0x60)
  67. #define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
  68. #ifdef CONFIG_MACH_SUN50I_H6
  69. #define CCM_SPI0_CLK (0x03001000 + 0x940)
  70. #else
  71. #define CCM_SPI0_CLK (0x01C20000 + 0xA0)
  72. #endif
  73. #define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
  74. #define AHB_RESET_SPI0_SHIFT 20
  75. #define AHB_GATE_OFFSET_SPI0 20
  76. #define SPI0_CLK_DIV_BY_2 0x1000
  77. #define SPI0_CLK_DIV_BY_4 0x1001
  78. /*****************************************************************************/
  79. /*
  80. * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  81. * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  82. * The H6 uses PC0, PC2, PC3, PC5.
  83. */
  84. static void spi0_pinmux_setup(unsigned int pin_function)
  85. {
  86. /* All chips use PC0 and PC2. */
  87. sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
  88. sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
  89. /* All chips except H6 use PC1, and only H6 uses PC5. */
  90. if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  91. sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
  92. else
  93. sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
  94. /* Older generations use PC23 for CS, newer ones use PC3. */
  95. if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
  96. IS_ENABLED(CONFIG_MACH_SUN8I_R40))
  97. sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
  98. else
  99. sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
  100. }
  101. static bool is_sun6i_gen_spi(void)
  102. {
  103. return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
  104. IS_ENABLED(CONFIG_MACH_SUN50I_H6);
  105. }
  106. static uintptr_t spi0_base_address(void)
  107. {
  108. if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
  109. return 0x01C05000;
  110. if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  111. return 0x05010000;
  112. if (!is_sun6i_gen_spi())
  113. return 0x01C05000;
  114. return 0x01C68000;
  115. }
  116. /*
  117. * Setup 6 MHz from OSC24M (because the BROM is doing the same).
  118. */
  119. static void spi0_enable_clock(void)
  120. {
  121. uintptr_t base = spi0_base_address();
  122. /* Deassert SPI0 reset on SUN6I */
  123. if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  124. setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
  125. else if (is_sun6i_gen_spi())
  126. setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
  127. (1 << AHB_RESET_SPI0_SHIFT));
  128. /* Open the SPI0 gate */
  129. if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  130. setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
  131. /* Divide by 4 */
  132. writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
  133. SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
  134. /* 24MHz from OSC24M */
  135. writel((1 << 31), CCM_SPI0_CLK);
  136. if (is_sun6i_gen_spi()) {
  137. /* Enable SPI in the master mode and do a soft reset */
  138. setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
  139. SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
  140. /* Wait for completion */
  141. while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
  142. ;
  143. } else {
  144. /* Enable SPI in the master mode and reset FIFO */
  145. setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
  146. SUN4I_CTL_ENABLE |
  147. SUN4I_CTL_TF_RST |
  148. SUN4I_CTL_RF_RST);
  149. }
  150. }
  151. static void spi0_disable_clock(void)
  152. {
  153. uintptr_t base = spi0_base_address();
  154. /* Disable the SPI0 controller */
  155. if (is_sun6i_gen_spi())
  156. clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
  157. SUN6I_CTL_ENABLE);
  158. else
  159. clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
  160. SUN4I_CTL_ENABLE);
  161. /* Disable the SPI0 clock */
  162. writel(0, CCM_SPI0_CLK);
  163. /* Close the SPI0 gate */
  164. if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  165. clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
  166. /* Assert SPI0 reset on SUN6I */
  167. if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  168. clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
  169. else if (is_sun6i_gen_spi())
  170. clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
  171. (1 << AHB_RESET_SPI0_SHIFT));
  172. }
  173. static void spi0_init(void)
  174. {
  175. unsigned int pin_function = SUNXI_GPC_SPI0;
  176. if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
  177. IS_ENABLED(CONFIG_MACH_SUN50I_H6))
  178. pin_function = SUN50I_GPC_SPI0;
  179. spi0_pinmux_setup(pin_function);
  180. spi0_enable_clock();
  181. }
  182. static void spi0_deinit(void)
  183. {
  184. /* New SoCs can disable pins, older could only set them as input */
  185. unsigned int pin_function = SUNXI_GPIO_INPUT;
  186. if (is_sun6i_gen_spi())
  187. pin_function = SUNXI_GPIO_DISABLE;
  188. spi0_disable_clock();
  189. spi0_pinmux_setup(pin_function);
  190. }
  191. /*****************************************************************************/
  192. #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
  193. static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
  194. ulong spi_ctl_reg,
  195. ulong spi_ctl_xch_bitmask,
  196. ulong spi_fifo_reg,
  197. ulong spi_tx_reg,
  198. ulong spi_rx_reg,
  199. ulong spi_bc_reg,
  200. ulong spi_tc_reg,
  201. ulong spi_bcc_reg)
  202. {
  203. writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
  204. writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
  205. if (spi_bcc_reg)
  206. writel(4, spi_bcc_reg); /* SUN6I also needs this */
  207. /* Send the Read Data Bytes (03h) command header */
  208. writeb(0x03, spi_tx_reg);
  209. writeb((u8)(addr >> 16), spi_tx_reg);
  210. writeb((u8)(addr >> 8), spi_tx_reg);
  211. writeb((u8)(addr), spi_tx_reg);
  212. /* Start the data transfer */
  213. setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
  214. /* Wait until everything is received in the RX FIFO */
  215. while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
  216. ;
  217. /* Skip 4 bytes */
  218. readl(spi_rx_reg);
  219. /* Read the data */
  220. while (bufsize-- > 0)
  221. *buf++ = readb(spi_rx_reg);
  222. /* tSHSL time is up to 100 ns in various SPI flash datasheets */
  223. udelay(1);
  224. }
  225. static void spi0_read_data(void *buf, u32 addr, u32 len)
  226. {
  227. u8 *buf8 = buf;
  228. u32 chunk_len;
  229. uintptr_t base = spi0_base_address();
  230. while (len > 0) {
  231. chunk_len = len;
  232. if (chunk_len > SPI_READ_MAX_SIZE)
  233. chunk_len = SPI_READ_MAX_SIZE;
  234. if (is_sun6i_gen_spi()) {
  235. sunxi_spi0_read_data(buf8, addr, chunk_len,
  236. base + SUN6I_SPI0_TCR,
  237. SUN6I_TCR_XCH,
  238. base + SUN6I_SPI0_FIFO_STA,
  239. base + SUN6I_SPI0_TXD,
  240. base + SUN6I_SPI0_RXD,
  241. base + SUN6I_SPI0_MBC,
  242. base + SUN6I_SPI0_MTC,
  243. base + SUN6I_SPI0_BCC);
  244. } else {
  245. sunxi_spi0_read_data(buf8, addr, chunk_len,
  246. base + SUN4I_SPI0_CTL,
  247. SUN4I_CTL_XCH,
  248. base + SUN4I_SPI0_FIFO_STA,
  249. base + SUN4I_SPI0_TX,
  250. base + SUN4I_SPI0_RX,
  251. base + SUN4I_SPI0_BC,
  252. base + SUN4I_SPI0_TC,
  253. 0);
  254. }
  255. len -= chunk_len;
  256. buf8 += chunk_len;
  257. addr += chunk_len;
  258. }
  259. }
  260. static ulong spi_load_read(struct spl_load_info *load, ulong sector,
  261. ulong count, void *buf)
  262. {
  263. spi0_read_data(buf, sector, count);
  264. return count;
  265. }
  266. /*****************************************************************************/
  267. static int spl_spi_load_image(struct spl_image_info *spl_image,
  268. struct spl_boot_device *bootdev)
  269. {
  270. int ret = 0;
  271. struct image_header *header;
  272. header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
  273. spi0_init();
  274. spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
  275. if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
  276. image_get_magic(header) == FDT_MAGIC) {
  277. struct spl_load_info load;
  278. debug("Found FIT image\n");
  279. load.dev = NULL;
  280. load.priv = NULL;
  281. load.filename = NULL;
  282. load.bl_len = 1;
  283. load.read = spi_load_read;
  284. ret = spl_load_simple_fit(spl_image, &load,
  285. CONFIG_SYS_SPI_U_BOOT_OFFS, header);
  286. } else {
  287. ret = spl_parse_image_header(spl_image, header);
  288. if (ret)
  289. return ret;
  290. spi0_read_data((void *)spl_image->load_addr,
  291. CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
  292. }
  293. spi0_deinit();
  294. return ret;
  295. }
  296. /* Use priorty 0 to override the default if it happens to be linked in */
  297. SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);