dram_sunxi_dw.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sun8i H3 platform dram controller init
  4. *
  5. * (C) Copyright 2007-2015 Allwinner Technology Co.
  6. * Jerry Wang <wangflord@allwinnertech.com>
  7. * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
  8. * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
  9. * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/dram.h>
  17. #include <asm/arch/cpu.h>
  18. #include <linux/delay.h>
  19. #include <linux/kconfig.h>
  20. static void mctl_phy_init(u32 val)
  21. {
  22. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  23. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  24. writel(val | PIR_INIT, &mctl_ctl->pir);
  25. mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
  26. }
  27. static void mctl_set_bit_delays(struct dram_para *para)
  28. {
  29. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  30. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  31. int i, j;
  32. clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  33. for (i = 0; i < NR_OF_BYTE_LANES; i++)
  34. for (j = 0; j < LINES_PER_BYTE_LANE; j++)
  35. writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
  36. DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
  37. &mctl_ctl->dx[i].bdlr[j]);
  38. for (i = 0; i < 31; i++)
  39. writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
  40. &mctl_ctl->acbdlr[i]);
  41. #ifdef CONFIG_MACH_SUN8I_R40
  42. /* DQSn, DMn, DQn output enable bit delay */
  43. for (i = 0; i < 4; i++)
  44. writel(0x6 << 24, &mctl_ctl->dx[i].sdlr);
  45. #endif
  46. setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  47. }
  48. enum {
  49. MBUS_PORT_CPU = 0,
  50. MBUS_PORT_GPU = 1,
  51. MBUS_PORT_UNUSED = 2,
  52. MBUS_PORT_DMA = 3,
  53. MBUS_PORT_VE = 4,
  54. MBUS_PORT_CSI = 5,
  55. MBUS_PORT_NAND = 6,
  56. MBUS_PORT_SS = 7,
  57. MBUS_PORT_TS = 8,
  58. MBUS_PORT_DI = 9,
  59. MBUS_PORT_DE = 10,
  60. MBUS_PORT_DE_CFD = 11,
  61. MBUS_PORT_UNKNOWN1 = 12,
  62. MBUS_PORT_UNKNOWN2 = 13,
  63. MBUS_PORT_UNKNOWN3 = 14,
  64. };
  65. enum {
  66. MBUS_QOS_LOWEST = 0,
  67. MBUS_QOS_LOW,
  68. MBUS_QOS_HIGH,
  69. MBUS_QOS_HIGHEST
  70. };
  71. inline void mbus_configure_port(u8 port,
  72. bool bwlimit,
  73. bool priority,
  74. u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
  75. u8 waittime, /* 0 .. 0xf */
  76. u8 acs, /* 0 .. 0xff */
  77. u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
  78. u16 bwl1,
  79. u16 bwl2)
  80. {
  81. struct sunxi_mctl_com_reg * const mctl_com =
  82. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  83. const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
  84. | (priority ? (1 << 1) : 0)
  85. | ((qos & 0x3) << 2)
  86. | ((waittime & 0xf) << 4)
  87. | ((acs & 0xff) << 8)
  88. | (bwl0 << 16) );
  89. const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
  90. debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
  91. writel(cfg0, &mctl_com->mcr[port][0]);
  92. writel(cfg1, &mctl_com->mcr[port][1]);
  93. }
  94. #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
  95. mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
  96. MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
  97. static void mctl_set_master_priority_h3(void)
  98. {
  99. struct sunxi_mctl_com_reg * const mctl_com =
  100. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  101. /* enable bandwidth limit windows and set windows size 1us */
  102. writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
  103. /* set cpu high priority */
  104. writel(0x00000001, &mctl_com->mapr);
  105. MBUS_CONF( CPU, true, HIGHEST, 0, 512, 256, 128);
  106. MBUS_CONF( GPU, true, HIGH, 0, 1536, 1024, 256);
  107. MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
  108. MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
  109. MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
  110. MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32);
  111. MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
  112. MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
  113. MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
  114. MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
  115. MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024);
  116. MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
  117. }
  118. static void mctl_set_master_priority_a64(void)
  119. {
  120. struct sunxi_mctl_com_reg * const mctl_com =
  121. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  122. /* enable bandwidth limit windows and set windows size 1us */
  123. writel(399, &mctl_com->tmr);
  124. writel((1 << 16), &mctl_com->bwcr);
  125. /* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
  126. * initialise it */
  127. MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
  128. MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
  129. MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
  130. MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
  131. MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
  132. MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
  133. MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
  134. MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
  135. MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
  136. MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
  137. MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
  138. MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
  139. writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
  140. }
  141. static void mctl_set_master_priority_h5(void)
  142. {
  143. struct sunxi_mctl_com_reg * const mctl_com =
  144. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  145. /* enable bandwidth limit windows and set windows size 1us */
  146. writel(399, &mctl_com->tmr);
  147. writel((1 << 16), &mctl_com->bwcr);
  148. /* set cpu high priority */
  149. writel(0x00000001, &mctl_com->mapr);
  150. /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
  151. * they initialise it */
  152. MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
  153. MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
  154. MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
  155. MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
  156. MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
  157. MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
  158. MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
  159. MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
  160. MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
  161. MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
  162. MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024);
  163. MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200);
  164. }
  165. static void mctl_set_master_priority_r40(void)
  166. {
  167. struct sunxi_mctl_com_reg * const mctl_com =
  168. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  169. /* enable bandwidth limit windows and set windows size 1us */
  170. writel(399, &mctl_com->tmr);
  171. writel((1 << 16), &mctl_com->bwcr);
  172. /* set cpu high priority */
  173. writel(0x00000001, &mctl_com->mapr);
  174. /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
  175. * they initialise it */
  176. MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
  177. MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
  178. MBUS_CONF( UNUSED, true, HIGHEST, 0, 512, 256, 96);
  179. MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
  180. MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
  181. MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
  182. MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
  183. MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
  184. MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
  185. MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
  186. /*
  187. * The port names are probably wrong, but no correct sources
  188. * are available.
  189. */
  190. MBUS_CONF( DE, true, HIGH, 0, 128, 48, 0);
  191. MBUS_CONF( DE_CFD, true, HIGH, 0, 384, 256, 0);
  192. MBUS_CONF(UNKNOWN1, true, HIGHEST, 0, 512, 384, 256);
  193. MBUS_CONF(UNKNOWN2, true, HIGHEST, 2, 8192, 6144, 1024);
  194. MBUS_CONF(UNKNOWN3, true, HIGH, 0, 1280, 144, 64);
  195. }
  196. static void mctl_set_master_priority(uint16_t socid)
  197. {
  198. switch (socid) {
  199. case SOCID_H3:
  200. mctl_set_master_priority_h3();
  201. return;
  202. case SOCID_A64:
  203. mctl_set_master_priority_a64();
  204. return;
  205. case SOCID_H5:
  206. mctl_set_master_priority_h5();
  207. return;
  208. case SOCID_R40:
  209. mctl_set_master_priority_r40();
  210. return;
  211. }
  212. }
  213. static u32 bin_to_mgray(int val)
  214. {
  215. static const u8 lookup_table[32] = {
  216. 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  217. 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
  218. 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
  219. 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
  220. };
  221. return lookup_table[clamp(val, 0, 31)];
  222. }
  223. static int mgray_to_bin(u32 val)
  224. {
  225. static const u8 lookup_table[32] = {
  226. 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  227. 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
  228. 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
  229. 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
  230. };
  231. return lookup_table[val & 0x1f];
  232. }
  233. static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
  234. {
  235. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  236. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  237. int zq_count;
  238. #if defined CONFIG_SUNXI_DRAM_DW_16BIT
  239. zq_count = 4;
  240. #else
  241. zq_count = 6;
  242. #endif
  243. if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
  244. (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
  245. u32 reg_val;
  246. clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
  247. CONFIG_DRAM_ZQ & 0xffff);
  248. writel(PIR_CLRSR, &mctl_ctl->pir);
  249. mctl_phy_init(PIR_ZCAL);
  250. reg_val = readl(&mctl_ctl->zqdr[0]);
  251. reg_val &= (0x1f << 16) | (0x1f << 0);
  252. reg_val |= reg_val << 8;
  253. writel(reg_val, &mctl_ctl->zqdr[0]);
  254. reg_val = readl(&mctl_ctl->zqdr[1]);
  255. reg_val &= (0x1f << 16) | (0x1f << 0);
  256. reg_val |= reg_val << 8;
  257. writel(reg_val, &mctl_ctl->zqdr[1]);
  258. writel(reg_val, &mctl_ctl->zqdr[2]);
  259. } else {
  260. int i;
  261. u16 zq_val[6];
  262. u8 val;
  263. writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
  264. for (i = 0; i < zq_count; i++) {
  265. u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
  266. writel((zq << 20) | (zq << 16) | (zq << 12) |
  267. (zq << 8) | (zq << 4) | (zq << 0),
  268. &mctl_ctl->zqcr);
  269. writel(PIR_CLRSR, &mctl_ctl->pir);
  270. mctl_phy_init(PIR_ZCAL);
  271. zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
  272. writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
  273. writel(PIR_CLRSR, &mctl_ctl->pir);
  274. mctl_phy_init(PIR_ZCAL);
  275. val = readl(&mctl_ctl->zqdr[0]) >> 24;
  276. zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
  277. }
  278. writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
  279. writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
  280. if (zq_count > 4)
  281. writel((zq_val[5] << 16) | zq_val[4],
  282. &mctl_ctl->zqdr[2]);
  283. }
  284. }
  285. static void mctl_set_cr(uint16_t socid, struct dram_para *para)
  286. {
  287. struct sunxi_mctl_com_reg * const mctl_com =
  288. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  289. writel(MCTL_CR_BL8 | MCTL_CR_INTERLEAVED |
  290. #if defined CONFIG_SUNXI_DRAM_DDR3
  291. MCTL_CR_DDR3 | MCTL_CR_2T |
  292. #elif defined CONFIG_SUNXI_DRAM_DDR2
  293. MCTL_CR_DDR2 | MCTL_CR_2T |
  294. #elif defined CONFIG_SUNXI_DRAM_LPDDR3
  295. MCTL_CR_LPDDR3 | MCTL_CR_1T |
  296. #else
  297. #error Unsupported DRAM type!
  298. #endif
  299. (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
  300. MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
  301. (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
  302. MCTL_CR_PAGE_SIZE(para->page_size) |
  303. MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
  304. if (socid == SOCID_R40) {
  305. if (para->dual_rank)
  306. panic("Dual rank memory not supported\n");
  307. /* Mux pin to A15 address line for single rank memory. */
  308. setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
  309. }
  310. }
  311. static void mctl_sys_init(uint16_t socid, struct dram_para *para)
  312. {
  313. struct sunxi_ccm_reg * const ccm =
  314. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  315. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  316. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  317. clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
  318. clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
  319. clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  320. clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  321. clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
  322. if (socid == SOCID_A64 || socid == SOCID_R40)
  323. clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
  324. udelay(10);
  325. clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
  326. udelay(1000);
  327. if (socid == SOCID_A64 || socid == SOCID_R40) {
  328. clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
  329. clrsetbits_le32(&ccm->dram_clk_cfg,
  330. CCM_DRAMCLK_CFG_DIV_MASK |
  331. CCM_DRAMCLK_CFG_SRC_MASK,
  332. CCM_DRAMCLK_CFG_DIV(1) |
  333. CCM_DRAMCLK_CFG_SRC_PLL11 |
  334. CCM_DRAMCLK_CFG_UPD);
  335. } else if (socid == SOCID_H3 || socid == SOCID_H5) {
  336. clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
  337. clrsetbits_le32(&ccm->dram_clk_cfg,
  338. CCM_DRAMCLK_CFG_DIV_MASK |
  339. CCM_DRAMCLK_CFG_SRC_MASK,
  340. CCM_DRAMCLK_CFG_DIV(1) |
  341. CCM_DRAMCLK_CFG_SRC_PLL5 |
  342. CCM_DRAMCLK_CFG_UPD);
  343. }
  344. mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
  345. setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
  346. setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
  347. setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
  348. setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
  349. setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
  350. udelay(10);
  351. writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
  352. udelay(500);
  353. }
  354. /* These are more guessed based on some Allwinner code. */
  355. #define DX_GCR_ODT_DYNAMIC (0x0 << 4)
  356. #define DX_GCR_ODT_ALWAYS_ON (0x1 << 4)
  357. #define DX_GCR_ODT_OFF (0x2 << 4)
  358. static int mctl_channel_init(uint16_t socid, struct dram_para *para)
  359. {
  360. struct sunxi_mctl_com_reg * const mctl_com =
  361. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  362. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  363. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  364. unsigned int i;
  365. mctl_set_cr(socid, para);
  366. mctl_set_timing_params(socid, para);
  367. mctl_set_master_priority(socid);
  368. /* setting VTC, default disable all VT */
  369. clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
  370. if (socid == SOCID_H5)
  371. setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
  372. else
  373. clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
  374. /* increase DFI_PHY_UPD clock */
  375. writel(PROTECT_MAGIC, &mctl_com->protect);
  376. udelay(100);
  377. clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
  378. writel(0x0, &mctl_com->protect);
  379. udelay(100);
  380. /* set dramc odt */
  381. for (i = 0; i < 4; i++) {
  382. u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
  383. (0x3 << 12) | (0x3 << 14);
  384. u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
  385. DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
  386. if (socid == SOCID_H5) {
  387. clearmask |= 0x2 << 8;
  388. setmask |= 0x4 << 8;
  389. }
  390. clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
  391. }
  392. /* AC PDR should always ON */
  393. clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
  394. 0x1 << 1);
  395. /* set DQS auto gating PD mode */
  396. setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
  397. if (socid == SOCID_H3) {
  398. /* dx ddr_clk & hdr_clk dynamic mode */
  399. clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
  400. /* dphy & aphy phase select 270 degree */
  401. clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
  402. (0x1 << 10) | (0x2 << 8));
  403. } else if (socid == SOCID_A64 || socid == SOCID_H5) {
  404. /* dphy & aphy phase select ? */
  405. clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
  406. (0x0 << 10) | (0x3 << 8));
  407. } else if (socid == SOCID_R40) {
  408. /* dx ddr_clk & hdr_clk dynamic mode (tpr13[9] == 0) */
  409. clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
  410. /* dphy & aphy phase select ? */
  411. clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
  412. (0x0 << 10) | (0x3 << 8));
  413. }
  414. /* set half DQ */
  415. if (!para->bus_full_width) {
  416. #if defined CONFIG_SUNXI_DRAM_DW_32BIT
  417. writel(0x0, &mctl_ctl->dx[2].gcr);
  418. writel(0x0, &mctl_ctl->dx[3].gcr);
  419. #elif defined CONFIG_SUNXI_DRAM_DW_16BIT
  420. writel(0x0, &mctl_ctl->dx[1].gcr);
  421. #else
  422. #error Unsupported DRAM bus width!
  423. #endif
  424. }
  425. /* data training configuration */
  426. clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
  427. (para->dual_rank ? 0x3 : 0x1) << 24);
  428. mctl_set_bit_delays(para);
  429. udelay(50);
  430. if (socid == SOCID_H3) {
  431. mctl_h3_zq_calibration_quirk(para);
  432. mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
  433. PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
  434. } else if (socid == SOCID_A64 || socid == SOCID_H5) {
  435. clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
  436. mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
  437. PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
  438. /* no PIR_QSGATE for H5 ???? */
  439. } else if (socid == SOCID_R40) {
  440. clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
  441. mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
  442. PIR_DRAMRST | PIR_DRAMINIT);
  443. }
  444. /* detect ranks and bus width */
  445. if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
  446. /* only one rank */
  447. if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2)
  448. #if defined CONFIG_SUNXI_DRAM_DW_32BIT
  449. || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)
  450. #endif
  451. ) {
  452. clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
  453. para->dual_rank = 0;
  454. }
  455. /* only half DQ width */
  456. #if defined CONFIG_SUNXI_DRAM_DW_32BIT
  457. if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
  458. ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
  459. writel(0x0, &mctl_ctl->dx[2].gcr);
  460. writel(0x0, &mctl_ctl->dx[3].gcr);
  461. para->bus_full_width = 0;
  462. }
  463. #elif defined CONFIG_SUNXI_DRAM_DW_16BIT
  464. if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) {
  465. writel(0x0, &mctl_ctl->dx[1].gcr);
  466. para->bus_full_width = 0;
  467. }
  468. #endif
  469. mctl_set_cr(socid, para);
  470. udelay(20);
  471. /* re-train */
  472. mctl_phy_init(PIR_QSGATE);
  473. if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
  474. return 1;
  475. }
  476. /* check the dramc status */
  477. mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
  478. /* liuke added for refresh debug */
  479. setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
  480. udelay(10);
  481. clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
  482. udelay(10);
  483. /* set PGCR3, CKE polarity */
  484. if (socid == SOCID_H3)
  485. writel(0x00aa0060, &mctl_ctl->pgcr[3]);
  486. else if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40)
  487. writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
  488. /* power down zq calibration module for power save */
  489. setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
  490. /* enable master access */
  491. writel(0xffffffff, &mctl_com->maer);
  492. return 0;
  493. }
  494. static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
  495. {
  496. /* detect row address bits */
  497. para->page_size = 512;
  498. para->row_bits = 16;
  499. para->bank_bits = 2;
  500. mctl_set_cr(socid, para);
  501. for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
  502. if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
  503. break;
  504. /* detect bank address bits */
  505. para->bank_bits = 3;
  506. mctl_set_cr(socid, para);
  507. for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
  508. if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
  509. break;
  510. /* detect page size */
  511. para->page_size = 8192;
  512. mctl_set_cr(socid, para);
  513. for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
  514. if (mctl_mem_matches(para->page_size))
  515. break;
  516. }
  517. /*
  518. * The actual values used here are taken from Allwinner provided boot0
  519. * binaries, though they are probably board specific, so would likely benefit
  520. * from invidual tuning for each board. Apparently a lot of boards copy from
  521. * some Allwinner reference design, so we go with those generic values for now
  522. * in the hope that they are reasonable for most (all?) boards.
  523. */
  524. #define SUN8I_H3_DX_READ_DELAYS \
  525. {{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
  526. { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
  527. { 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
  528. { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }}
  529. #define SUN8I_H3_DX_WRITE_DELAYS \
  530. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
  531. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
  532. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
  533. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6 }}
  534. #define SUN8I_H3_AC_DELAYS \
  535. { 0, 0, 0, 0, 0, 0, 0, 0, \
  536. 0, 0, 0, 0, 0, 0, 0, 0, \
  537. 0, 0, 0, 0, 0, 0, 0, 0, \
  538. 0, 0, 0, 0, 0, 0, 0 }
  539. #define SUN8I_R40_DX_READ_DELAYS \
  540. {{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
  541. { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
  542. { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
  543. { 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 } }
  544. #define SUN8I_R40_DX_WRITE_DELAYS \
  545. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
  546. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
  547. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 }, \
  548. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0 } }
  549. #define SUN8I_R40_AC_DELAYS \
  550. { 0, 0, 3, 0, 0, 0, 0, 0, \
  551. 0, 0, 0, 0, 0, 0, 0, 0, \
  552. 0, 0, 0, 0, 0, 0, 0, 0, \
  553. 0, 0, 0, 0, 0, 0, 0 }
  554. #define SUN50I_A64_DX_READ_DELAYS \
  555. {{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
  556. { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
  557. { 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
  558. { 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
  559. #define SUN50I_A64_DX_WRITE_DELAYS \
  560. {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
  561. { 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
  562. { 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
  563. { 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
  564. #define SUN50I_A64_AC_DELAYS \
  565. { 5, 5, 13, 10, 2, 5, 3, 3, \
  566. 0, 3, 3, 3, 1, 0, 0, 0, \
  567. 3, 4, 0, 3, 4, 1, 4, 0, \
  568. 1, 1, 0, 1, 13, 5, 4 }
  569. #define SUN8I_H5_DX_READ_DELAYS \
  570. {{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
  571. { 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \
  572. { 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \
  573. { 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } }
  574. #define SUN8I_H5_DX_WRITE_DELAYS \
  575. {{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \
  576. { 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \
  577. { 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \
  578. { 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } }
  579. #define SUN8I_H5_AC_DELAYS \
  580. { 0, 0, 5, 5, 0, 0, 0, 0, \
  581. 0, 0, 0, 0, 3, 3, 3, 3, \
  582. 3, 3, 3, 3, 3, 3, 3, 3, \
  583. 3, 3, 3, 3, 2, 0, 0 }
  584. unsigned long sunxi_dram_init(void)
  585. {
  586. struct sunxi_mctl_com_reg * const mctl_com =
  587. (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  588. struct sunxi_mctl_ctl_reg * const mctl_ctl =
  589. (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  590. struct dram_para para = {
  591. .dual_rank = 1,
  592. .bus_full_width = 1,
  593. .row_bits = 15,
  594. .bank_bits = 3,
  595. .page_size = 4096,
  596. #if defined(CONFIG_MACH_SUN8I_H3)
  597. .dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
  598. .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
  599. .ac_delays = SUN8I_H3_AC_DELAYS,
  600. #elif defined(CONFIG_MACH_SUN8I_R40)
  601. .dx_read_delays = SUN8I_R40_DX_READ_DELAYS,
  602. .dx_write_delays = SUN8I_R40_DX_WRITE_DELAYS,
  603. .ac_delays = SUN8I_R40_AC_DELAYS,
  604. #elif defined(CONFIG_MACH_SUN50I)
  605. .dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
  606. .dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
  607. .ac_delays = SUN50I_A64_AC_DELAYS,
  608. #elif defined(CONFIG_MACH_SUN50I_H5)
  609. .dx_read_delays = SUN8I_H5_DX_READ_DELAYS,
  610. .dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
  611. .ac_delays = SUN8I_H5_AC_DELAYS,
  612. #endif
  613. };
  614. /*
  615. * Let the compiler optimize alternatives away by passing this value into
  616. * the static functions. This saves us #ifdefs, but still keeps the binary
  617. * small.
  618. */
  619. #if defined(CONFIG_MACH_SUN8I_H3)
  620. uint16_t socid = SOCID_H3;
  621. #elif defined(CONFIG_MACH_SUN8I_R40)
  622. uint16_t socid = SOCID_R40;
  623. /* Currently we cannot support R40 with dual rank memory */
  624. para.dual_rank = 0;
  625. #elif defined(CONFIG_MACH_SUN8I_V3S)
  626. /* TODO: set delays and mbus priority for V3s */
  627. uint16_t socid = SOCID_H3;
  628. #elif defined(CONFIG_MACH_SUN50I)
  629. uint16_t socid = SOCID_A64;
  630. #elif defined(CONFIG_MACH_SUN50I_H5)
  631. uint16_t socid = SOCID_H5;
  632. #endif
  633. mctl_sys_init(socid, &para);
  634. if (mctl_channel_init(socid, &para))
  635. return 0;
  636. if (para.dual_rank)
  637. writel(0x00000303, &mctl_ctl->odtmap);
  638. else
  639. writel(0x00000201, &mctl_ctl->odtmap);
  640. udelay(1);
  641. /* odt delay */
  642. if (socid == SOCID_H3)
  643. writel(0x0c000400, &mctl_ctl->odtcfg);
  644. if (socid == SOCID_A64 || socid == SOCID_H5 || socid == SOCID_R40) {
  645. /* VTF enable (tpr13[8] == 1) */
  646. setbits_le32(&mctl_ctl->vtfcr,
  647. (socid != SOCID_A64 ? 3 : 2) << 8);
  648. /* DQ hold disable (tpr13[26] == 1) */
  649. clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
  650. }
  651. /* clear credit value */
  652. setbits_le32(&mctl_com->cccr, 1 << 31);
  653. udelay(10);
  654. mctl_auto_detect_dram_size(socid, &para);
  655. mctl_set_cr(socid, &para);
  656. return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
  657. (para.dual_rank ? 2 : 1);
  658. }