dram_sun4i.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sunxi DRAM controller initialization
  4. * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
  5. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  6. *
  7. * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
  8. * and earlier U-Boot Allwinner A10 SPL work
  9. *
  10. * (C) Copyright 2007-2012
  11. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  12. * Berg Xing <bergxing@allwinnertech.com>
  13. * Tom Cubie <tangliang@allwinnertech.com>
  14. */
  15. /*
  16. * Unfortunately the only documentation we have on the sun7i DRAM
  17. * controller is Allwinner boot0 + boot1 code, and that code uses
  18. * magic numbers & shifts with no explanations. Hence this code is
  19. * rather undocumented and full of magic.
  20. */
  21. #include <common.h>
  22. #include <init.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/clock.h>
  25. #include <asm/arch/dram.h>
  26. #include <asm/arch/timer.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <linux/delay.h>
  29. #define CPU_CFG_CHIP_VER(n) ((n) << 6)
  30. #define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
  31. #define CPU_CFG_CHIP_REV_A 0x0
  32. #define CPU_CFG_CHIP_REV_C1 0x1
  33. #define CPU_CFG_CHIP_REV_C2 0x2
  34. #define CPU_CFG_CHIP_REV_B 0x3
  35. /*
  36. * Wait up to 1s for mask to be clear in given reg.
  37. */
  38. static inline void await_bits_clear(u32 *reg, u32 mask)
  39. {
  40. mctl_await_completion(reg, mask, 0);
  41. }
  42. /*
  43. * Wait up to 1s for mask to be set in given reg.
  44. */
  45. static inline void await_bits_set(u32 *reg, u32 mask)
  46. {
  47. mctl_await_completion(reg, mask, mask);
  48. }
  49. /*
  50. * This performs the external DRAM reset by driving the RESET pin low and
  51. * then high again. According to the DDR3 spec, the RESET pin needs to be
  52. * kept low for at least 200 us.
  53. */
  54. static void mctl_ddr3_reset(void)
  55. {
  56. struct sunxi_dram_reg *dram =
  57. (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  58. #ifdef CONFIG_MACH_SUN4I
  59. struct sunxi_timer_reg *timer =
  60. (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
  61. u32 reg_val;
  62. writel(0, &timer->cpu_cfg);
  63. reg_val = readl(&timer->cpu_cfg);
  64. if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
  65. CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
  66. setbits_le32(&dram->mcr, DRAM_MCR_RESET);
  67. udelay(200);
  68. clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
  69. } else
  70. #endif
  71. {
  72. clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
  73. udelay(200);
  74. setbits_le32(&dram->mcr, DRAM_MCR_RESET);
  75. }
  76. /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
  77. * for additional 500 us before driving the CKE pin (Clock Enable)
  78. * high. The duration of this delay can be configured in the SDR_IDCR
  79. * (Initialization Delay Configuration Register) and applied
  80. * automatically by the DRAM controller during the DDR3 initialization
  81. * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
  82. * can't provide sufficient delay at DRAM clock frequencies higher than
  83. * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
  84. * 533 MHz according to the datasheet). Additionally, there is no
  85. * official documentation for the SDR_IDCR register anywhere, and
  86. * there is always a chance that we are interpreting it wrong.
  87. * Better be safe than sorry, so add an explicit delay here. */
  88. udelay(500);
  89. }
  90. static void mctl_set_drive(void)
  91. {
  92. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  93. #ifdef CONFIG_MACH_SUN7I
  94. clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
  95. #else
  96. clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
  97. #endif
  98. DRAM_MCR_MODE_EN(0x3) |
  99. 0xffc);
  100. }
  101. static void mctl_itm_disable(void)
  102. {
  103. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  104. clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
  105. }
  106. static void mctl_itm_enable(void)
  107. {
  108. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  109. clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
  110. }
  111. static void mctl_itm_reset(void)
  112. {
  113. mctl_itm_disable();
  114. udelay(1); /* ITM reset needs a bit of delay */
  115. mctl_itm_enable();
  116. udelay(1);
  117. }
  118. static void mctl_enable_dll0(u32 phase)
  119. {
  120. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  121. clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
  122. ((phase >> 16) & 0x3f) << 6);
  123. clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
  124. udelay(2);
  125. clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
  126. udelay(22);
  127. clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
  128. udelay(22);
  129. }
  130. /* Get the number of DDR byte lanes */
  131. static u32 mctl_get_number_of_lanes(void)
  132. {
  133. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  134. if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
  135. DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
  136. return 4;
  137. else
  138. return 2;
  139. }
  140. /*
  141. * Note: This differs from pm/standby in that it checks the bus width
  142. */
  143. static void mctl_enable_dllx(u32 phase)
  144. {
  145. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  146. u32 i, number_of_lanes;
  147. number_of_lanes = mctl_get_number_of_lanes();
  148. for (i = 1; i <= number_of_lanes; i++) {
  149. clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
  150. (phase & 0xf) << 14);
  151. clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
  152. DRAM_DLLCR_DISABLE);
  153. phase >>= 4;
  154. }
  155. udelay(2);
  156. for (i = 1; i <= number_of_lanes; i++)
  157. clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
  158. DRAM_DLLCR_DISABLE);
  159. udelay(22);
  160. for (i = 1; i <= number_of_lanes; i++)
  161. clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
  162. DRAM_DLLCR_NRESET);
  163. udelay(22);
  164. }
  165. static u32 hpcr_value[32] = {
  166. #ifdef CONFIG_MACH_SUN5I
  167. 0, 0, 0, 0,
  168. 0, 0, 0, 0,
  169. 0, 0, 0, 0,
  170. 0, 0, 0, 0,
  171. 0x1031, 0x1031, 0x0735, 0x1035,
  172. 0x1035, 0x0731, 0x1031, 0,
  173. 0x0301, 0x0301, 0x0301, 0x0301,
  174. 0x0301, 0x0301, 0x0301, 0
  175. #endif
  176. #ifdef CONFIG_MACH_SUN4I
  177. 0x0301, 0x0301, 0x0301, 0x0301,
  178. 0x0301, 0x0301, 0, 0,
  179. 0, 0, 0, 0,
  180. 0, 0, 0, 0,
  181. 0x1031, 0x1031, 0x0735, 0x5031,
  182. 0x1035, 0x0731, 0x1031, 0x0735,
  183. 0x1035, 0x1031, 0x0731, 0x1035,
  184. 0x1031, 0x0301, 0x0301, 0x0731
  185. #endif
  186. #ifdef CONFIG_MACH_SUN7I
  187. 0x0301, 0x0301, 0x0301, 0x0301,
  188. 0x0301, 0x0301, 0x0301, 0x0301,
  189. 0, 0, 0, 0,
  190. 0, 0, 0, 0,
  191. 0x1031, 0x1031, 0x0735, 0x1035,
  192. 0x1035, 0x0731, 0x1031, 0x0735,
  193. 0x1035, 0x1031, 0x0731, 0x1035,
  194. 0x0001, 0x1031, 0, 0x1031
  195. /* last row differs from boot0 source table
  196. * 0x1031, 0x0301, 0x0301, 0x0731
  197. * but boot0 code skips #28 and #30, and sets #29 and #31 to the
  198. * value from #28 entry (0x1031)
  199. */
  200. #endif
  201. };
  202. static void mctl_configure_hostport(void)
  203. {
  204. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  205. u32 i;
  206. for (i = 0; i < 32; i++)
  207. writel(hpcr_value[i], &dram->hpcr[i]);
  208. }
  209. static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
  210. {
  211. u32 reg_val;
  212. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  213. u32 pll5p_clk, pll6x_clk;
  214. u32 pll5p_div, pll6x_div;
  215. u32 pll5p_rate, pll6x_rate;
  216. /* setup DRAM PLL */
  217. reg_val = readl(&ccm->pll5_cfg);
  218. reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
  219. reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
  220. reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
  221. reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
  222. #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
  223. /* Old kernels are hardcoded to P=1 (divide by 2) */
  224. reg_val |= CCM_PLL5_CTRL_P(1);
  225. #endif
  226. if (clk >= 540 && clk < 552) {
  227. /* dram = 540MHz */
  228. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
  229. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
  230. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
  231. } else if (clk >= 512 && clk < 528) {
  232. /* dram = 512MHz */
  233. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
  234. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
  235. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
  236. } else if (clk >= 496 && clk < 504) {
  237. /* dram = 496MHz */
  238. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
  239. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
  240. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
  241. } else if (clk >= 468 && clk < 480) {
  242. /* dram = 468MHz */
  243. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
  244. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
  245. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
  246. } else if (clk >= 396 && clk < 408) {
  247. /* dram = 396MHz */
  248. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
  249. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
  250. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
  251. } else {
  252. /* any other frequency that is a multiple of 24 */
  253. reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
  254. reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
  255. reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
  256. }
  257. reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
  258. reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
  259. writel(reg_val, &ccm->pll5_cfg);
  260. udelay(5500);
  261. setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
  262. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  263. /* reset GPS */
  264. clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
  265. setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
  266. udelay(1);
  267. clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
  268. #endif
  269. /* setup MBUS clock */
  270. if (!mbus_clk)
  271. mbus_clk = 300;
  272. /* PLL5P and PLL6 are the potential clock sources for MBUS */
  273. pll6x_clk = clock_get_pll6() / 1000000;
  274. #ifdef CONFIG_MACH_SUN7I
  275. pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
  276. #endif
  277. pll5p_clk = clock_get_pll5p() / 1000000;
  278. pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
  279. pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
  280. pll6x_rate = pll6x_clk / pll6x_div;
  281. pll5p_rate = pll5p_clk / pll5p_div;
  282. if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
  283. /* use PLL6 as the MBUS clock source */
  284. reg_val = CCM_MBUS_CTRL_GATE |
  285. CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
  286. CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
  287. CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
  288. } else if (pll5p_div <= 16) {
  289. /* use PLL5P as the MBUS clock source */
  290. reg_val = CCM_MBUS_CTRL_GATE |
  291. CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
  292. CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
  293. CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
  294. } else {
  295. panic("Bad mbus_clk\n");
  296. }
  297. writel(reg_val, &ccm->mbus_clk_cfg);
  298. /*
  299. * open DRAMC AHB & DLL register clock
  300. * close it first
  301. */
  302. #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
  303. clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
  304. #else
  305. clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
  306. #endif
  307. udelay(22);
  308. /* then open it */
  309. #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
  310. setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
  311. #else
  312. setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
  313. #endif
  314. udelay(22);
  315. }
  316. /*
  317. * The data from rslrX and rdgrX registers (X=rank) is stored
  318. * in a single 32-bit value using the following format:
  319. * bits [31:26] - DQS gating system latency for byte lane 3
  320. * bits [25:24] - DQS gating phase select for byte lane 3
  321. * bits [23:18] - DQS gating system latency for byte lane 2
  322. * bits [17:16] - DQS gating phase select for byte lane 2
  323. * bits [15:10] - DQS gating system latency for byte lane 1
  324. * bits [ 9:8 ] - DQS gating phase select for byte lane 1
  325. * bits [ 7:2 ] - DQS gating system latency for byte lane 0
  326. * bits [ 1:0 ] - DQS gating phase select for byte lane 0
  327. */
  328. static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
  329. {
  330. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  331. u32 lane, number_of_lanes = mctl_get_number_of_lanes();
  332. /* rank0 gating system latency (3 bits per lane: cycles) */
  333. u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
  334. /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
  335. u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
  336. for (lane = 0; lane < number_of_lanes; lane++) {
  337. u32 tmp = dqs_gating_delay >> (lane * 8);
  338. slr &= ~(7 << (lane * 3));
  339. slr |= ((tmp >> 2) & 7) << (lane * 3);
  340. dgr &= ~(3 << (lane * 2));
  341. dgr |= (tmp & 3) << (lane * 2);
  342. }
  343. writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
  344. writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
  345. }
  346. static int dramc_scan_readpipe(void)
  347. {
  348. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  349. u32 reg_val;
  350. /* data training trigger */
  351. clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
  352. setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
  353. /* check whether data training process has completed */
  354. await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
  355. /* check data training result */
  356. reg_val = readl(&dram->csr);
  357. if (reg_val & DRAM_CSR_FAILED)
  358. return -1;
  359. return 0;
  360. }
  361. static void dramc_clock_output_en(u32 on)
  362. {
  363. #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
  364. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  365. if (on)
  366. setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
  367. else
  368. clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
  369. #endif
  370. #ifdef CONFIG_MACH_SUN4I
  371. struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  372. if (on)
  373. setbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
  374. else
  375. clrbits_le32(&ccm->dram_clk_gate, CCM_DRAM_CTRL_DCLK_OUT);
  376. #endif
  377. }
  378. /* tRFC in nanoseconds for different densities (from the DDR3 spec) */
  379. static const u16 tRFC_DDR3_table[6] = {
  380. /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
  381. 90, 90, 110, 160, 300, 350
  382. };
  383. static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
  384. {
  385. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  386. u32 tRFC, tREFI;
  387. tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
  388. tREFI = (7987 * clk) >> 10; /* <= 7.8us */
  389. writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
  390. }
  391. /* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
  392. static u32 ddr3_write_recovery(u32 clk)
  393. {
  394. u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
  395. u32 twr_ck = (twr_ns * clk + 999) / 1000;
  396. if (twr_ck < 5)
  397. return 1;
  398. else if (twr_ck <= 8)
  399. return twr_ck - 4;
  400. else if (twr_ck <= 10)
  401. return 5;
  402. else
  403. return 6;
  404. }
  405. /*
  406. * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
  407. * means that DRAM is currently in self-refresh mode and retaining the old
  408. * data. Since we have no idea what to do in this situation yet, just set this
  409. * register to 0 and initialize DRAM in the same way as on any normal reboot
  410. * (discarding whatever was stored there).
  411. *
  412. * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
  413. * value for this write operation to have any effect. On sun5i hadware this
  414. * magic value is not necessary. And on sun4i hardware the writes to this
  415. * register seem to have no effect at all.
  416. */
  417. static void mctl_disable_power_save(void)
  418. {
  419. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  420. writel(0x16510000, &dram->ppwrsctl);
  421. }
  422. /*
  423. * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
  424. * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
  425. * (SDR_IDCR) register appears to configure this delay, which gets applied
  426. * right at the time when the DRAM initialization is activated in the
  427. * 'mctl_ddr3_initialize' function.
  428. */
  429. static void mctl_set_cke_delay(void)
  430. {
  431. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  432. /* The CKE delay is represented in DRAM clock cycles, multiplied by N
  433. * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
  434. * the maximum possible value 0x1ffff, just like in the Allwinner's
  435. * boot0 bootloader. The resulting delay value is somewhere between
  436. * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
  437. * with 360 MHz DRAM clock speed). */
  438. setbits_le32(&dram->idcr, 0x1ffff);
  439. }
  440. /*
  441. * This triggers the DRAM initialization. It performs sending the mode registers
  442. * to the DRAM among other things. Very likely the ZQCL command is also getting
  443. * executed (to do the initial impedance calibration on the DRAM side of the
  444. * wire). The memory controller and the PHY must be already configured before
  445. * calling this function.
  446. */
  447. static void mctl_ddr3_initialize(void)
  448. {
  449. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  450. setbits_le32(&dram->ccr, DRAM_CCR_INIT);
  451. await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
  452. }
  453. /*
  454. * Perform impedance calibration on the DRAM controller side of the wire.
  455. */
  456. static void mctl_set_impedance(u32 zq, bool odt_en)
  457. {
  458. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  459. u32 reg_val;
  460. u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
  461. #ifndef CONFIG_MACH_SUN7I
  462. /* Appears that some kind of automatically initiated default
  463. * ZQ calibration is already in progress at this point on sun4i/sun5i
  464. * hardware, but not on sun7i. So it is reasonable to wait for its
  465. * completion before doing anything else. */
  466. await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
  467. #endif
  468. /* ZQ calibration is not really useful unless ODT is enabled */
  469. if (!odt_en)
  470. return;
  471. #ifdef CONFIG_MACH_SUN7I
  472. /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
  473. * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
  474. * SDR_ZQCR1 register, but there are hints indicating that it might
  475. * be related to periodic impedance re-calibration. This particular
  476. * magic value is borrowed from the Allwinner boot0 bootloader, and
  477. * using it helps to avoid troubles */
  478. writel((1 << 24) | (1 << 1), &dram->zqcr1);
  479. #endif
  480. /* Needed at least for sun5i, because it does not self clear there */
  481. clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
  482. if (zdata) {
  483. /* Set the user supplied impedance data */
  484. reg_val = DRAM_ZQCR0_ZDEN | zdata;
  485. writel(reg_val, &dram->zqcr0);
  486. /* no need to wait, this takes effect immediately */
  487. } else {
  488. /* Do the calibration using the external resistor */
  489. reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
  490. writel(reg_val, &dram->zqcr0);
  491. /* Wait for the new impedance configuration to settle */
  492. await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
  493. }
  494. /* Needed at least for sun5i, because it does not self clear there */
  495. clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
  496. /* Set I/O configure register */
  497. writel(DRAM_IOCR_ODT_EN, &dram->iocr);
  498. }
  499. static unsigned long dramc_init_helper(struct dram_para *para)
  500. {
  501. struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
  502. u32 reg_val;
  503. u32 density;
  504. int ret_val;
  505. /*
  506. * only single rank DDR3 is supported by this code even though the
  507. * hardware can theoretically support DDR2 and up to two ranks
  508. */
  509. if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
  510. return 0;
  511. /* setup DRAM relative clock */
  512. mctl_setup_dram_clock(para->clock, para->mbus_clock);
  513. /* Disable any pad power save control */
  514. mctl_disable_power_save();
  515. mctl_set_drive();
  516. /* dram clock off */
  517. dramc_clock_output_en(0);
  518. #ifdef CONFIG_MACH_SUN4I
  519. /* select dram controller 1 */
  520. writel(DRAM_CSEL_MAGIC, &dram->csel);
  521. #endif
  522. mctl_itm_disable();
  523. mctl_enable_dll0(para->tpr3);
  524. /* configure external DRAM */
  525. reg_val = DRAM_DCR_TYPE_DDR3;
  526. reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
  527. if (para->density == 256)
  528. density = DRAM_DCR_CHIP_DENSITY_256M;
  529. else if (para->density == 512)
  530. density = DRAM_DCR_CHIP_DENSITY_512M;
  531. else if (para->density == 1024)
  532. density = DRAM_DCR_CHIP_DENSITY_1024M;
  533. else if (para->density == 2048)
  534. density = DRAM_DCR_CHIP_DENSITY_2048M;
  535. else if (para->density == 4096)
  536. density = DRAM_DCR_CHIP_DENSITY_4096M;
  537. else if (para->density == 8192)
  538. density = DRAM_DCR_CHIP_DENSITY_8192M;
  539. else
  540. density = DRAM_DCR_CHIP_DENSITY_256M;
  541. reg_val |= DRAM_DCR_CHIP_DENSITY(density);
  542. reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
  543. reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
  544. reg_val |= DRAM_DCR_CMD_RANK_ALL;
  545. reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
  546. writel(reg_val, &dram->dcr);
  547. dramc_clock_output_en(1);
  548. mctl_set_impedance(para->zq, para->odt_en);
  549. mctl_set_cke_delay();
  550. mctl_ddr3_reset();
  551. udelay(1);
  552. await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
  553. mctl_enable_dllx(para->tpr3);
  554. /* set refresh period */
  555. dramc_set_autorefresh_cycle(para->clock, density);
  556. /* set timing parameters */
  557. writel(para->tpr0, &dram->tpr0);
  558. writel(para->tpr1, &dram->tpr1);
  559. writel(para->tpr2, &dram->tpr2);
  560. reg_val = DRAM_MR_BURST_LENGTH(0x0);
  561. #if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
  562. reg_val |= DRAM_MR_POWER_DOWN;
  563. #endif
  564. reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
  565. reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
  566. writel(reg_val, &dram->mr);
  567. writel(para->emr1, &dram->emr);
  568. writel(para->emr2, &dram->emr2);
  569. writel(para->emr3, &dram->emr3);
  570. /* disable drift compensation and set passive DQS window mode */
  571. clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
  572. #ifdef CONFIG_MACH_SUN7I
  573. /* Command rate timing mode 2T & 1T */
  574. if (para->tpr4 & 0x1)
  575. setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
  576. #endif
  577. /* initialize external DRAM */
  578. mctl_ddr3_initialize();
  579. /* scan read pipe value */
  580. mctl_itm_enable();
  581. /* Hardware DQS gate training */
  582. ret_val = dramc_scan_readpipe();
  583. if (ret_val < 0)
  584. return 0;
  585. /* allow to override the DQS training results with a custom delay */
  586. if (para->dqs_gating_delay)
  587. mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
  588. /* set the DQS gating window type */
  589. if (para->active_windowing)
  590. clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
  591. else
  592. setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
  593. mctl_itm_reset();
  594. /* configure all host port */
  595. mctl_configure_hostport();
  596. return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
  597. }
  598. unsigned long dramc_init(struct dram_para *para)
  599. {
  600. unsigned long dram_size, actual_density;
  601. /* If the dram configuration is not provided, use a default */
  602. if (!para)
  603. return 0;
  604. /* if everything is known, then autodetection is not necessary */
  605. if (para->io_width && para->bus_width && para->density)
  606. return dramc_init_helper(para);
  607. /* try to autodetect the DRAM bus width and density */
  608. para->io_width = 16;
  609. para->bus_width = 32;
  610. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
  611. /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
  612. para->density = 4096;
  613. #else
  614. /* all A0-A15 address lines on A20, which allow density 8192 */
  615. para->density = 8192;
  616. #endif
  617. dram_size = dramc_init_helper(para);
  618. if (!dram_size) {
  619. /* if 32-bit bus width failed, try 16-bit bus width instead */
  620. para->bus_width = 16;
  621. dram_size = dramc_init_helper(para);
  622. if (!dram_size) {
  623. /* if 16-bit bus width also failed, then bail out */
  624. return dram_size;
  625. }
  626. }
  627. /* check if we need to adjust the density */
  628. actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
  629. if (actual_density != para->density) {
  630. /* update the density and re-initialize DRAM again */
  631. para->density = actual_density;
  632. dram_size = dramc_init_helper(para);
  633. }
  634. return dram_size;
  635. }