rk3368.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  4. * Copyright (c) 2016 Andreas Färber
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <syscon.h>
  9. #include <asm/armv8/mmu.h>
  10. #include <asm/io.h>
  11. #include <asm/arch-rockchip/bootrom.h>
  12. #include <asm/arch-rockchip/clock.h>
  13. #include <asm/arch-rockchip/cru_rk3368.h>
  14. #include <asm/arch-rockchip/grf_rk3368.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <linux/delay.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. #define IMEM_BASE 0xFF8C0000
  19. /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
  20. #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4)
  21. #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
  22. #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
  23. /* exsram may using by mcu to accessing dram(0x0-0x20000000) */
  24. #define MCU_EXSRAM_BASE (0)
  25. #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
  26. #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
  27. /* experi no used, reserved value = 0 */
  28. #define MCU_EXPERI_BASE (0)
  29. #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
  30. #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
  31. static struct mm_region rk3368_mem_map[] = {
  32. {
  33. .virt = 0x0UL,
  34. .phys = 0x0UL,
  35. .size = 0x80000000UL,
  36. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  37. PTE_BLOCK_INNER_SHARE
  38. }, {
  39. .virt = 0xf0000000UL,
  40. .phys = 0xf0000000UL,
  41. .size = 0x10000000UL,
  42. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43. PTE_BLOCK_NON_SHARE |
  44. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  45. }, {
  46. /* List terminator */
  47. 0,
  48. }
  49. };
  50. struct mm_region *mem_map = rk3368_mem_map;
  51. const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
  52. [BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
  53. [BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
  54. };
  55. #ifdef CONFIG_ARCH_EARLY_INIT_R
  56. static int mcu_init(void)
  57. {
  58. struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  59. struct rk3368_cru *cru = rockchip_get_cru();
  60. rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
  61. MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
  62. rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
  63. MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
  64. rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
  65. MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
  66. rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
  67. MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
  68. rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
  69. MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
  70. rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
  71. MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
  72. rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
  73. (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
  74. (5 << MCU_CLK_DIV_SHIFT));
  75. /* mcu dereset, for start running */
  76. rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
  77. return 0;
  78. }
  79. int arch_early_init_r(void)
  80. {
  81. return mcu_init();
  82. }
  83. #endif
  84. #ifdef CONFIG_SPL_BUILD
  85. /*
  86. * The SPL (and also the full U-Boot stage on the RK3368) will run in
  87. * secure mode (i.e. EL3) and an ATF will eventually be booted before
  88. * starting up the operating system... so we can initialize the SGRF
  89. * here and rely on the ATF installing the final (secure) policy
  90. * later.
  91. */
  92. static inline uintptr_t sgrf_soc_con_addr(unsigned int no)
  93. {
  94. const uintptr_t SGRF_BASE =
  95. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  96. return SGRF_BASE + sizeof(u32) * no;
  97. }
  98. static inline uintptr_t sgrf_busdmac_addr(unsigned int no)
  99. {
  100. const uintptr_t SGRF_BASE =
  101. (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
  102. const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
  103. const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
  104. return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
  105. }
  106. static void sgrf_init(void)
  107. {
  108. struct rk3368_cru * const cru =
  109. (struct rk3368_cru * const)rockchip_get_cru();
  110. const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
  111. const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
  112. const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
  113. /* Set all configurable IP to 'non secure'-mode */
  114. rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
  115. rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
  116. rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
  117. /*
  118. * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
  119. * Original comment: "ddr space set no secure mode"
  120. */
  121. rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
  122. rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
  123. rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
  124. /* Set 'secure dma' to 'non secure'-mode */
  125. rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
  126. rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
  127. dsb(); /* barrier */
  128. rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  129. rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  130. dsb(); /* barrier */
  131. udelay(10);
  132. rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
  133. rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
  134. }
  135. int arch_cpu_init(void)
  136. {
  137. /* Reset security, so we can use DMA in the MMC drivers */
  138. sgrf_init();
  139. return 0;
  140. }
  141. #endif
  142. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  143. void board_debug_uart_init(void)
  144. {
  145. /*
  146. * N.B.: This is called before the device-model has been
  147. * initialised. For this reason, we can not access
  148. * the GRF address range using the syscon API.
  149. */
  150. #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
  151. struct rk3368_grf * const grf =
  152. (struct rk3368_grf * const)0xff770000;
  153. enum {
  154. GPIO2D1_MASK = GENMASK(3, 2),
  155. GPIO2D1_GPIO = 0,
  156. GPIO2D1_UART0_SOUT = (1 << 2),
  157. GPIO2D0_MASK = GENMASK(1, 0),
  158. GPIO2D0_GPIO = 0,
  159. GPIO2D0_UART0_SIN = (1 << 0),
  160. };
  161. /* Enable early UART0 on the RK3368 */
  162. rk_clrsetreg(&grf->gpio2d_iomux,
  163. GPIO2D0_MASK, GPIO2D0_UART0_SIN);
  164. rk_clrsetreg(&grf->gpio2d_iomux,
  165. GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
  166. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff1c0000)
  167. struct rk3368_pmu_grf * const pmugrf __maybe_unused =
  168. (struct rk3368_pmu_grf * const)0xff738000;
  169. enum {
  170. /* UART4 */
  171. GPIO0D2_MASK = GENMASK(5, 4),
  172. GPIO0D2_GPIO = 0,
  173. GPIO0D2_UART4_SOUT = (3 << 4),
  174. GPIO0D3_MASK = GENMASK(7, 6),
  175. GPIO0D3_GPIO = 0,
  176. GPIO0D3_UART4_SIN = (3 << 6),
  177. };
  178. /* Enable early UART4 on the PX5 */
  179. rk_clrsetreg(&pmugrf->gpio0d_iomux,
  180. GPIO0D2_MASK | GPIO0D3_MASK,
  181. GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
  182. #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
  183. struct rk3368_grf * const grf =
  184. (struct rk3368_grf * const)0xff770000;
  185. enum {
  186. GPIO2A6_SHIFT = 12,
  187. GPIO2A6_MASK = GENMASK(13, 12),
  188. GPIO2A6_GPIO = 0,
  189. GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
  190. GPIO2A5_SHIFT = 10,
  191. GPIO2A5_MASK = GENMASK(11, 10),
  192. GPIO2A5_GPIO = 0,
  193. GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
  194. };
  195. /* Enable early UART2 on the RK3368 */
  196. rk_clrsetreg(&grf->gpio2a_iomux,
  197. GPIO2A6_MASK, GPIO2A6_UART2_SIN);
  198. rk_clrsetreg(&grf->gpio2a_iomux,
  199. GPIO2A5_MASK, GPIO2A5_UART2_SOUT);
  200. #endif
  201. }
  202. #endif