timer.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  4. *
  5. * Based on original Kirkwood support which is
  6. * Copyright (C) Marvell International Ltd. and its affiliates
  7. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <linux/delay.h>
  14. #define UBOOT_CNTR 0 /* counter to use for uboot timer */
  15. /* Timer reload and current value registers */
  16. struct orion5x_tmr_val {
  17. u32 reload; /* Timer reload reg */
  18. u32 val; /* Timer value reg */
  19. };
  20. /* Timer registers */
  21. struct orion5x_tmr_registers {
  22. u32 ctrl; /* Timer control reg */
  23. u32 pad[3];
  24. struct orion5x_tmr_val tmr[2];
  25. u32 wdt_reload;
  26. u32 wdt_val;
  27. };
  28. struct orion5x_tmr_registers *orion5x_tmr_regs =
  29. (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
  30. /*
  31. * ARM Timers Registers Map
  32. */
  33. #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
  34. #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
  35. #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
  36. /*
  37. * ARM Timers Control Register
  38. * CPU_TIMERS_CTRL_REG (CTCR)
  39. */
  40. #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
  41. #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
  42. #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  43. #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  44. #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
  45. #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
  46. #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  47. #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  48. /*
  49. * ARM Timer\Watchdog Reload Register
  50. * CNTMR_RELOAD_REG (TRR)
  51. */
  52. #define TRG_ARM_TIMER_REL_OFFS 0
  53. #define TRG_ARM_TIMER_REL_MASK 0xffffffff
  54. /*
  55. * ARM Timer\Watchdog Register
  56. * CNTMR_VAL_REG (TVRG)
  57. */
  58. #define TVR_ARM_TIMER_OFFS 0
  59. #define TVR_ARM_TIMER_MASK 0xffffffff
  60. #define TVR_ARM_TIMER_MAX 0xffffffff
  61. #define TIMER_LOAD_VAL 0xffffffff
  62. static inline ulong read_timer(void)
  63. {
  64. return readl(CNTMR_VAL_REG(UBOOT_CNTR))
  65. / (CONFIG_SYS_TCLK / 1000);
  66. }
  67. DECLARE_GLOBAL_DATA_PTR;
  68. #define timestamp gd->arch.tbl
  69. #define lastdec gd->arch.lastinc
  70. static ulong get_timer_masked(void)
  71. {
  72. ulong now = read_timer();
  73. if (lastdec >= now) {
  74. /* normal mode */
  75. timestamp += lastdec - now;
  76. } else {
  77. /* we have an overflow ... */
  78. timestamp += lastdec +
  79. (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  80. }
  81. lastdec = now;
  82. return timestamp;
  83. }
  84. ulong get_timer(ulong base)
  85. {
  86. return get_timer_masked() - base;
  87. }
  88. static inline ulong uboot_cntr_val(void)
  89. {
  90. return readl(CNTMR_VAL_REG(UBOOT_CNTR));
  91. }
  92. void __udelay(unsigned long usec)
  93. {
  94. uint current;
  95. ulong delayticks;
  96. current = uboot_cntr_val();
  97. delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
  98. if (current < delayticks) {
  99. delayticks -= current;
  100. while (uboot_cntr_val() < current)
  101. ;
  102. while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
  103. ;
  104. } else {
  105. while (uboot_cntr_val() > (current - delayticks))
  106. ;
  107. }
  108. }
  109. /*
  110. * init the counter
  111. */
  112. int timer_init(void)
  113. {
  114. unsigned int cntmrctrl;
  115. /* load value into timer */
  116. writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
  117. writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
  118. /* enable timer in auto reload mode */
  119. cntmrctrl = readl(CNTMR_CTRL_REG);
  120. cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
  121. cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
  122. writel(cntmrctrl, CNTMR_CTRL_REG);
  123. return 0;
  124. }
  125. void timer_init_r(void)
  126. {
  127. /* init the timestamp and lastdec value */
  128. lastdec = read_timer();
  129. timestamp = 0;
  130. }
  131. /*
  132. * This function is derived from PowerPC code (read timebase as long long).
  133. * On ARM it just returns the timer value.
  134. */
  135. unsigned long long get_ticks(void)
  136. {
  137. return get_timer(0);
  138. }
  139. /*
  140. * This function is derived from PowerPC code (timebase clock frequency).
  141. * On ARM it returns the number of timer ticks per second.
  142. */
  143. ulong get_tbclk(void)
  144. {
  145. return (ulong)CONFIG_SYS_HZ;
  146. }