hwinit.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Functions for omap5 based boards.
  5. *
  6. * (C) Copyright 2011
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Aneesh V <aneesh@ti.com>
  11. * Steve Sakoman <steve@sakoman.com>
  12. * Sricharan <r.sricharan@ti.com>
  13. */
  14. #include <common.h>
  15. #include <cpu_func.h>
  16. #include <palmas.h>
  17. #include <asm/armv7.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/clock.h>
  21. #include <linux/delay.h>
  22. #include <linux/sizes.h>
  23. #include <asm/utils.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/emif.h>
  26. #include <asm/omap_common.h>
  27. u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  28. #if !CONFIG_IS_ENABLED(DM_GPIO)
  29. static struct gpio_bank gpio_bank_54xx[8] = {
  30. { (void *)OMAP54XX_GPIO1_BASE },
  31. { (void *)OMAP54XX_GPIO2_BASE },
  32. { (void *)OMAP54XX_GPIO3_BASE },
  33. { (void *)OMAP54XX_GPIO4_BASE },
  34. { (void *)OMAP54XX_GPIO5_BASE },
  35. { (void *)OMAP54XX_GPIO6_BASE },
  36. { (void *)OMAP54XX_GPIO7_BASE },
  37. { (void *)OMAP54XX_GPIO8_BASE },
  38. };
  39. const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  40. #endif
  41. void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
  42. {
  43. int i;
  44. struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  45. for (i = 0; i < size; i++, pad++)
  46. writel(pad->val, base + pad->offset);
  47. }
  48. #ifdef CONFIG_SPL_BUILD
  49. /* LPDDR2 specific IO settings */
  50. static void io_settings_lpddr2(void)
  51. {
  52. const struct ctrl_ioregs *ioregs;
  53. get_ioregs(&ioregs);
  54. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  55. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  56. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  57. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  58. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  59. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  60. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  61. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  62. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  63. }
  64. /* DDR3 specific IO settings */
  65. static void io_settings_ddr3(void)
  66. {
  67. u32 io_settings = 0;
  68. const struct ctrl_ioregs *ioregs;
  69. get_ioregs(&ioregs);
  70. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  71. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  72. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  73. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  74. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  75. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  76. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  77. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  78. if (!is_dra7xx()) {
  79. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  80. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  81. }
  82. /* omap5432 does not use lpddr2 */
  83. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  84. writel(ioregs->ctrl_emif_sdram_config_ext,
  85. (*ctrl)->control_emif1_sdram_config_ext);
  86. if (!is_dra72x())
  87. writel(ioregs->ctrl_emif_sdram_config_ext,
  88. (*ctrl)->control_emif2_sdram_config_ext);
  89. if (is_omap54xx()) {
  90. /* Disable DLL select */
  91. io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
  92. & 0xFFEFFFFF);
  93. writel(io_settings,
  94. (*ctrl)->control_port_emif1_sdram_config);
  95. io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
  96. & 0xFFEFFFFF);
  97. writel(io_settings,
  98. (*ctrl)->control_port_emif2_sdram_config);
  99. } else {
  100. writel(ioregs->ctrl_ddr_ctrl_ext_0,
  101. (*ctrl)->control_ddr_control_ext_0);
  102. }
  103. }
  104. /*
  105. * Some tuning of IOs for optimal power and performance
  106. */
  107. void do_io_settings(void)
  108. {
  109. u32 io_settings = 0, mask = 0;
  110. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  111. /* Impedance settings EMMC, C2C 1,2, hsi2 */
  112. mask = (ds_mask << 2) | (ds_mask << 8) |
  113. (ds_mask << 16) | (ds_mask << 18);
  114. io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
  115. (~mask);
  116. io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
  117. (ds_45_ohm << 18) | (ds_60_ohm << 2);
  118. writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
  119. /* Impedance settings Mcspi2 */
  120. mask = (ds_mask << 30);
  121. io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
  122. (~mask);
  123. io_settings |= (ds_60_ohm << 30);
  124. writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
  125. /* Impedance settings C2C 3,4 */
  126. mask = (ds_mask << 14) | (ds_mask << 16);
  127. io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
  128. (~mask);
  129. io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
  130. writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
  131. /* Slew rate settings EMMC, C2C 1,2 */
  132. mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
  133. io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
  134. (~mask);
  135. io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
  136. writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
  137. /* Slew rate settings hsi2, Mcspi2 */
  138. mask = (sc_mask << 24) | (sc_mask << 28);
  139. io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
  140. (~mask);
  141. io_settings |= (sc_fast << 28) | (sc_fast << 24);
  142. writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
  143. /* Slew rate settings C2C 3,4 */
  144. mask = (sc_mask << 16) | (sc_mask << 18);
  145. io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
  146. (~mask);
  147. io_settings |= (sc_na << 16) | (sc_na << 18);
  148. writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
  149. /* impedance and slew rate settings for usb */
  150. mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
  151. (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
  152. io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
  153. (~mask);
  154. io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
  155. (ds_60_ohm << 23) | (sc_fast << 20) |
  156. (sc_fast << 17) | (sc_fast << 14);
  157. writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
  158. if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
  159. io_settings_lpddr2();
  160. else
  161. io_settings_ddr3();
  162. }
  163. static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
  164. {0x45, 0x1}, /* 12 MHz */
  165. {-1, -1}, /* 13 MHz */
  166. {0x63, 0x2}, /* 16.8 MHz */
  167. {0x57, 0x2}, /* 19.2 MHz */
  168. {0x20, 0x1}, /* 26 MHz */
  169. {-1, -1}, /* 27 MHz */
  170. {0x41, 0x3} /* 38.4 MHz */
  171. };
  172. void srcomp_enable(void)
  173. {
  174. u32 srcomp_value, mul_factor, div_factor, clk_val, i;
  175. u32 sysclk_ind = get_sys_clk_index();
  176. u32 omap_rev = omap_revision();
  177. if (!is_omap54xx())
  178. return;
  179. mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
  180. div_factor = srcomp_parameters[sysclk_ind].divide_factor;
  181. for (i = 0; i < 4; i++) {
  182. srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
  183. srcomp_value &=
  184. ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
  185. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  186. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  187. writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
  188. }
  189. if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
  190. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  191. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  192. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  193. for (i = 0; i < 4; i++) {
  194. srcomp_value =
  195. readl((*ctrl)->control_srcomp_north_side + i*4);
  196. srcomp_value &= ~PWRDWN_XS_MASK;
  197. writel(srcomp_value,
  198. (*ctrl)->control_srcomp_north_side + i*4);
  199. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  200. & SRCODE_READ_XS_MASK) >>
  201. SRCODE_READ_XS_SHIFT) == 0)
  202. ;
  203. srcomp_value =
  204. readl((*ctrl)->control_srcomp_north_side + i*4);
  205. srcomp_value &= ~OVERRIDE_XS_MASK;
  206. writel(srcomp_value,
  207. (*ctrl)->control_srcomp_north_side + i*4);
  208. }
  209. } else {
  210. srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
  211. srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
  212. DIVIDE_FACTOR_XS_MASK);
  213. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  214. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  215. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  216. for (i = 0; i < 4; i++) {
  217. srcomp_value =
  218. readl((*ctrl)->control_srcomp_north_side + i*4);
  219. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  220. writel(srcomp_value,
  221. (*ctrl)->control_srcomp_north_side + i*4);
  222. srcomp_value =
  223. readl((*ctrl)->control_srcomp_north_side + i*4);
  224. srcomp_value &= ~OVERRIDE_XS_MASK;
  225. writel(srcomp_value,
  226. (*ctrl)->control_srcomp_north_side + i*4);
  227. }
  228. srcomp_value =
  229. readl((*ctrl)->control_srcomp_east_side_wkup);
  230. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  231. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  232. srcomp_value =
  233. readl((*ctrl)->control_srcomp_east_side_wkup);
  234. srcomp_value &= ~OVERRIDE_XS_MASK;
  235. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  236. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  237. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  238. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  239. clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  240. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  241. writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  242. for (i = 0; i < 4; i++) {
  243. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  244. & SRCODE_READ_XS_MASK) >>
  245. SRCODE_READ_XS_SHIFT) == 0)
  246. ;
  247. srcomp_value =
  248. readl((*ctrl)->control_srcomp_north_side + i*4);
  249. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  250. writel(srcomp_value,
  251. (*ctrl)->control_srcomp_north_side + i*4);
  252. }
  253. while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
  254. SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
  255. ;
  256. srcomp_value =
  257. readl((*ctrl)->control_srcomp_east_side_wkup);
  258. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  259. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  260. }
  261. }
  262. #endif
  263. void config_data_eye_leveling_samples(u32 emif_base)
  264. {
  265. const struct ctrl_ioregs *ioregs;
  266. get_ioregs(&ioregs);
  267. /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
  268. if (emif_base == EMIF1_BASE)
  269. writel(ioregs->ctrl_emif_sdram_config_ext_final,
  270. (*ctrl)->control_emif1_sdram_config_ext);
  271. else if (emif_base == EMIF2_BASE)
  272. writel(ioregs->ctrl_emif_sdram_config_ext_final,
  273. (*ctrl)->control_emif2_sdram_config_ext);
  274. }
  275. void init_cpu_configuration(void)
  276. {
  277. u32 l2actlr;
  278. asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
  279. /*
  280. * L2ACTLR: Ensure to enable the following:
  281. * 3: Disable clean/evict push to external
  282. * 4: Disable WriteUnique and WriteLineUnique transactions from master
  283. * 8: Disable DVM/CMO message broadcast
  284. */
  285. l2actlr |= 0x118;
  286. omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
  287. }
  288. void init_omap_revision(void)
  289. {
  290. /*
  291. * For some of the ES2/ES1 boards ID_CODE is not reliable:
  292. * Also, ES1 and ES2 have different ARM revisions
  293. * So use ARM revision for identification
  294. */
  295. unsigned int rev = cortex_rev();
  296. switch (readl(CONTROL_ID_CODE)) {
  297. case OMAP5430_CONTROL_ID_CODE_ES1_0:
  298. *omap_si_rev = OMAP5430_ES1_0;
  299. if (rev == MIDR_CORTEX_A15_R2P2)
  300. *omap_si_rev = OMAP5430_ES2_0;
  301. break;
  302. case OMAP5432_CONTROL_ID_CODE_ES1_0:
  303. *omap_si_rev = OMAP5432_ES1_0;
  304. if (rev == MIDR_CORTEX_A15_R2P2)
  305. *omap_si_rev = OMAP5432_ES2_0;
  306. break;
  307. case OMAP5430_CONTROL_ID_CODE_ES2_0:
  308. *omap_si_rev = OMAP5430_ES2_0;
  309. break;
  310. case OMAP5432_CONTROL_ID_CODE_ES2_0:
  311. *omap_si_rev = OMAP5432_ES2_0;
  312. break;
  313. case DRA762_CONTROL_ID_CODE_ES1_0:
  314. *omap_si_rev = DRA762_ES1_0;
  315. break;
  316. case DRA752_CONTROL_ID_CODE_ES1_0:
  317. *omap_si_rev = DRA752_ES1_0;
  318. break;
  319. case DRA752_CONTROL_ID_CODE_ES1_1:
  320. *omap_si_rev = DRA752_ES1_1;
  321. break;
  322. case DRA752_CONTROL_ID_CODE_ES2_0:
  323. *omap_si_rev = DRA752_ES2_0;
  324. break;
  325. case DRA722_CONTROL_ID_CODE_ES1_0:
  326. *omap_si_rev = DRA722_ES1_0;
  327. break;
  328. case DRA722_CONTROL_ID_CODE_ES2_0:
  329. *omap_si_rev = DRA722_ES2_0;
  330. break;
  331. case DRA722_CONTROL_ID_CODE_ES2_1:
  332. *omap_si_rev = DRA722_ES2_1;
  333. break;
  334. default:
  335. *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
  336. }
  337. init_cpu_configuration();
  338. }
  339. void init_package_revision(void)
  340. {
  341. unsigned int die_id[4] = { 0 };
  342. u8 package;
  343. omap_die_id(die_id);
  344. package = (die_id[2] >> 16) & 0x3;
  345. if (is_dra76x()) {
  346. switch (package) {
  347. case DRA762_ABZ_PACKAGE:
  348. *omap_si_rev = DRA762_ABZ_ES1_0;
  349. break;
  350. case DRA762_ACD_PACKAGE:
  351. default:
  352. *omap_si_rev = DRA762_ACD_ES1_0;
  353. break;
  354. }
  355. }
  356. }
  357. void omap_die_id(unsigned int *die_id)
  358. {
  359. die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
  360. die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
  361. die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
  362. die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
  363. }
  364. void reset_cpu(ulong ignored)
  365. {
  366. u32 omap_rev = omap_revision();
  367. /*
  368. * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
  369. * So use cold reset in case instead.
  370. */
  371. if (omap_rev == OMAP5430_ES1_0)
  372. writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
  373. else
  374. writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
  375. }
  376. u32 warm_reset(void)
  377. {
  378. return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
  379. }
  380. void setup_warmreset_time(void)
  381. {
  382. u32 rst_time, rst_val;
  383. /*
  384. * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
  385. * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
  386. * into microsec and passing the value.
  387. */
  388. rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
  389. << RSTTIME1_SHIFT;
  390. if (rst_time > RSTTIME1_MASK)
  391. rst_time = RSTTIME1_MASK;
  392. rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
  393. rst_val |= rst_time;
  394. writel(rst_val, (*prcm)->prm_rsttime);
  395. }
  396. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  397. u32 cpu_rev_comb, u32 cpu_variant,
  398. u32 cpu_rev)
  399. {
  400. omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
  401. }
  402. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  403. u32 cpu_variant, u32 cpu_rev)
  404. {
  405. #ifdef CONFIG_ARM_ERRATA_801819
  406. /*
  407. * DRA72x processors are uniprocessors and DONOT have
  408. * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
  409. * Extensions) Hence the erratum workaround is not applicable for
  410. * DRA72x processors.
  411. */
  412. if (is_dra72x())
  413. acr &= ~((0x3 << 23) | (0x3 << 25));
  414. #endif
  415. omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
  416. }
  417. #if defined(CONFIG_PALMAS_POWER)
  418. __weak void board_mmc_poweron_ldo(uint voltage)
  419. {
  420. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  421. }
  422. void vmmc_pbias_config(uint voltage)
  423. {
  424. u32 value = 0;
  425. value = readl((*ctrl)->control_pbias);
  426. value &= ~SDCARD_PWRDNZ;
  427. writel(value, (*ctrl)->control_pbias);
  428. udelay(10); /* wait 10 us */
  429. value &= ~SDCARD_BIAS_PWRDNZ;
  430. writel(value, (*ctrl)->control_pbias);
  431. board_mmc_poweron_ldo(voltage);
  432. value = readl((*ctrl)->control_pbias);
  433. value |= SDCARD_BIAS_PWRDNZ;
  434. writel(value, (*ctrl)->control_pbias);
  435. udelay(150); /* wait 150 us */
  436. value |= SDCARD_PWRDNZ;
  437. writel(value, (*ctrl)->control_pbias);
  438. udelay(150); /* wait 150 us */
  439. }
  440. #endif