hw_data.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * HW data initialization for OMAP5
  5. *
  6. * (C) Copyright 2013
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Sricharan R <r.sricharan@ti.com>
  10. */
  11. #include <common.h>
  12. #include <palmas.h>
  13. #include <asm/arch/omap.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/omap_common.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/omap_gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/emif.h>
  20. struct prcm_regs const **prcm =
  21. (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  22. struct dplls const **dplls_data =
  23. (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  24. struct vcores_data const **omap_vcores =
  25. (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  26. struct omap_sys_ctrl_regs const **ctrl =
  27. (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
  28. /* OPP NOM FREQUENCY for ES1.0 */
  29. static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  30. {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  31. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  32. {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  33. {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  34. {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  35. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  36. {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  37. };
  38. /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
  39. static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  40. {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  41. {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  42. {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  43. {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  44. {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  45. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  46. {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  47. };
  48. static const struct dpll_params
  49. core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  50. {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
  51. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  52. {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
  53. {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
  54. {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
  55. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  56. {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
  57. };
  58. static const struct dpll_params
  59. core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
  60. {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
  61. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  62. {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
  63. {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
  64. {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
  65. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  66. {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
  67. };
  68. static const struct dpll_params
  69. core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
  70. {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
  71. {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
  72. {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
  73. {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
  74. {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
  75. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  76. {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
  77. };
  78. static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
  79. {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
  80. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  81. {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  82. {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  83. {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
  84. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  85. {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
  86. };
  87. static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
  88. {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
  89. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  90. {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  91. {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  92. {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
  93. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  94. {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
  95. };
  96. static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
  97. {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */
  98. {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
  99. {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  100. {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  101. {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */
  102. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  103. {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */
  104. };
  105. static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
  106. {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */
  107. {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */
  108. {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  109. {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  110. {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */
  111. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  112. {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */
  113. };
  114. static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
  115. {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  116. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  117. {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  118. {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  119. {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  120. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  121. {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  122. };
  123. static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
  124. {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  125. {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  126. {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  127. {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  128. {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  129. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  130. {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  131. };
  132. /* ABE M & N values with sys_clk as source */
  133. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  134. static const struct dpll_params
  135. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  136. {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  137. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  138. {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  139. {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  140. {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  141. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  142. {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  143. };
  144. #endif
  145. /* ABE M & N values with 32K clock as source */
  146. #ifndef CONFIG_SYS_OMAP_ABE_SYSCK
  147. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  148. 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
  149. };
  150. #endif
  151. /* ABE M & N values with sysclk2(22.5792 MHz) as input */
  152. static const struct dpll_params
  153. abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
  154. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  155. {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  156. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  157. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  158. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  159. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  160. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  161. };
  162. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  163. {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  164. {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  165. {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  166. {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  167. {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  168. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  169. {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  170. };
  171. static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
  172. {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  173. {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  174. {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  175. {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  176. {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  177. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  178. {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  179. };
  180. static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
  181. {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  182. {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
  183. {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  184. {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  185. {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  186. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  187. {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  188. };
  189. static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
  190. {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
  191. {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
  192. {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  193. {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  194. {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
  195. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  196. {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  197. };
  198. struct dplls omap5_dplls_es1 = {
  199. .mpu = mpu_dpll_params_800mhz,
  200. .core = core_dpll_params_2128mhz_ddr532,
  201. .per = per_dpll_params_768mhz,
  202. .iva = iva_dpll_params_2330mhz,
  203. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  204. .abe = abe_dpll_params_sysclk_196608khz,
  205. #else
  206. .abe = &abe_dpll_params_32k_196608khz,
  207. #endif
  208. .usb = usb_dpll_params_1920mhz,
  209. .ddr = NULL
  210. };
  211. struct dplls omap5_dplls_es2 = {
  212. .mpu = mpu_dpll_params_1ghz,
  213. .core = core_dpll_params_2128mhz_ddr532_es2,
  214. .per = per_dpll_params_768mhz_es2,
  215. .iva = iva_dpll_params_2330mhz,
  216. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  217. .abe = abe_dpll_params_sysclk_196608khz,
  218. #else
  219. .abe = &abe_dpll_params_32k_196608khz,
  220. #endif
  221. .usb = usb_dpll_params_1920mhz,
  222. .ddr = NULL
  223. };
  224. struct dplls dra76x_dplls = {
  225. .mpu = mpu_dpll_params_1ghz,
  226. .core = core_dpll_params_2128mhz_dra7xx,
  227. .per = per_dpll_params_768mhz_dra76x,
  228. .abe = abe_dpll_params_sysclk2_361267khz,
  229. .iva = iva_dpll_params_2330mhz_dra7xx,
  230. .usb = usb_dpll_params_1920mhz,
  231. .ddr = ddr_dpll_params_2664mhz,
  232. .gmac = gmac_dpll_params_2000mhz,
  233. };
  234. struct dplls dra7xx_dplls = {
  235. .mpu = mpu_dpll_params_1ghz,
  236. .core = core_dpll_params_2128mhz_dra7xx,
  237. .per = per_dpll_params_768mhz_dra7xx,
  238. .abe = abe_dpll_params_sysclk2_361267khz,
  239. .iva = iva_dpll_params_2330mhz_dra7xx,
  240. .usb = usb_dpll_params_1920mhz,
  241. .ddr = ddr_dpll_params_2128mhz,
  242. .gmac = gmac_dpll_params_2000mhz,
  243. };
  244. struct dplls dra72x_dplls = {
  245. .mpu = mpu_dpll_params_1ghz,
  246. .core = core_dpll_params_2128mhz_dra7xx,
  247. .per = per_dpll_params_768mhz_dra7xx,
  248. .abe = abe_dpll_params_sysclk2_361267khz,
  249. .iva = iva_dpll_params_2330mhz_dra7xx,
  250. .usb = usb_dpll_params_1920mhz,
  251. .ddr = ddr_dpll_params_2664mhz,
  252. .gmac = gmac_dpll_params_2000mhz,
  253. };
  254. struct pmic_data palmas = {
  255. .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
  256. .step = 10000, /* 10 mV represented in uV */
  257. /*
  258. * Offset codes 1-6 all give the base voltage in Palmas
  259. * Offset code 0 switches OFF the SMPS
  260. */
  261. .start_code = 6,
  262. .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
  263. .pmic_bus_init = sri2c_init,
  264. .pmic_write = omap_vc_bypass_send_value,
  265. .gpio_en = 0,
  266. };
  267. /* The TPS659038 and TPS65917 are software-compatible, use common struct */
  268. struct pmic_data tps659038 = {
  269. .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
  270. .step = 10000, /* 10 mV represented in uV */
  271. /*
  272. * Offset codes 1-6 all give the base voltage in Palmas
  273. * Offset code 0 switches OFF the SMPS
  274. */
  275. .start_code = 6,
  276. .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
  277. .pmic_bus_init = gpi2c_init,
  278. .pmic_write = palmas_i2c_write_u8,
  279. .gpio_en = 0,
  280. };
  281. /* The LP87565*/
  282. struct pmic_data lp87565 = {
  283. .base_offset = LP873X_BUCK_BASE_VOLT_UV,
  284. .step = 5000, /* 5 mV represented in uV */
  285. /*
  286. * Offset codes 0 - 0x13 Invalid.
  287. * Offset codes 0x14 0x17 give 10mV steps
  288. * Offset codes 0x17 through 0x9D give 5mV steps
  289. * So let us start with our operating range from .73V
  290. */
  291. .start_code = 0x17,
  292. .i2c_slave_addr = 0x60,
  293. .pmic_bus_init = gpi2c_init,
  294. .pmic_write = palmas_i2c_write_u8,
  295. };
  296. /* The LP8732 and LP8733 are software-compatible, use common struct */
  297. struct pmic_data lp8733 = {
  298. .base_offset = LP873X_BUCK_BASE_VOLT_UV,
  299. .step = 5000, /* 5 mV represented in uV */
  300. /*
  301. * Offset codes 0 - 0x13 Invalid.
  302. * Offset codes 0x14 0x17 give 10mV steps
  303. * Offset codes 0x17 through 0x9D give 5mV steps
  304. * So let us start with our operating range from .73V
  305. */
  306. .start_code = 0x17,
  307. .i2c_slave_addr = 0x60,
  308. .pmic_bus_init = gpi2c_init,
  309. .pmic_write = palmas_i2c_write_u8,
  310. };
  311. struct vcores_data omap5430_volts = {
  312. .mpu.value[OPP_NOM] = VDD_MPU,
  313. .mpu.addr = SMPS_REG_ADDR_12_MPU,
  314. .mpu.pmic = &palmas,
  315. .core.value[OPP_NOM] = VDD_CORE,
  316. .core.addr = SMPS_REG_ADDR_8_CORE,
  317. .core.pmic = &palmas,
  318. .mm.value[OPP_NOM] = VDD_MM,
  319. .mm.addr = SMPS_REG_ADDR_45_IVA,
  320. .mm.pmic = &palmas,
  321. };
  322. struct vcores_data omap5430_volts_es2 = {
  323. .mpu.value[OPP_NOM] = VDD_MPU_ES2,
  324. .mpu.addr = SMPS_REG_ADDR_12_MPU,
  325. .mpu.pmic = &palmas,
  326. .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  327. .core.value[OPP_NOM] = VDD_CORE_ES2,
  328. .core.addr = SMPS_REG_ADDR_8_CORE,
  329. .core.pmic = &palmas,
  330. .mm.value[OPP_NOM] = VDD_MM_ES2,
  331. .mm.addr = SMPS_REG_ADDR_45_IVA,
  332. .mm.pmic = &palmas,
  333. .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
  334. .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN,
  335. .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
  336. .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
  337. .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
  338. .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN,
  339. .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS,
  340. };
  341. /*
  342. * Enable essential clock domains, modules and
  343. * do some additional special settings needed
  344. */
  345. void enable_basic_clocks(void)
  346. {
  347. u32 const clk_domains_essential[] = {
  348. (*prcm)->cm_l4per_clkstctrl,
  349. (*prcm)->cm_l3init_clkstctrl,
  350. (*prcm)->cm_memif_clkstctrl,
  351. (*prcm)->cm_l4cfg_clkstctrl,
  352. #ifdef CONFIG_DRIVER_TI_CPSW
  353. (*prcm)->cm_gmac_clkstctrl,
  354. #endif
  355. 0
  356. };
  357. u32 const clk_modules_hw_auto_essential[] = {
  358. (*prcm)->cm_l3_gpmc_clkctrl,
  359. (*prcm)->cm_memif_emif_1_clkctrl,
  360. (*prcm)->cm_memif_emif_2_clkctrl,
  361. (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
  362. (*prcm)->cm_wkup_gpio1_clkctrl,
  363. (*prcm)->cm_l4per_gpio2_clkctrl,
  364. (*prcm)->cm_l4per_gpio3_clkctrl,
  365. (*prcm)->cm_l4per_gpio4_clkctrl,
  366. (*prcm)->cm_l4per_gpio5_clkctrl,
  367. (*prcm)->cm_l4per_gpio6_clkctrl,
  368. (*prcm)->cm_l4per_gpio7_clkctrl,
  369. (*prcm)->cm_l4per_gpio8_clkctrl,
  370. #ifdef CONFIG_SCSI_AHCI_PLAT
  371. (*prcm)->cm_l3init_ocp2scp3_clkctrl,
  372. #endif
  373. 0
  374. };
  375. u32 const clk_modules_explicit_en_essential[] = {
  376. (*prcm)->cm_wkup_gptimer1_clkctrl,
  377. (*prcm)->cm_l3init_hsmmc1_clkctrl,
  378. (*prcm)->cm_l3init_hsmmc2_clkctrl,
  379. (*prcm)->cm_l4per_gptimer2_clkctrl,
  380. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  381. (*prcm)->cm_l4per_uart1_clkctrl,
  382. (*prcm)->cm_l4per_uart3_clkctrl,
  383. (*prcm)->cm_l4per_i2c1_clkctrl,
  384. #ifdef CONFIG_DRIVER_TI_CPSW
  385. (*prcm)->cm_gmac_gmac_clkctrl,
  386. #endif
  387. #ifdef CONFIG_TI_QSPI
  388. (*prcm)->cm_l4per_qspi_clkctrl,
  389. #endif
  390. #ifdef CONFIG_SCSI_AHCI_PLAT
  391. (*prcm)->cm_l3init_sata_clkctrl,
  392. #endif
  393. 0
  394. };
  395. /* Enable optional additional functional clock for GPIO4 */
  396. setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
  397. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  398. /* Enable 192 MHz clock for MMC1 & MMC2 */
  399. setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  400. HSMMC_CLKCTRL_CLKSEL_MASK);
  401. setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  402. HSMMC_CLKCTRL_CLKSEL_MASK);
  403. /* Set the correct clock dividers for mmc */
  404. clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  405. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  406. clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  407. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  408. /* Select 32KHz clock as the source of GPTIMER1 */
  409. setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
  410. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  411. do_enable_clocks(clk_domains_essential,
  412. clk_modules_hw_auto_essential,
  413. clk_modules_explicit_en_essential,
  414. 1);
  415. #ifdef CONFIG_TI_QSPI
  416. setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
  417. #endif
  418. #ifdef CONFIG_SCSI_AHCI_PLAT
  419. /* Enable optional functional clock for SATA */
  420. setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
  421. SATA_CLKCTRL_OPTFCLKEN_MASK);
  422. #endif
  423. /* Enable SCRM OPT clocks for PER and CORE dpll */
  424. setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
  425. OPTFCLKEN_SCRM_PER_MASK);
  426. setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
  427. OPTFCLKEN_SCRM_CORE_MASK);
  428. }
  429. void enable_basic_uboot_clocks(void)
  430. {
  431. u32 const clk_domains_essential[] = {
  432. #if defined(CONFIG_DRA7XX)
  433. (*prcm)->cm_ipu_clkstctrl,
  434. #endif
  435. 0
  436. };
  437. u32 const clk_modules_hw_auto_essential[] = {
  438. (*prcm)->cm_l3init_hsusbtll_clkctrl,
  439. 0
  440. };
  441. u32 const clk_modules_explicit_en_essential[] = {
  442. (*prcm)->cm_l4per_mcspi1_clkctrl,
  443. (*prcm)->cm_l4per_i2c2_clkctrl,
  444. (*prcm)->cm_l4per_i2c3_clkctrl,
  445. (*prcm)->cm_l4per_i2c4_clkctrl,
  446. #if defined(CONFIG_DRA7XX)
  447. (*prcm)->cm_ipu_i2c5_clkctrl,
  448. #else
  449. (*prcm)->cm_l4per_i2c5_clkctrl,
  450. #endif
  451. (*prcm)->cm_l3init_hsusbhost_clkctrl,
  452. (*prcm)->cm_l3init_fsusb_clkctrl,
  453. 0
  454. };
  455. do_enable_clocks(clk_domains_essential,
  456. clk_modules_hw_auto_essential,
  457. clk_modules_explicit_en_essential,
  458. 1);
  459. }
  460. #ifdef CONFIG_TI_EDMA3
  461. void enable_edma3_clocks(void)
  462. {
  463. u32 const clk_domains_edma3[] = {
  464. 0
  465. };
  466. u32 const clk_modules_hw_auto_edma3[] = {
  467. (*prcm)->cm_l3main1_tptc1_clkctrl,
  468. (*prcm)->cm_l3main1_tptc2_clkctrl,
  469. 0
  470. };
  471. u32 const clk_modules_explicit_en_edma3[] = {
  472. 0
  473. };
  474. do_enable_clocks(clk_domains_edma3,
  475. clk_modules_hw_auto_edma3,
  476. clk_modules_explicit_en_edma3,
  477. 1);
  478. }
  479. void disable_edma3_clocks(void)
  480. {
  481. u32 const clk_domains_edma3[] = {
  482. 0
  483. };
  484. u32 const clk_modules_disable_edma3[] = {
  485. (*prcm)->cm_l3main1_tptc1_clkctrl,
  486. (*prcm)->cm_l3main1_tptc2_clkctrl,
  487. 0
  488. };
  489. do_disable_clocks(clk_domains_edma3,
  490. clk_modules_disable_edma3,
  491. 1);
  492. }
  493. #endif
  494. #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
  495. void enable_usb_clocks(int index)
  496. {
  497. u32 cm_l3init_usb_otg_ss_clkctrl = 0;
  498. if (index == 0) {
  499. cm_l3init_usb_otg_ss_clkctrl =
  500. (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
  501. /* Enable 960 MHz clock for dwc3 */
  502. setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
  503. OPTFCLKEN_REFCLK960M);
  504. /* Enable 32 KHz clock for USB_PHY1 */
  505. setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
  506. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  507. /* Enable 32 KHz clock for USB_PHY3 */
  508. if (is_dra7xx())
  509. setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
  510. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  511. } else if (index == 1) {
  512. cm_l3init_usb_otg_ss_clkctrl =
  513. (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
  514. /* Enable 960 MHz clock for dwc3 */
  515. setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
  516. OPTFCLKEN_REFCLK960M);
  517. /* Enable 32 KHz clock for dwc3 */
  518. setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
  519. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  520. /* Enable 60 MHz clock for USB2PHY2 */
  521. setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
  522. L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
  523. }
  524. u32 const clk_domains_usb[] = {
  525. 0
  526. };
  527. u32 const clk_modules_hw_auto_usb[] = {
  528. (*prcm)->cm_l3init_ocp2scp1_clkctrl,
  529. cm_l3init_usb_otg_ss_clkctrl,
  530. 0
  531. };
  532. u32 const clk_modules_explicit_en_usb[] = {
  533. 0
  534. };
  535. do_enable_clocks(clk_domains_usb,
  536. clk_modules_hw_auto_usb,
  537. clk_modules_explicit_en_usb,
  538. 1);
  539. }
  540. void disable_usb_clocks(int index)
  541. {
  542. u32 cm_l3init_usb_otg_ss_clkctrl = 0;
  543. if (index == 0) {
  544. cm_l3init_usb_otg_ss_clkctrl =
  545. (*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
  546. /* Disable 960 MHz clock for dwc3 */
  547. clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
  548. OPTFCLKEN_REFCLK960M);
  549. /* Disable 32 KHz clock for USB_PHY1 */
  550. clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
  551. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  552. /* Disable 32 KHz clock for USB_PHY3 */
  553. if (is_dra7xx())
  554. clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
  555. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  556. } else if (index == 1) {
  557. cm_l3init_usb_otg_ss_clkctrl =
  558. (*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
  559. /* Disable 960 MHz clock for dwc3 */
  560. clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
  561. OPTFCLKEN_REFCLK960M);
  562. /* Disable 32 KHz clock for dwc3 */
  563. clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
  564. USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
  565. /* Disable 60 MHz clock for USB2PHY2 */
  566. clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
  567. L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
  568. }
  569. u32 const clk_domains_usb[] = {
  570. 0
  571. };
  572. u32 const clk_modules_disable[] = {
  573. (*prcm)->cm_l3init_ocp2scp1_clkctrl,
  574. cm_l3init_usb_otg_ss_clkctrl,
  575. 0
  576. };
  577. do_disable_clocks(clk_domains_usb,
  578. clk_modules_disable,
  579. 1);
  580. }
  581. #endif
  582. const struct ctrl_ioregs ioregs_omap5430 = {
  583. .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  584. .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  585. .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
  586. .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
  587. .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
  588. };
  589. const struct ctrl_ioregs ioregs_omap5432_es1 = {
  590. .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  591. .ctrl_lpddr2ch = 0x0,
  592. .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  593. .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
  594. .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
  595. .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
  596. .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
  597. .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
  598. };
  599. const struct ctrl_ioregs ioregs_omap5432_es2 = {
  600. .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
  601. .ctrl_lpddr2ch = 0x0,
  602. .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
  603. .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
  604. .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
  605. .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
  606. .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
  607. .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
  608. };
  609. const struct ctrl_ioregs ioregs_dra7xx_es1 = {
  610. .ctrl_ddrch = 0x40404040,
  611. .ctrl_lpddr2ch = 0x40404040,
  612. .ctrl_ddr3ch = 0x80808080,
  613. .ctrl_ddrio_0 = 0x00094A40,
  614. .ctrl_ddrio_1 = 0x04A52000,
  615. .ctrl_ddrio_2 = 0x84210000,
  616. .ctrl_emif_sdram_config_ext = 0x0001C1A7,
  617. .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
  618. .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
  619. };
  620. const struct ctrl_ioregs ioregs_dra72x_es1 = {
  621. .ctrl_ddrch = 0x40404040,
  622. .ctrl_lpddr2ch = 0x40404040,
  623. .ctrl_ddr3ch = 0x60606080,
  624. .ctrl_ddrio_0 = 0x00094A40,
  625. .ctrl_ddrio_1 = 0x04A52000,
  626. .ctrl_ddrio_2 = 0x84210000,
  627. .ctrl_emif_sdram_config_ext = 0x0001C1A7,
  628. .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
  629. .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
  630. };
  631. const struct ctrl_ioregs ioregs_dra72x_es2 = {
  632. .ctrl_ddrch = 0x40404040,
  633. .ctrl_lpddr2ch = 0x40404040,
  634. .ctrl_ddr3ch = 0x60606060,
  635. .ctrl_ddrio_0 = 0x00094A40,
  636. .ctrl_ddrio_1 = 0x00000000,
  637. .ctrl_ddrio_2 = 0x00000000,
  638. .ctrl_emif_sdram_config_ext = 0x0001C1A7,
  639. .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
  640. .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
  641. };
  642. void __weak hw_data_init(void)
  643. {
  644. u32 omap_rev = omap_revision();
  645. switch (omap_rev) {
  646. case OMAP5430_ES1_0:
  647. case OMAP5432_ES1_0:
  648. *prcm = &omap5_es1_prcm;
  649. *dplls_data = &omap5_dplls_es1;
  650. *omap_vcores = &omap5430_volts;
  651. *ctrl = &omap5_ctrl;
  652. break;
  653. case OMAP5430_ES2_0:
  654. case OMAP5432_ES2_0:
  655. *prcm = &omap5_es2_prcm;
  656. *dplls_data = &omap5_dplls_es2;
  657. *omap_vcores = &omap5430_volts_es2;
  658. *ctrl = &omap5_ctrl;
  659. break;
  660. case DRA762_ABZ_ES1_0:
  661. case DRA762_ACD_ES1_0:
  662. case DRA762_ES1_0:
  663. *prcm = &dra7xx_prcm;
  664. *dplls_data = &dra76x_dplls;
  665. *ctrl = &dra7xx_ctrl;
  666. break;
  667. case DRA752_ES1_0:
  668. case DRA752_ES1_1:
  669. case DRA752_ES2_0:
  670. *prcm = &dra7xx_prcm;
  671. *dplls_data = &dra7xx_dplls;
  672. *ctrl = &dra7xx_ctrl;
  673. break;
  674. case DRA722_ES1_0:
  675. case DRA722_ES2_0:
  676. case DRA722_ES2_1:
  677. *prcm = &dra7xx_prcm;
  678. *dplls_data = &dra72x_dplls;
  679. *ctrl = &dra7xx_ctrl;
  680. break;
  681. default:
  682. printf("\n INVALID OMAP REVISION ");
  683. }
  684. }
  685. void get_ioregs(const struct ctrl_ioregs **regs)
  686. {
  687. u32 omap_rev = omap_revision();
  688. switch (omap_rev) {
  689. case OMAP5430_ES1_0:
  690. case OMAP5430_ES2_0:
  691. *regs = &ioregs_omap5430;
  692. break;
  693. case OMAP5432_ES1_0:
  694. *regs = &ioregs_omap5432_es1;
  695. break;
  696. case OMAP5432_ES2_0:
  697. *regs = &ioregs_omap5432_es2;
  698. break;
  699. case DRA752_ES1_0:
  700. case DRA752_ES1_1:
  701. case DRA752_ES2_0:
  702. case DRA762_ES1_0:
  703. case DRA762_ACD_ES1_0:
  704. case DRA762_ABZ_ES1_0:
  705. *regs = &ioregs_dra7xx_es1;
  706. break;
  707. case DRA722_ES1_0:
  708. *regs = &ioregs_dra72x_es1;
  709. break;
  710. case DRA722_ES2_0:
  711. case DRA722_ES2_1:
  712. *regs = &ioregs_dra72x_es2;
  713. break;
  714. default:
  715. printf("\n INVALID OMAP REVISION ");
  716. }
  717. }