emif-common.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * EMIF programming
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. */
  10. #include <common.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <net.h>
  15. #include <asm/emif.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/omap_common.h>
  19. #include <asm/omap_sec_common.h>
  20. #include <asm/utils.h>
  21. #include <linux/compiler.h>
  22. #include <asm/ti-common/ti-edma3.h>
  23. #include <linux/delay.h>
  24. static int emif1_enabled = -1, emif2_enabled = -1;
  25. void set_lpmode_selfrefresh(u32 base)
  26. {
  27. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  28. u32 reg;
  29. reg = readl(&emif->emif_pwr_mgmt_ctrl);
  30. reg &= ~EMIF_REG_LP_MODE_MASK;
  31. reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  32. reg &= ~EMIF_REG_SR_TIM_MASK;
  33. writel(reg, &emif->emif_pwr_mgmt_ctrl);
  34. /* dummy read for the new SR_TIM to be loaded */
  35. readl(&emif->emif_pwr_mgmt_ctrl);
  36. }
  37. void force_emif_self_refresh()
  38. {
  39. set_lpmode_selfrefresh(EMIF1_BASE);
  40. if (!is_dra72x())
  41. set_lpmode_selfrefresh(EMIF2_BASE);
  42. }
  43. inline u32 emif_num(u32 base)
  44. {
  45. if (base == EMIF1_BASE)
  46. return 1;
  47. else if (base == EMIF2_BASE)
  48. return 2;
  49. else
  50. return 0;
  51. }
  52. static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  53. {
  54. u32 mr;
  55. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  56. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  57. writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  58. if (omap_revision() == OMAP4430_ES2_0)
  59. mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  60. else
  61. mr = readl(&emif->emif_lpddr2_mode_reg_data);
  62. debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  63. cs, mr_addr, mr);
  64. if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
  65. ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  66. ((mr & 0xff000000) >> 24) == (mr & 0xff))
  67. return mr & 0xff;
  68. else
  69. return mr;
  70. }
  71. static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  72. {
  73. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  74. mr_addr |= cs << EMIF_REG_CS_SHIFT;
  75. writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  76. writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  77. }
  78. void emif_reset_phy(u32 base)
  79. {
  80. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  81. u32 iodft;
  82. iodft = readl(&emif->emif_iodft_tlgc);
  83. iodft |= EMIF_REG_RESET_PHY_MASK;
  84. writel(iodft, &emif->emif_iodft_tlgc);
  85. }
  86. static void do_lpddr2_init(u32 base, u32 cs)
  87. {
  88. u32 mr_addr;
  89. const struct lpddr2_mr_regs *mr_regs;
  90. get_lpddr2_mr_regs(&mr_regs);
  91. /* Wait till device auto initialization is complete */
  92. while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  93. ;
  94. set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
  95. /*
  96. * tZQINIT = 1 us
  97. * Enough loops assuming a maximum of 2GHz
  98. */
  99. sdelay(2000);
  100. set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
  101. set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
  102. /*
  103. * Enable refresh along with writing MR2
  104. * Encoding of RL in MR2 is (RL - 2)
  105. */
  106. mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  107. set_mr(base, cs, mr_addr, mr_regs->mr2);
  108. if (mr_regs->mr3 > 0)
  109. set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
  110. }
  111. static void lpddr2_init(u32 base, const struct emif_regs *regs)
  112. {
  113. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  114. /* Not NVM */
  115. clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
  116. /*
  117. * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
  118. * when EMIF_SDRAM_CONFIG register is written
  119. */
  120. setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  121. /*
  122. * Set the SDRAM_CONFIG and PHY_CTRL for the
  123. * un-locked frequency & default RL
  124. */
  125. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  126. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  127. do_ext_phy_settings(base, regs);
  128. do_lpddr2_init(base, CS0);
  129. if (regs->sdram_config & EMIF_REG_EBANK_MASK)
  130. do_lpddr2_init(base, CS1);
  131. writel(regs->sdram_config, &emif->emif_sdram_config);
  132. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
  133. /* Enable refresh now */
  134. clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  135. }
  136. __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
  137. {
  138. }
  139. void emif_update_timings(u32 base, const struct emif_regs *regs)
  140. {
  141. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  142. if (!is_dra7xx())
  143. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
  144. else
  145. writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
  146. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
  147. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
  148. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
  149. if (omap_revision() == OMAP4430_ES1_0) {
  150. /* ES1 bug EMIF should be in force idle during freq_update */
  151. writel(0, &emif->emif_pwr_mgmt_ctrl);
  152. } else {
  153. writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
  154. writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
  155. }
  156. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
  157. writel(regs->zq_config, &emif->emif_zq_config);
  158. writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
  159. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
  160. if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
  161. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
  162. &emif->emif_l3_config);
  163. } else if (omap_revision() >= OMAP4460_ES1_0) {
  164. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
  165. &emif->emif_l3_config);
  166. } else {
  167. writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
  168. &emif->emif_l3_config);
  169. }
  170. }
  171. #ifndef CONFIG_OMAP44XX
  172. static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
  173. {
  174. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  175. /* keep sdram in self-refresh */
  176. writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
  177. & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
  178. __udelay(130);
  179. /*
  180. * Set invert_clkout (if activated)--DDR_PHYCTRL_1
  181. * Invert clock adds an additional half cycle delay on the
  182. * command interface. The additional half cycle, is usually
  183. * meant to enable leveling in the situation that DQS is later
  184. * than CK on the board.It also helps provide some additional
  185. * margin for leveling.
  186. */
  187. writel(regs->emif_ddr_phy_ctlr_1,
  188. &emif->emif_ddr_phy_ctrl_1);
  189. writel(regs->emif_ddr_phy_ctlr_1,
  190. &emif->emif_ddr_phy_ctrl_1_shdw);
  191. __udelay(130);
  192. writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
  193. & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
  194. /* Launch Full leveling */
  195. writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
  196. /* Wait till full leveling is complete */
  197. readl(&emif->emif_rd_wr_lvl_ctl);
  198. __udelay(130);
  199. /* Read data eye leveling no of samples */
  200. config_data_eye_leveling_samples(base);
  201. /*
  202. * Launch 8 incremental WR_LVL- to compensate for
  203. * PHY limitation.
  204. */
  205. writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
  206. &emif->emif_rd_wr_lvl_ctl);
  207. __udelay(130);
  208. /* Launch Incremental leveling */
  209. writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
  210. __udelay(130);
  211. }
  212. static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
  213. {
  214. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  215. u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
  216. u32 reg, i, phy;
  217. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[6];
  218. phy = readl(&emif->emif_ddr_phy_ctrl_1);
  219. /* Update PHY_REG_RDDQS_RATIO */
  220. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
  221. if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
  222. for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
  223. reg = readl(emif_phy_status++);
  224. writel(reg, emif_ext_phy_ctrl_reg++);
  225. writel(reg, emif_ext_phy_ctrl_reg++);
  226. }
  227. /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
  228. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
  229. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[11];
  230. if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
  231. for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
  232. reg = readl(emif_phy_status++);
  233. writel(reg, emif_ext_phy_ctrl_reg++);
  234. writel(reg, emif_ext_phy_ctrl_reg++);
  235. }
  236. /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
  237. emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
  238. emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[16];
  239. if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
  240. for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
  241. reg = readl(emif_phy_status++);
  242. writel(reg, emif_ext_phy_ctrl_reg++);
  243. writel(reg, emif_ext_phy_ctrl_reg++);
  244. }
  245. /* Disable Leveling */
  246. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
  247. writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
  248. writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
  249. }
  250. static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
  251. {
  252. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  253. /* Clear Error Status */
  254. clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
  255. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
  256. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
  257. clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
  258. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
  259. EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
  260. /* Disable refreshed before leveling */
  261. clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
  262. EMIF_REG_INITREF_DIS_MASK);
  263. /* Start Full leveling */
  264. writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
  265. __udelay(300);
  266. /* Check for leveling timeout */
  267. if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
  268. printf("Leveling timeout on EMIF%d\n", emif_num(base));
  269. return;
  270. }
  271. /* Enable refreshes after leveling */
  272. clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
  273. debug("HW leveling success\n");
  274. /*
  275. * Update slave ratios in EXT_PHY_CTRLx registers
  276. * as per HW leveling output
  277. */
  278. update_hwleveling_output(base, regs);
  279. }
  280. static void dra7_reset_ddr_data(u32 base, u32 size)
  281. {
  282. #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
  283. enable_edma3_clocks();
  284. edma3_fill(EDMA3_BASE, 1, (void *)base, 0, size);
  285. disable_edma3_clocks();
  286. #else
  287. memset((void *)base, 0, size);
  288. #endif
  289. }
  290. static void dra7_enable_ecc(u32 base, const struct emif_regs *regs)
  291. {
  292. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  293. u32 rgn, rgn_start, size, ctrl_reg;
  294. /* ECC available only on dra76x EMIF1 */
  295. if ((base != EMIF1_BASE) || !is_dra76x())
  296. return;
  297. if (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK) {
  298. /* Disable high-order interleaving */
  299. clrbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
  300. #ifdef CONFIG_DRA7XX
  301. /* Clear the status flags and other history */
  302. writel(readl(&emif->emif_1b_ecc_err_cnt),
  303. &emif->emif_1b_ecc_err_cnt);
  304. writel(0xffffffff, &emif->emif_1b_ecc_err_dist_1);
  305. writel(0x2, &emif->emif_1b_ecc_err_addr_log);
  306. writel(0x1, &emif->emif_2b_ecc_err_addr_log);
  307. writel(EMIF_INT_WR_ECC_ERR_SYS_MASK |
  308. EMIF_INT_TWOBIT_ECC_ERR_SYS_MASK |
  309. EMIF_INT_ONEBIT_ECC_ERR_SYS_MASK,
  310. &emif->emif_irqstatus_sys);
  311. #endif
  312. writel(regs->emif_ecc_address_range_1,
  313. &emif->emif_ecc_address_range_1);
  314. writel(regs->emif_ecc_address_range_2,
  315. &emif->emif_ecc_address_range_2);
  316. /* Disable RMW and ECC verification for read accesses */
  317. ctrl_reg = (regs->emif_ecc_ctrl_reg &
  318. ~EMIF_ECC_REG_RMW_EN_MASK) |
  319. EMIF_ECC_CTRL_REG_ECC_VERIFY_DIS_MASK;
  320. writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
  321. /* Set region1 memory with 0 */
  322. rgn_start = (regs->emif_ecc_address_range_1 &
  323. EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
  324. rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
  325. size = (regs->emif_ecc_address_range_1 &
  326. EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
  327. if (regs->emif_ecc_ctrl_reg &
  328. EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK)
  329. dra7_reset_ddr_data(rgn, size);
  330. /* Set region2 memory with 0 */
  331. rgn_start = (regs->emif_ecc_address_range_2 &
  332. EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16;
  333. rgn = rgn_start + CONFIG_SYS_SDRAM_BASE;
  334. size = (regs->emif_ecc_address_range_2 &
  335. EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start;
  336. if (regs->emif_ecc_ctrl_reg &
  337. EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK)
  338. dra7_reset_ddr_data(rgn, size);
  339. /* Default value enables RMW and ECC verification */
  340. writel(regs->emif_ecc_ctrl_reg, &emif->emif_ecc_ctrl_reg);
  341. }
  342. }
  343. static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
  344. {
  345. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  346. if (warm_reset()) {
  347. emif_reset_phy(base);
  348. writel(0x0, &emif->emif_pwr_mgmt_ctrl);
  349. }
  350. do_ext_phy_settings(base, regs);
  351. writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
  352. &emif->emif_sdram_ref_ctrl);
  353. /* Update timing registers */
  354. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
  355. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
  356. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
  357. writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
  358. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
  359. writel(regs->zq_config, &emif->emif_zq_config);
  360. writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
  361. writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
  362. writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
  363. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  364. writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
  365. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
  366. writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
  367. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  368. __udelay(1000);
  369. writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
  370. if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) {
  371. /*
  372. * Perform Dummy ECC setup just to allow hardware
  373. * leveling of ECC memories
  374. */
  375. if (is_dra76x() && (base == EMIF1_BASE) &&
  376. (regs->emif_ecc_ctrl_reg & EMIF_ECC_CTRL_REG_ECC_EN_MASK)) {
  377. writel(0, &emif->emif_ecc_address_range_1);
  378. writel(0, &emif->emif_ecc_address_range_2);
  379. writel(EMIF_ECC_CTRL_REG_ECC_EN_MASK |
  380. EMIF_ECC_CTRL_REG_ECC_ADDR_RGN_PROT_MASK,
  381. &emif->emif_ecc_ctrl_reg);
  382. }
  383. dra7_ddr3_leveling(base, regs);
  384. /* Disable ECC */
  385. if (is_dra76x())
  386. writel(0, &emif->emif_ecc_ctrl_reg);
  387. }
  388. /* Enable ECC as necessary */
  389. dra7_enable_ecc(base, regs);
  390. }
  391. static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
  392. {
  393. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  394. writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
  395. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  396. /*
  397. * Set SDRAM_CONFIG and PHY control registers to locked frequency
  398. * and RL =7. As the default values of the Mode Registers are not
  399. * defined, contents of mode Registers must be fully initialized.
  400. * H/W takes care of this initialization
  401. */
  402. writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
  403. /* Update timing registers */
  404. writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
  405. writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
  406. writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
  407. writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
  408. writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
  409. writel(regs->sdram_config_init, &emif->emif_sdram_config);
  410. do_ext_phy_settings(base, regs);
  411. writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
  412. omap5_ddr3_leveling(base, regs);
  413. }
  414. static void ddr3_init(u32 base, const struct emif_regs *regs)
  415. {
  416. if (is_omap54xx())
  417. omap5_ddr3_init(base, regs);
  418. else
  419. dra7_ddr3_init(base, regs);
  420. }
  421. #endif
  422. #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  423. #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
  424. /*
  425. * Organization and refresh requirements for LPDDR2 devices of different
  426. * types and densities. Derived from JESD209-2 section 2.4
  427. */
  428. const struct lpddr2_addressing addressing_table[] = {
  429. /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
  430. {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
  431. {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
  432. {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
  433. {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
  434. {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
  435. {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
  436. {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
  437. {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
  438. {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
  439. {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
  440. };
  441. static const u32 lpddr2_density_2_size_in_mbytes[] = {
  442. 8, /* 64Mb */
  443. 16, /* 128Mb */
  444. 32, /* 256Mb */
  445. 64, /* 512Mb */
  446. 128, /* 1Gb */
  447. 256, /* 2Gb */
  448. 512, /* 4Gb */
  449. 1024, /* 8Gb */
  450. 2048, /* 16Gb */
  451. 4096 /* 32Gb */
  452. };
  453. /*
  454. * Calculate the period of DDR clock from frequency value and set the
  455. * denominator and numerator in global variables for easy access later
  456. */
  457. static void set_ddr_clk_period(u32 freq)
  458. {
  459. /*
  460. * period = 1/freq
  461. * period_in_ns = 10^9/freq
  462. */
  463. *T_num = 1000000000;
  464. *T_den = freq;
  465. cancel_out(T_num, T_den, 200);
  466. }
  467. /*
  468. * Convert time in nano seconds to number of cycles of DDR clock
  469. */
  470. static inline u32 ns_2_cycles(u32 ns)
  471. {
  472. return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
  473. }
  474. /*
  475. * ns_2_cycles with the difference that the time passed is 2 times the actual
  476. * value(to avoid fractions). The cycles returned is for the original value of
  477. * the timing parameter
  478. */
  479. static inline u32 ns_x2_2_cycles(u32 ns)
  480. {
  481. return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
  482. }
  483. /*
  484. * Find addressing table index based on the device's type(S2 or S4) and
  485. * density
  486. */
  487. s8 addressing_table_index(u8 type, u8 density, u8 width)
  488. {
  489. u8 index;
  490. if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
  491. return -1;
  492. /*
  493. * Look at the way ADDR_TABLE_INDEX* values have been defined
  494. * in emif.h compared to LPDDR2_DENSITY_* values
  495. * The table is layed out in the increasing order of density
  496. * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
  497. * at the end
  498. */
  499. if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
  500. index = ADDR_TABLE_INDEX1GS2;
  501. else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
  502. index = ADDR_TABLE_INDEX2GS2;
  503. else
  504. index = density;
  505. debug("emif: addressing table index %d\n", index);
  506. return index;
  507. }
  508. /*
  509. * Find the the right timing table from the array of timing
  510. * tables of the device using DDR clock frequency
  511. */
  512. static const struct lpddr2_ac_timings *get_timings_table(const struct
  513. lpddr2_ac_timings *const *device_timings,
  514. u32 freq)
  515. {
  516. u32 i, temp, freq_nearest;
  517. const struct lpddr2_ac_timings *timings = 0;
  518. emif_assert(freq <= MAX_LPDDR2_FREQ);
  519. emif_assert(device_timings);
  520. /*
  521. * Start with the maximum allowed frequency - that is always safe
  522. */
  523. freq_nearest = MAX_LPDDR2_FREQ;
  524. /*
  525. * Find the timings table that has the max frequency value:
  526. * i. Above or equal to the DDR frequency - safe
  527. * ii. The lowest that satisfies condition (i) - optimal
  528. */
  529. for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
  530. temp = device_timings[i]->max_freq;
  531. if ((temp >= freq) && (temp <= freq_nearest)) {
  532. freq_nearest = temp;
  533. timings = device_timings[i];
  534. }
  535. }
  536. debug("emif: timings table: %d\n", freq_nearest);
  537. return timings;
  538. }
  539. /*
  540. * Finds the value of emif_sdram_config_reg
  541. * All parameters are programmed based on the device on CS0.
  542. * If there is a device on CS1, it will be same as that on CS0 or
  543. * it will be NVM. We don't support NVM yet.
  544. * If cs1_device pointer is NULL it is assumed that there is no device
  545. * on CS1
  546. */
  547. static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
  548. const struct lpddr2_device_details *cs1_device,
  549. const struct lpddr2_addressing *addressing,
  550. u8 RL)
  551. {
  552. u32 config_reg = 0;
  553. config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
  554. config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
  555. EMIF_REG_IBANK_POS_SHIFT;
  556. config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
  557. config_reg |= RL << EMIF_REG_CL_SHIFT;
  558. config_reg |= addressing->row_sz[cs0_device->io_width] <<
  559. EMIF_REG_ROWSIZE_SHIFT;
  560. config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
  561. config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
  562. EMIF_REG_EBANK_SHIFT;
  563. config_reg |= addressing->col_sz[cs0_device->io_width] <<
  564. EMIF_REG_PAGESIZE_SHIFT;
  565. return config_reg;
  566. }
  567. static u32 get_sdram_ref_ctrl(u32 freq,
  568. const struct lpddr2_addressing *addressing)
  569. {
  570. u32 ref_ctrl = 0, val = 0, freq_khz;
  571. freq_khz = freq / 1000;
  572. /*
  573. * refresh rate to be set is 'tREFI * freq in MHz
  574. * division by 10000 to account for khz and x10 in t_REFI_us_x10
  575. */
  576. val = addressing->t_REFI_us_x10 * freq_khz / 10000;
  577. ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
  578. return ref_ctrl;
  579. }
  580. static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
  581. const struct lpddr2_min_tck *min_tck,
  582. const struct lpddr2_addressing *addressing)
  583. {
  584. u32 tim1 = 0, val = 0;
  585. val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
  586. tim1 |= val << EMIF_REG_T_WTR_SHIFT;
  587. if (addressing->num_banks == BANKS8)
  588. val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
  589. (4 * (*T_num)) - 1;
  590. else
  591. val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
  592. tim1 |= val << EMIF_REG_T_RRD_SHIFT;
  593. val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
  594. tim1 |= val << EMIF_REG_T_RC_SHIFT;
  595. val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
  596. tim1 |= val << EMIF_REG_T_RAS_SHIFT;
  597. val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
  598. tim1 |= val << EMIF_REG_T_WR_SHIFT;
  599. val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
  600. tim1 |= val << EMIF_REG_T_RCD_SHIFT;
  601. val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
  602. tim1 |= val << EMIF_REG_T_RP_SHIFT;
  603. return tim1;
  604. }
  605. static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
  606. const struct lpddr2_min_tck *min_tck)
  607. {
  608. u32 tim2 = 0, val = 0;
  609. val = max(min_tck->tCKE, timings->tCKE) - 1;
  610. tim2 |= val << EMIF_REG_T_CKE_SHIFT;
  611. val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
  612. tim2 |= val << EMIF_REG_T_RTP_SHIFT;
  613. /*
  614. * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
  615. * same value
  616. */
  617. val = ns_2_cycles(timings->tXSR) - 1;
  618. tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
  619. tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
  620. val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
  621. tim2 |= val << EMIF_REG_T_XP_SHIFT;
  622. return tim2;
  623. }
  624. static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
  625. const struct lpddr2_min_tck *min_tck,
  626. const struct lpddr2_addressing *addressing)
  627. {
  628. u32 tim3 = 0, val = 0;
  629. val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
  630. tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
  631. val = ns_2_cycles(timings->tRFCab) - 1;
  632. tim3 |= val << EMIF_REG_T_RFC_SHIFT;
  633. val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
  634. tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
  635. val = ns_2_cycles(timings->tZQCS) - 1;
  636. tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
  637. val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
  638. tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
  639. return tim3;
  640. }
  641. static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
  642. const struct lpddr2_addressing *addressing,
  643. u8 volt_ramp)
  644. {
  645. u32 zq = 0, val = 0;
  646. if (volt_ramp)
  647. val =
  648. EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
  649. addressing->t_REFI_us_x10;
  650. else
  651. val =
  652. EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
  653. addressing->t_REFI_us_x10;
  654. zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
  655. zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
  656. zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
  657. zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
  658. /*
  659. * Assuming that two chipselects have a single calibration resistor
  660. * If there are indeed two calibration resistors, then this flag should
  661. * be enabled to take advantage of dual calibration feature.
  662. * This data should ideally come from board files. But considering
  663. * that none of the boards today have calibration resistors per CS,
  664. * it would be an unnecessary overhead.
  665. */
  666. zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
  667. zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
  668. zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
  669. return zq;
  670. }
  671. static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
  672. const struct lpddr2_addressing *addressing,
  673. u8 is_derated)
  674. {
  675. u32 alert = 0, interval;
  676. interval =
  677. TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
  678. if (is_derated)
  679. interval *= 4;
  680. alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
  681. alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
  682. alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
  683. alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
  684. alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
  685. alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
  686. return alert;
  687. }
  688. static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
  689. {
  690. u32 idle = 0, val = 0;
  691. if (volt_ramp)
  692. val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
  693. else
  694. /*Maximum value in normal conditions - suggested by hw team */
  695. val = 0x1FF;
  696. idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
  697. idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
  698. return idle;
  699. }
  700. static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
  701. {
  702. u32 phy = 0, val = 0;
  703. phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
  704. if (freq <= 100000000)
  705. val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
  706. else if (freq <= 200000000)
  707. val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
  708. else
  709. val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
  710. phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
  711. /* Other fields are constant magic values. Hardcode them together */
  712. phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
  713. EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
  714. return phy;
  715. }
  716. static u32 get_emif_mem_size(u32 base)
  717. {
  718. u32 size_mbytes = 0, temp;
  719. struct emif_device_details dev_details;
  720. struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
  721. u32 emif_nr = emif_num(base);
  722. emif_reset_phy(base);
  723. dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
  724. &cs0_dev_details);
  725. dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
  726. &cs1_dev_details);
  727. emif_reset_phy(base);
  728. if (dev_details.cs0_device_details) {
  729. temp = dev_details.cs0_device_details->density;
  730. size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
  731. }
  732. if (dev_details.cs1_device_details) {
  733. temp = dev_details.cs1_device_details->density;
  734. size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
  735. }
  736. /* convert to bytes */
  737. return size_mbytes << 20;
  738. }
  739. /* Gets the encoding corresponding to a given DMM section size */
  740. u32 get_dmm_section_size_map(u32 section_size)
  741. {
  742. /*
  743. * Section size mapping:
  744. * 0x0: 16-MiB section
  745. * 0x1: 32-MiB section
  746. * 0x2: 64-MiB section
  747. * 0x3: 128-MiB section
  748. * 0x4: 256-MiB section
  749. * 0x5: 512-MiB section
  750. * 0x6: 1-GiB section
  751. * 0x7: 2-GiB section
  752. */
  753. section_size >>= 24; /* divide by 16 MB */
  754. return log_2_n_round_down(section_size);
  755. }
  756. static void emif_calculate_regs(
  757. const struct emif_device_details *emif_dev_details,
  758. u32 freq, struct emif_regs *regs)
  759. {
  760. u32 temp, sys_freq;
  761. const struct lpddr2_addressing *addressing;
  762. const struct lpddr2_ac_timings *timings;
  763. const struct lpddr2_min_tck *min_tck;
  764. const struct lpddr2_device_details *cs0_dev_details =
  765. emif_dev_details->cs0_device_details;
  766. const struct lpddr2_device_details *cs1_dev_details =
  767. emif_dev_details->cs1_device_details;
  768. const struct lpddr2_device_timings *cs0_dev_timings =
  769. emif_dev_details->cs0_device_timings;
  770. emif_assert(emif_dev_details);
  771. emif_assert(regs);
  772. /*
  773. * You can not have a device on CS1 without one on CS0
  774. * So configuring EMIF without a device on CS0 doesn't
  775. * make sense
  776. */
  777. emif_assert(cs0_dev_details);
  778. emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
  779. /*
  780. * If there is a device on CS1 it should be same type as CS0
  781. * (or NVM. But NVM is not supported in this driver yet)
  782. */
  783. emif_assert((cs1_dev_details == NULL) ||
  784. (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
  785. (cs0_dev_details->type == cs1_dev_details->type));
  786. emif_assert(freq <= MAX_LPDDR2_FREQ);
  787. set_ddr_clk_period(freq);
  788. /*
  789. * The device on CS0 is used for all timing calculations
  790. * There is only one set of registers for timings per EMIF. So, if the
  791. * second CS(CS1) has a device, it should have the same timings as the
  792. * device on CS0
  793. */
  794. timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
  795. emif_assert(timings);
  796. min_tck = cs0_dev_timings->min_tck;
  797. temp = addressing_table_index(cs0_dev_details->type,
  798. cs0_dev_details->density,
  799. cs0_dev_details->io_width);
  800. emif_assert((temp >= 0));
  801. addressing = &(addressing_table[temp]);
  802. emif_assert(addressing);
  803. sys_freq = get_sys_clk_freq();
  804. regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
  805. cs1_dev_details,
  806. addressing, RL_BOOT);
  807. regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
  808. cs1_dev_details,
  809. addressing, RL_FINAL);
  810. regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
  811. regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
  812. regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
  813. regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
  814. regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
  815. regs->temp_alert_config =
  816. get_temp_alert_config(cs1_dev_details, addressing, 0);
  817. regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
  818. LPDDR2_VOLTAGE_STABLE);
  819. regs->emif_ddr_phy_ctlr_1_init =
  820. get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
  821. regs->emif_ddr_phy_ctlr_1 =
  822. get_ddr_phy_ctrl_1(freq, RL_FINAL);
  823. regs->freq = freq;
  824. print_timing_reg(regs->sdram_config_init);
  825. print_timing_reg(regs->sdram_config);
  826. print_timing_reg(regs->ref_ctrl);
  827. print_timing_reg(regs->sdram_tim1);
  828. print_timing_reg(regs->sdram_tim2);
  829. print_timing_reg(regs->sdram_tim3);
  830. print_timing_reg(regs->read_idle_ctrl);
  831. print_timing_reg(regs->temp_alert_config);
  832. print_timing_reg(regs->zq_config);
  833. print_timing_reg(regs->emif_ddr_phy_ctlr_1);
  834. print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
  835. }
  836. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  837. #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
  838. const char *get_lpddr2_type(u8 type_id)
  839. {
  840. switch (type_id) {
  841. case LPDDR2_TYPE_S4:
  842. return "LPDDR2-S4";
  843. case LPDDR2_TYPE_S2:
  844. return "LPDDR2-S2";
  845. default:
  846. return NULL;
  847. }
  848. }
  849. const char *get_lpddr2_io_width(u8 width_id)
  850. {
  851. switch (width_id) {
  852. case LPDDR2_IO_WIDTH_8:
  853. return "x8";
  854. case LPDDR2_IO_WIDTH_16:
  855. return "x16";
  856. case LPDDR2_IO_WIDTH_32:
  857. return "x32";
  858. default:
  859. return NULL;
  860. }
  861. }
  862. const char *get_lpddr2_manufacturer(u32 manufacturer)
  863. {
  864. switch (manufacturer) {
  865. case LPDDR2_MANUFACTURER_SAMSUNG:
  866. return "Samsung";
  867. case LPDDR2_MANUFACTURER_QIMONDA:
  868. return "Qimonda";
  869. case LPDDR2_MANUFACTURER_ELPIDA:
  870. return "Elpida";
  871. case LPDDR2_MANUFACTURER_ETRON:
  872. return "Etron";
  873. case LPDDR2_MANUFACTURER_NANYA:
  874. return "Nanya";
  875. case LPDDR2_MANUFACTURER_HYNIX:
  876. return "Hynix";
  877. case LPDDR2_MANUFACTURER_MOSEL:
  878. return "Mosel";
  879. case LPDDR2_MANUFACTURER_WINBOND:
  880. return "Winbond";
  881. case LPDDR2_MANUFACTURER_ESMT:
  882. return "ESMT";
  883. case LPDDR2_MANUFACTURER_SPANSION:
  884. return "Spansion";
  885. case LPDDR2_MANUFACTURER_SST:
  886. return "SST";
  887. case LPDDR2_MANUFACTURER_ZMOS:
  888. return "ZMOS";
  889. case LPDDR2_MANUFACTURER_INTEL:
  890. return "Intel";
  891. case LPDDR2_MANUFACTURER_NUMONYX:
  892. return "Numonyx";
  893. case LPDDR2_MANUFACTURER_MICRON:
  894. return "Micron";
  895. default:
  896. return NULL;
  897. }
  898. }
  899. static void display_sdram_details(u32 emif_nr, u32 cs,
  900. struct lpddr2_device_details *device)
  901. {
  902. const char *mfg_str;
  903. const char *type_str;
  904. char density_str[10];
  905. u32 density;
  906. debug("EMIF%d CS%d\t", emif_nr, cs);
  907. if (!device) {
  908. debug("None\n");
  909. return;
  910. }
  911. mfg_str = get_lpddr2_manufacturer(device->manufacturer);
  912. type_str = get_lpddr2_type(device->type);
  913. density = lpddr2_density_2_size_in_mbytes[device->density];
  914. if ((density / 1024 * 1024) == density) {
  915. density /= 1024;
  916. sprintf(density_str, "%d GB", density);
  917. } else
  918. sprintf(density_str, "%d MB", density);
  919. if (mfg_str && type_str)
  920. debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
  921. }
  922. static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
  923. struct lpddr2_device_details *lpddr2_device)
  924. {
  925. u32 mr = 0, temp;
  926. mr = get_mr(base, cs, LPDDR2_MR0);
  927. if (mr > 0xFF) {
  928. /* Mode register value bigger than 8 bit */
  929. return 0;
  930. }
  931. temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
  932. if (temp) {
  933. /* Not SDRAM */
  934. return 0;
  935. }
  936. temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
  937. if (temp) {
  938. /* DNV supported - But DNV is only supported for NVM */
  939. return 0;
  940. }
  941. mr = get_mr(base, cs, LPDDR2_MR4);
  942. if (mr > 0xFF) {
  943. /* Mode register value bigger than 8 bit */
  944. return 0;
  945. }
  946. mr = get_mr(base, cs, LPDDR2_MR5);
  947. if (mr > 0xFF) {
  948. /* Mode register value bigger than 8 bit */
  949. return 0;
  950. }
  951. if (!get_lpddr2_manufacturer(mr)) {
  952. /* Manufacturer not identified */
  953. return 0;
  954. }
  955. lpddr2_device->manufacturer = mr;
  956. mr = get_mr(base, cs, LPDDR2_MR6);
  957. if (mr >= 0xFF) {
  958. /* Mode register value bigger than 8 bit */
  959. return 0;
  960. }
  961. mr = get_mr(base, cs, LPDDR2_MR7);
  962. if (mr >= 0xFF) {
  963. /* Mode register value bigger than 8 bit */
  964. return 0;
  965. }
  966. mr = get_mr(base, cs, LPDDR2_MR8);
  967. if (mr >= 0xFF) {
  968. /* Mode register value bigger than 8 bit */
  969. return 0;
  970. }
  971. temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
  972. if (!get_lpddr2_type(temp)) {
  973. /* Not SDRAM */
  974. return 0;
  975. }
  976. lpddr2_device->type = temp;
  977. temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
  978. if (temp > LPDDR2_DENSITY_32Gb) {
  979. /* Density not supported */
  980. return 0;
  981. }
  982. lpddr2_device->density = temp;
  983. temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
  984. if (!get_lpddr2_io_width(temp)) {
  985. /* IO width unsupported value */
  986. return 0;
  987. }
  988. lpddr2_device->io_width = temp;
  989. /*
  990. * If all the above tests pass we should
  991. * have a device on this chip-select
  992. */
  993. return 1;
  994. }
  995. struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
  996. struct lpddr2_device_details *lpddr2_dev_details)
  997. {
  998. u32 phy;
  999. u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
  1000. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  1001. if (!lpddr2_dev_details)
  1002. return NULL;
  1003. /* Do the minimum init for mode register accesses */
  1004. if (!(running_from_sdram() || warm_reset())) {
  1005. phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
  1006. writel(phy, &emif->emif_ddr_phy_ctrl_1);
  1007. }
  1008. if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
  1009. return NULL;
  1010. display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
  1011. return lpddr2_dev_details;
  1012. }
  1013. #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
  1014. static void do_sdram_init(u32 base)
  1015. {
  1016. const struct emif_regs *regs;
  1017. u32 in_sdram, emif_nr;
  1018. debug(">>do_sdram_init() %x\n", base);
  1019. in_sdram = running_from_sdram();
  1020. emif_nr = (base == EMIF1_BASE) ? 1 : 2;
  1021. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1022. emif_get_reg_dump(emif_nr, &regs);
  1023. if (!regs) {
  1024. debug("EMIF: reg dump not provided\n");
  1025. return;
  1026. }
  1027. #else
  1028. /*
  1029. * The user has not provided the register values. We need to
  1030. * calculate it based on the timings and the DDR frequency
  1031. */
  1032. struct emif_device_details dev_details;
  1033. struct emif_regs calculated_regs;
  1034. /*
  1035. * Get device details:
  1036. * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
  1037. * - Obtained from user otherwise
  1038. */
  1039. struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
  1040. emif_reset_phy(base);
  1041. dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
  1042. &cs0_dev_details);
  1043. dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
  1044. &cs1_dev_details);
  1045. emif_reset_phy(base);
  1046. /* Return if no devices on this EMIF */
  1047. if (!dev_details.cs0_device_details &&
  1048. !dev_details.cs1_device_details) {
  1049. return;
  1050. }
  1051. /*
  1052. * Get device timings:
  1053. * - Default timings specified by JESD209-2 if
  1054. * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
  1055. * - Obtained from user otherwise
  1056. */
  1057. emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
  1058. &dev_details.cs1_device_timings);
  1059. /* Calculate the register values */
  1060. emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
  1061. regs = &calculated_regs;
  1062. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  1063. /*
  1064. * Initializing the DDR device can not happen from SDRAM.
  1065. * Changing the timing registers in EMIF can happen(going from one
  1066. * OPP to another)
  1067. */
  1068. if (!in_sdram && (!warm_reset() || is_dra7xx())) {
  1069. if (emif_sdram_type(regs->sdram_config) ==
  1070. EMIF_SDRAM_TYPE_LPDDR2)
  1071. lpddr2_init(base, regs);
  1072. #ifndef CONFIG_OMAP44XX
  1073. else
  1074. ddr3_init(base, regs);
  1075. #endif
  1076. }
  1077. #ifdef CONFIG_OMAP54XX
  1078. if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
  1079. EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
  1080. set_lpmode_selfrefresh(base);
  1081. emif_reset_phy(base);
  1082. omap5_ddr3_leveling(base, regs);
  1083. }
  1084. #endif
  1085. /* Write to the shadow registers */
  1086. emif_update_timings(base, regs);
  1087. debug("<<do_sdram_init() %x\n", base);
  1088. }
  1089. void emif_post_init_config(u32 base)
  1090. {
  1091. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  1092. u32 omap_rev = omap_revision();
  1093. /* reset phy on ES2.0 */
  1094. if (omap_rev == OMAP4430_ES2_0)
  1095. emif_reset_phy(base);
  1096. /* Put EMIF back in smart idle on ES1.0 */
  1097. if (omap_rev == OMAP4430_ES1_0)
  1098. writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
  1099. }
  1100. void dmm_init(u32 base)
  1101. {
  1102. const struct dmm_lisa_map_regs *lisa_map_regs;
  1103. u32 i, section, valid;
  1104. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  1105. emif_get_dmm_regs(&lisa_map_regs);
  1106. #else
  1107. u32 emif1_size, emif2_size, mapped_size, section_map = 0;
  1108. u32 section_cnt, sys_addr;
  1109. struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
  1110. mapped_size = 0;
  1111. section_cnt = 3;
  1112. sys_addr = CONFIG_SYS_SDRAM_BASE;
  1113. emif1_size = get_emif_mem_size(EMIF1_BASE);
  1114. emif2_size = get_emif_mem_size(EMIF2_BASE);
  1115. debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
  1116. if (!emif1_size && !emif2_size)
  1117. return;
  1118. /* symmetric interleaved section */
  1119. if (emif1_size && emif2_size) {
  1120. mapped_size = min(emif1_size, emif2_size);
  1121. section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
  1122. section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
  1123. /* only MSB */
  1124. section_map |= (sys_addr >> 24) <<
  1125. EMIF_SYS_ADDR_SHIFT;
  1126. section_map |= get_dmm_section_size_map(mapped_size * 2)
  1127. << EMIF_SYS_SIZE_SHIFT;
  1128. lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
  1129. emif1_size -= mapped_size;
  1130. emif2_size -= mapped_size;
  1131. sys_addr += (mapped_size * 2);
  1132. section_cnt--;
  1133. }
  1134. /*
  1135. * Single EMIF section(we can have a maximum of 1 single EMIF
  1136. * section- either EMIF1 or EMIF2 or none, but not both)
  1137. */
  1138. if (emif1_size) {
  1139. section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
  1140. section_map |= get_dmm_section_size_map(emif1_size)
  1141. << EMIF_SYS_SIZE_SHIFT;
  1142. /* only MSB */
  1143. section_map |= (mapped_size >> 24) <<
  1144. EMIF_SDRC_ADDR_SHIFT;
  1145. /* only MSB */
  1146. section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
  1147. section_cnt--;
  1148. }
  1149. if (emif2_size) {
  1150. section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
  1151. section_map |= get_dmm_section_size_map(emif2_size) <<
  1152. EMIF_SYS_SIZE_SHIFT;
  1153. /* only MSB */
  1154. section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
  1155. /* only MSB */
  1156. section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
  1157. section_cnt--;
  1158. }
  1159. if (section_cnt == 2) {
  1160. /* Only 1 section - either symmetric or single EMIF */
  1161. lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
  1162. lis_map_regs_calculated.dmm_lisa_map_2 = 0;
  1163. lis_map_regs_calculated.dmm_lisa_map_1 = 0;
  1164. } else {
  1165. /* 2 sections - 1 symmetric, 1 single EMIF */
  1166. lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
  1167. lis_map_regs_calculated.dmm_lisa_map_1 = 0;
  1168. }
  1169. /* TRAP for invalid TILER mappings in section 0 */
  1170. lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
  1171. if (omap_revision() >= OMAP4460_ES1_0)
  1172. lis_map_regs_calculated.is_ma_present = 1;
  1173. lisa_map_regs = &lis_map_regs_calculated;
  1174. #endif
  1175. struct dmm_lisa_map_regs *hw_lisa_map_regs =
  1176. (struct dmm_lisa_map_regs *)base;
  1177. writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
  1178. writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
  1179. writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
  1180. writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
  1181. writel(lisa_map_regs->dmm_lisa_map_3,
  1182. &hw_lisa_map_regs->dmm_lisa_map_3);
  1183. writel(lisa_map_regs->dmm_lisa_map_2,
  1184. &hw_lisa_map_regs->dmm_lisa_map_2);
  1185. writel(lisa_map_regs->dmm_lisa_map_1,
  1186. &hw_lisa_map_regs->dmm_lisa_map_1);
  1187. writel(lisa_map_regs->dmm_lisa_map_0,
  1188. &hw_lisa_map_regs->dmm_lisa_map_0);
  1189. if (lisa_map_regs->is_ma_present) {
  1190. hw_lisa_map_regs =
  1191. (struct dmm_lisa_map_regs *)MA_BASE;
  1192. writel(lisa_map_regs->dmm_lisa_map_3,
  1193. &hw_lisa_map_regs->dmm_lisa_map_3);
  1194. writel(lisa_map_regs->dmm_lisa_map_2,
  1195. &hw_lisa_map_regs->dmm_lisa_map_2);
  1196. writel(lisa_map_regs->dmm_lisa_map_1,
  1197. &hw_lisa_map_regs->dmm_lisa_map_1);
  1198. writel(lisa_map_regs->dmm_lisa_map_0,
  1199. &hw_lisa_map_regs->dmm_lisa_map_0);
  1200. setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
  1201. }
  1202. /*
  1203. * EMIF should be configured only when
  1204. * memory is mapped on it. Using emif1_enabled
  1205. * and emif2_enabled variables for this.
  1206. */
  1207. emif1_enabled = 0;
  1208. emif2_enabled = 0;
  1209. for (i = 0; i < 4; i++) {
  1210. section = __raw_readl(DMM_BASE + i*4);
  1211. valid = (section & EMIF_SDRC_MAP_MASK) >>
  1212. (EMIF_SDRC_MAP_SHIFT);
  1213. if (valid == 3) {
  1214. emif1_enabled = 1;
  1215. emif2_enabled = 1;
  1216. break;
  1217. }
  1218. if (valid == 1)
  1219. emif1_enabled = 1;
  1220. if (valid == 2)
  1221. emif2_enabled = 1;
  1222. }
  1223. }
  1224. static void do_bug0039_workaround(u32 base)
  1225. {
  1226. u32 val, i, clkctrl;
  1227. struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
  1228. const struct read_write_regs *bug_00339_regs;
  1229. u32 iterations;
  1230. u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
  1231. u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
  1232. if (is_dra7xx())
  1233. phy_status_base++;
  1234. bug_00339_regs = get_bug_regs(&iterations);
  1235. /* Put EMIF in to idle */
  1236. clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
  1237. __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
  1238. /* Copy the phy status registers in to phy ctrl shadow registers */
  1239. for (i = 0; i < iterations; i++) {
  1240. val = __raw_readl(phy_status_base +
  1241. bug_00339_regs[i].read_reg - 1);
  1242. __raw_writel(val, phy_ctrl_base +
  1243. ((bug_00339_regs[i].write_reg - 1) << 1));
  1244. __raw_writel(val, phy_ctrl_base +
  1245. (bug_00339_regs[i].write_reg << 1) - 1);
  1246. }
  1247. /* Disable leveling */
  1248. writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
  1249. __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
  1250. }
  1251. /*
  1252. * SDRAM initialization:
  1253. * SDRAM initialization has two parts:
  1254. * 1. Configuring the SDRAM device
  1255. * 2. Update the AC timings related parameters in the EMIF module
  1256. * (1) should be done only once and should not be done while we are
  1257. * running from SDRAM.
  1258. * (2) can and should be done more than once if OPP changes.
  1259. * Particularly, this may be needed when we boot without SPL and
  1260. * and using Configuration Header(CH). ROM code supports only at 50% OPP
  1261. * at boot (low power boot). So u-boot has to switch to OPP100 and update
  1262. * the frequency. So,
  1263. * Doing (1) and (2) makes sense - first time initialization
  1264. * Doing (2) and not (1) makes sense - OPP change (when using CH)
  1265. * Doing (1) and not (2) doen't make sense
  1266. * See do_sdram_init() for the details
  1267. */
  1268. void sdram_init(void)
  1269. {
  1270. u32 in_sdram, size_prog, size_detect;
  1271. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  1272. u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
  1273. debug(">>sdram_init()\n");
  1274. if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
  1275. return;
  1276. in_sdram = running_from_sdram();
  1277. debug("in_sdram = %d\n", in_sdram);
  1278. if (!in_sdram) {
  1279. if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
  1280. bypass_dpll((*prcm)->cm_clkmode_dpll_core);
  1281. else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
  1282. writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
  1283. }
  1284. if (!in_sdram)
  1285. dmm_init(DMM_BASE);
  1286. if (emif1_enabled)
  1287. do_sdram_init(EMIF1_BASE);
  1288. if (emif2_enabled)
  1289. do_sdram_init(EMIF2_BASE);
  1290. if (!(in_sdram || warm_reset())) {
  1291. if (emif1_enabled)
  1292. emif_post_init_config(EMIF1_BASE);
  1293. if (emif2_enabled)
  1294. emif_post_init_config(EMIF2_BASE);
  1295. }
  1296. /* for the shadow registers to take effect */
  1297. if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
  1298. freq_update_core();
  1299. /* Do some testing after the init */
  1300. if (!in_sdram) {
  1301. size_prog = omap_sdram_size();
  1302. size_prog = log_2_n_round_down(size_prog);
  1303. size_prog = (1 << size_prog);
  1304. size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  1305. size_prog);
  1306. /* Compare with the size programmed */
  1307. if (size_detect != size_prog) {
  1308. printf("SDRAM: identified size not same as expected"
  1309. " size identified: %x expected: %x\n",
  1310. size_detect,
  1311. size_prog);
  1312. } else
  1313. debug("get_ram_size() successful");
  1314. }
  1315. #if defined(CONFIG_TI_SECURE_DEVICE)
  1316. /*
  1317. * On HS devices, do static EMIF firewall configuration
  1318. * but only do it if not already running in SDRAM
  1319. */
  1320. if (!in_sdram)
  1321. if (0 != secure_emif_reserve())
  1322. hang();
  1323. /* On HS devices, ensure static EMIF firewall APIs are locked */
  1324. if (0 != secure_emif_firewall_lock())
  1325. hang();
  1326. #endif
  1327. if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
  1328. (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
  1329. if (emif1_enabled)
  1330. do_bug0039_workaround(EMIF1_BASE);
  1331. if (emif2_enabled)
  1332. do_bug0039_workaround(EMIF2_BASE);
  1333. }
  1334. debug("<<sdram_init()\n");
  1335. }