sys_env_lib.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/soc.h>
  10. #include "seq_exec.h"
  11. #include "sys_env_lib.h"
  12. #ifdef CONFIG_ARMADA_38X
  13. enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
  14. /* 6820 6810 6811 6828 */
  15. /* PEX_UNIT_ID */ { 4, 3, 3, 4},
  16. /* ETH_GIG_UNIT_ID */ { 3, 2, 3, 3},
  17. /* USB3H_UNIT_ID */ { 2, 2, 2, 2},
  18. /* USB3D_UNIT_ID */ { 1, 1, 1, 1},
  19. /* SATA_UNIT_ID */ { 2, 2, 2, 4},
  20. /* QSGMII_UNIT_ID */ { 1, 0, 0, 1},
  21. /* XAUI_UNIT_ID */ { 0, 0, 0, 0},
  22. /* RXAUI_UNIT_ID */ { 0, 0, 0, 0}
  23. };
  24. #else /* if (CONFIG_ARMADA_39X) */
  25. enum unit_id sys_env_soc_unit_nums[MAX_UNITS_ID][MAX_DEV_ID_NUM] = {
  26. /* 6920 6928 */
  27. /* PEX_UNIT_ID */ { 4, 4},
  28. /* ETH_GIG_UNIT_ID */ { 3, 4},
  29. /* USB3H_UNIT_ID */ { 1, 2},
  30. /* USB3D_UNIT_ID */ { 0, 1},
  31. /* SATA_UNIT_ID */ { 0, 4},
  32. /* QSGMII_UNIT_ID */ { 0, 1},
  33. /* XAUI_UNIT_ID */ { 1, 1},
  34. /* RXAUI_UNIT_ID */ { 1, 1}
  35. };
  36. #endif
  37. u32 g_dev_id = -1;
  38. u32 mv_board_id_get(void)
  39. {
  40. #if defined(CONFIG_TARGET_DB_88F6820_GP)
  41. return DB_GP_68XX_ID;
  42. #else
  43. /*
  44. * Return 0 here for custom board as this should not be used
  45. * for custom boards.
  46. */
  47. return 0;
  48. #endif
  49. }
  50. u32 mv_board_tclk_get(void)
  51. {
  52. u32 value;
  53. value = (reg_read(DEVICE_SAMPLE_AT_RESET1_REG) >> 15) & 0x1;
  54. switch (value) {
  55. case (0x0):
  56. return 250000000;
  57. case (0x1):
  58. return 200000000;
  59. default:
  60. return 0xffffffff;
  61. }
  62. }
  63. u32 mv_board_id_index_get(u32 board_id)
  64. {
  65. /*
  66. * Marvell Boards use 0x10 as base for Board ID:
  67. * mask MSB to receive index for board ID
  68. */
  69. return board_id & (MARVELL_BOARD_ID_MASK - 1);
  70. }
  71. /*
  72. * sys_env_suspend_wakeup_check
  73. * DESCRIPTION: Reads GPIO input for suspend-wakeup indication.
  74. * INPUT: None.
  75. * OUTPUT:
  76. * RETURNS: u32 indicating suspend wakeup status:
  77. * 0 - Not supported,
  78. * 1 - supported: read magic word detect wakeup,
  79. * 2 - detected wakeup from GPIO.
  80. */
  81. enum suspend_wakeup_status sys_env_suspend_wakeup_check(void)
  82. {
  83. u32 reg, board_id_index, gpio;
  84. struct board_wakeup_gpio board_gpio[] = MV_BOARD_WAKEUP_GPIO_INFO;
  85. board_id_index = mv_board_id_index_get(mv_board_id_get());
  86. if (!(sizeof(board_gpio) / sizeof(struct board_wakeup_gpio) >
  87. board_id_index)) {
  88. printf("\n_failed loading Suspend-Wakeup information (invalid board ID)\n");
  89. return SUSPEND_WAKEUP_DISABLED;
  90. }
  91. /*
  92. * - Detect if Suspend-Wakeup is supported on current board
  93. * - Fetch the GPIO number for wakeup status input indication
  94. */
  95. if (board_gpio[board_id_index].gpio_num == -1) {
  96. /* Suspend to RAM is not supported */
  97. return SUSPEND_WAKEUP_DISABLED;
  98. } else if (board_gpio[board_id_index].gpio_num == -2) {
  99. /*
  100. * Suspend to RAM is supported but GPIO indication is
  101. * not implemented - Skip
  102. */
  103. return SUSPEND_WAKEUP_ENABLED;
  104. } else {
  105. gpio = board_gpio[board_id_index].gpio_num;
  106. }
  107. /* Initialize MPP for GPIO (set MPP = 0x0) */
  108. reg = reg_read(MPP_CONTROL_REG(MPP_REG_NUM(gpio)));
  109. /* reset MPP21 to 0x0, keep rest of MPP settings*/
  110. reg &= ~MPP_MASK(gpio);
  111. reg_write(MPP_CONTROL_REG(MPP_REG_NUM(gpio)), reg);
  112. /* Initialize GPIO as input */
  113. reg = reg_read(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)));
  114. reg |= GPP_MASK(gpio);
  115. reg_write(GPP_DATA_OUT_EN_REG(GPP_REG_NUM(gpio)), reg);
  116. /*
  117. * Check GPP for input status from PIC: 0 - regular init,
  118. * 1 - suspend wakeup
  119. */
  120. reg = reg_read(GPP_DATA_IN_REG(GPP_REG_NUM(gpio)));
  121. /* if GPIO is ON: wakeup from S2RAM indication detected */
  122. return (reg & GPP_MASK(gpio)) ? SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED :
  123. SUSPEND_WAKEUP_DISABLED;
  124. }
  125. /*
  126. * mv_ctrl_dev_id_index_get
  127. *
  128. * DESCRIPTION: return SOC device index
  129. * INPUT: None
  130. * OUTPUT: None
  131. * RETURN:
  132. * return SOC device index
  133. */
  134. u32 sys_env_id_index_get(u32 ctrl_model)
  135. {
  136. switch (ctrl_model) {
  137. case MV_6820_DEV_ID:
  138. return MV_6820_INDEX;
  139. case MV_6810_DEV_ID:
  140. return MV_6810_INDEX;
  141. case MV_6811_DEV_ID:
  142. return MV_6811_INDEX;
  143. case MV_6828_DEV_ID:
  144. return MV_6828_INDEX;
  145. case MV_6920_DEV_ID:
  146. return MV_6920_INDEX;
  147. case MV_6928_DEV_ID:
  148. return MV_6928_INDEX;
  149. default:
  150. return MV_6820_INDEX;
  151. }
  152. }
  153. u32 sys_env_unit_max_num_get(enum unit_id unit)
  154. {
  155. u32 dev_id_index;
  156. if (unit >= MAX_UNITS_ID) {
  157. printf("%s: Error: Wrong unit type (%u)\n", __func__, unit);
  158. return 0;
  159. }
  160. dev_id_index = sys_env_id_index_get(sys_env_model_get());
  161. return sys_env_soc_unit_nums[unit][dev_id_index];
  162. }
  163. /*
  164. * sys_env_model_get
  165. * DESCRIPTION: Returns 16bit describing the device model (ID) as defined
  166. * in Vendor ID configuration register
  167. */
  168. u16 sys_env_model_get(void)
  169. {
  170. u32 default_ctrl_id, ctrl_id = reg_read(DEV_ID_REG);
  171. ctrl_id = (ctrl_id & (DEV_ID_REG_DEVICE_ID_MASK)) >>
  172. DEV_ID_REG_DEVICE_ID_OFFS;
  173. switch (ctrl_id) {
  174. case MV_6820_DEV_ID:
  175. case MV_6810_DEV_ID:
  176. case MV_6811_DEV_ID:
  177. case MV_6828_DEV_ID:
  178. case MV_6920_DEV_ID:
  179. case MV_6928_DEV_ID:
  180. return ctrl_id;
  181. default:
  182. /* Device ID Default for A38x: 6820 , for A39x: 6920 */
  183. #ifdef CONFIG_ARMADA_38X
  184. default_ctrl_id = MV_6820_DEV_ID;
  185. #else
  186. default_ctrl_id = MV_6920_DEV_ID;
  187. #endif
  188. printf("%s: Error retrieving device ID (%x), using default ID = %x\n",
  189. __func__, ctrl_id, default_ctrl_id);
  190. return default_ctrl_id;
  191. }
  192. }
  193. /*
  194. * sys_env_device_id_get
  195. * DESCRIPTION: Returns enum (0..7) index of the device model (ID)
  196. */
  197. u32 sys_env_device_id_get(void)
  198. {
  199. char *device_id_str[7] = {
  200. "6810", "6820", "6811", "6828", "NONE", "6920", "6928"
  201. };
  202. if (g_dev_id != -1)
  203. return g_dev_id;
  204. g_dev_id = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
  205. g_dev_id = g_dev_id >> SAR_DEV_ID_OFFS & SAR_DEV_ID_MASK;
  206. printf("Detected Device ID %s\n", device_id_str[g_dev_id]);
  207. return g_dev_id;
  208. }
  209. /*
  210. * sys_env_device_rev_get - Get Marvell controller device revision number
  211. *
  212. * DESCRIPTION:
  213. * This function returns 8bit describing the device revision as defined
  214. * Revision ID Register.
  215. *
  216. * INPUT:
  217. * None.
  218. *
  219. * OUTPUT:
  220. * None.
  221. *
  222. * RETURN:
  223. * 8bit desscribing Marvell controller revision number
  224. */
  225. u8 sys_env_device_rev_get(void)
  226. {
  227. u32 value;
  228. value = reg_read(DEV_VERSION_ID_REG);
  229. return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
  230. }
  231. void mv_rtc_config(void)
  232. {
  233. u32 i, val;
  234. if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
  235. return;
  236. /* Activate pipe0 for read/write transaction, and set XBAR client number #1 */
  237. val = 0x1 << DFX_PIPE_SELECT_PIPE0_ACTIVE_OFFS |
  238. 0x1 << DFX_PIPE_SELECT_XBAR_CLIENT_SEL_OFFS;
  239. writel(val, MVEBU_DFX_BASE);
  240. /* Set new RTC value for all memory wrappers */
  241. for (i = 0; i < RTC_MEMORY_WRAPPER_COUNT; i++)
  242. reg_write(RTC_MEMORY_WRAPPER_REG(i), RTC_MEMORY_WRAPPER_CTRL_VAL);
  243. }
  244. void mv_avs_init(void)
  245. {
  246. u32 sar_freq;
  247. if (!(IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARMADA_39X)))
  248. return;
  249. reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
  250. reg_write(AVS_DEBUG_CNTR_REG, AVS_DEBUG_CNTR_DEFAULT_VALUE);
  251. sar_freq = reg_read(DEVICE_SAMPLE_AT_RESET1_REG);
  252. sar_freq = sar_freq >> SAR_FREQ_OFFSET & SAR_FREQ_MASK;
  253. /* Set AVS value only for core frequency of 1600MHz or less.
  254. * For higher frequency leave the default value.
  255. */
  256. if (sar_freq <= 0xd) {
  257. u32 avs_reg_data = reg_read(AVS_ENABLED_CONTROL);
  258. avs_reg_data &= ~(AVS_LOW_VDD_LIMIT_MASK
  259. | AVS_HIGH_VDD_LIMIT_MASK);
  260. avs_reg_data |= AVS_LOW_VDD_SLOW_VAL | AVS_HIGH_VDD_SLOW_VAL;
  261. reg_write(AVS_ENABLED_CONTROL, avs_reg_data);
  262. }
  263. }