ctrl_pex.c 9.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <spl.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/cpu.h>
  9. #include <asm/arch/soc.h>
  10. #include <linux/delay.h>
  11. #include "ctrl_pex.h"
  12. #include "sys_env_lib.h"
  13. __weak void board_pex_config(void)
  14. {
  15. /* nothing in this weak default implementation */
  16. }
  17. int hws_pex_config(const struct serdes_map *serdes_map, u8 count)
  18. {
  19. u32 pex_idx, tmp, next_busno, first_busno, temp_pex_reg,
  20. temp_reg, addr, dev_id, ctrl_mode;
  21. enum serdes_type serdes_type;
  22. u32 idx;
  23. DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n");
  24. for (idx = 0; idx < count; idx++) {
  25. serdes_type = serdes_map[idx].serdes_type;
  26. /* configuration for PEX only */
  27. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  28. (serdes_type != PEX2) && (serdes_type != PEX3))
  29. continue;
  30. if ((serdes_type != PEX0) &&
  31. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  32. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  33. /* for PEX by4 - relevant for the first port only */
  34. continue;
  35. }
  36. pex_idx = serdes_type - PEX0;
  37. tmp = reg_read(PEX_CAPABILITIES_REG(pex_idx));
  38. tmp &= ~(0xf << 20);
  39. tmp |= (0x4 << 20);
  40. reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
  41. }
  42. tmp = reg_read(SOC_CTRL_REG);
  43. tmp &= ~0x03;
  44. for (idx = 0; idx < count; idx++) {
  45. serdes_type = serdes_map[idx].serdes_type;
  46. if ((serdes_type != PEX0) &&
  47. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  48. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  49. /* for PEX by4 - relevant for the first port only */
  50. continue;
  51. }
  52. switch (serdes_type) {
  53. case PEX0:
  54. tmp |= 0x1 << PCIE0_ENABLE_OFFS;
  55. break;
  56. case PEX1:
  57. tmp |= 0x1 << PCIE1_ENABLE_OFFS;
  58. break;
  59. case PEX2:
  60. tmp |= 0x1 << PCIE2_ENABLE_OFFS;
  61. break;
  62. case PEX3:
  63. tmp |= 0x1 << PCIE3_ENABLE_OFFS;
  64. break;
  65. default:
  66. break;
  67. }
  68. }
  69. reg_write(SOC_CTRL_REG, tmp);
  70. /* Support gen1/gen2 */
  71. DEBUG_INIT_FULL_S("Support gen1/gen2\n");
  72. board_pex_config();
  73. next_busno = 0;
  74. mdelay(150);
  75. for (idx = 0; idx < count; idx++) {
  76. serdes_type = serdes_map[idx].serdes_type;
  77. DEBUG_INIT_FULL_S(" serdes_type=0x");
  78. DEBUG_INIT_FULL_D(serdes_type, 8);
  79. DEBUG_INIT_FULL_S("\n");
  80. DEBUG_INIT_FULL_S(" idx=0x");
  81. DEBUG_INIT_FULL_D(idx, 8);
  82. DEBUG_INIT_FULL_S("\n");
  83. /* Configuration for PEX only */
  84. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  85. (serdes_type != PEX2) && (serdes_type != PEX3))
  86. continue;
  87. if ((serdes_type != PEX0) &&
  88. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  89. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  90. /* for PEX by4 - relevant for the first port only */
  91. continue;
  92. }
  93. pex_idx = serdes_type - PEX0;
  94. tmp = reg_read(PEX_DBG_STATUS_REG(pex_idx));
  95. first_busno = next_busno;
  96. if ((tmp & 0x7f) != 0x7e) {
  97. DEBUG_INIT_S("PCIe, Idx ");
  98. DEBUG_INIT_D(pex_idx, 1);
  99. DEBUG_INIT_S(": detected no link\n");
  100. continue;
  101. }
  102. next_busno++;
  103. temp_pex_reg = reg_read((PEX_CFG_DIRECT_ACCESS
  104. (pex_idx, PEX_LINK_CAPABILITY_REG)));
  105. temp_pex_reg &= 0xf;
  106. if (temp_pex_reg != 0x2)
  107. continue;
  108. temp_reg = (reg_read(PEX_CFG_DIRECT_ACCESS(
  109. pex_idx,
  110. PEX_LINK_CTRL_STAT_REG)) &
  111. 0xf0000) >> 16;
  112. /* Check if the link established is GEN1 */
  113. DEBUG_INIT_FULL_S
  114. ("Checking if the link established is gen1\n");
  115. if (temp_reg != 0x1)
  116. continue;
  117. pex_local_bus_num_set(pex_idx, first_busno);
  118. pex_local_dev_num_set(pex_idx, 1);
  119. DEBUG_INIT_FULL_S("PCIe, Idx ");
  120. DEBUG_INIT_FULL_D(pex_idx, 1);
  121. DEBUG_INIT_S(":** Link is Gen1, check the EP capability\n");
  122. /* link is Gen1, check the EP capability */
  123. addr = pex_config_read(pex_idx, first_busno, 0, 0, 0x34) & 0xff;
  124. DEBUG_INIT_FULL_C("pex_config_read: return addr=0x%x", addr, 4);
  125. if (addr == 0xff) {
  126. DEBUG_INIT_FULL_C
  127. ("pex_config_read: return 0xff -->PCIe (%d): Detected No Link.",
  128. pex_idx, 1);
  129. continue;
  130. }
  131. while ((pex_config_read(pex_idx, first_busno, 0, 0, addr)
  132. & 0xff) != 0x10) {
  133. addr = (pex_config_read(pex_idx, first_busno, 0,
  134. 0, addr) & 0xff00) >> 8;
  135. }
  136. /* Check for Gen2 and above */
  137. if ((pex_config_read(pex_idx, first_busno, 0, 0,
  138. addr + 0xc) & 0xf) < 0x2) {
  139. DEBUG_INIT_S("PCIe, Idx ");
  140. DEBUG_INIT_D(pex_idx, 1);
  141. DEBUG_INIT_S(": remains Gen1\n");
  142. continue;
  143. }
  144. tmp = reg_read(PEX_LINK_CTRL_STATUS2_REG(pex_idx));
  145. DEBUG_RD_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  146. tmp &= ~(BIT(0) | BIT(1));
  147. tmp |= BIT(1);
  148. tmp |= BIT(6); /* Select Deemphasize (-3.5d_b) */
  149. reg_write(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  150. DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp);
  151. tmp = reg_read(PEX_CTRL_REG(pex_idx));
  152. DEBUG_RD_REG(PEX_CTRL_REG(pex_idx), tmp);
  153. tmp |= BIT(10);
  154. reg_write(PEX_CTRL_REG(pex_idx), tmp);
  155. DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp);
  156. /*
  157. * We need to wait 10ms before reading the PEX_DBG_STATUS_REG
  158. * in order not to read the status of the former state
  159. */
  160. mdelay(10);
  161. DEBUG_INIT_S("PCIe, Idx ");
  162. DEBUG_INIT_D(pex_idx, 1);
  163. DEBUG_INIT_S
  164. (": Link upgraded to Gen2 based on client capabilities\n");
  165. }
  166. /* Update pex DEVICE ID */
  167. ctrl_mode = sys_env_model_get();
  168. for (idx = 0; idx < count; idx++) {
  169. serdes_type = serdes_map[idx].serdes_type;
  170. /* configuration for PEX only */
  171. if ((serdes_type != PEX0) && (serdes_type != PEX1) &&
  172. (serdes_type != PEX2) && (serdes_type != PEX3))
  173. continue;
  174. if ((serdes_type != PEX0) &&
  175. ((serdes_map[idx].serdes_mode == PEX_ROOT_COMPLEX_X4) ||
  176. (serdes_map[idx].serdes_mode == PEX_END_POINT_X4))) {
  177. /* for PEX by4 - relevant for the first port only */
  178. continue;
  179. }
  180. pex_idx = serdes_type - PEX0;
  181. dev_id = reg_read(PEX_CFG_DIRECT_ACCESS
  182. (pex_idx, PEX_DEVICE_AND_VENDOR_ID));
  183. dev_id &= 0xffff;
  184. dev_id |= ((ctrl_mode << 16) & 0xffff0000);
  185. reg_write(PEX_CFG_DIRECT_ACCESS
  186. (pex_idx, PEX_DEVICE_AND_VENDOR_ID), dev_id);
  187. }
  188. DEBUG_INIT_FULL_C("Update PEX Device ID ", ctrl_mode, 4);
  189. return MV_OK;
  190. }
  191. int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
  192. {
  193. u32 pex_status;
  194. DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n");
  195. if (bus_num >= MAX_PEX_BUSSES) {
  196. DEBUG_INIT_C("pex_local_bus_num_set: Illegal bus number %d\n",
  197. bus_num, 4);
  198. return MV_BAD_PARAM;
  199. }
  200. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  201. pex_status &= ~PXSR_PEX_BUS_NUM_MASK;
  202. pex_status |=
  203. (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
  204. reg_write(PEX_STATUS_REG(pex_if), pex_status);
  205. return MV_OK;
  206. }
  207. int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
  208. {
  209. u32 pex_status;
  210. DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n");
  211. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  212. pex_status &= ~PXSR_PEX_DEV_NUM_MASK;
  213. pex_status |=
  214. (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
  215. reg_write(PEX_STATUS_REG(pex_if), pex_status);
  216. return MV_OK;
  217. }
  218. /*
  219. * pex_config_read - Read from configuration space
  220. *
  221. * DESCRIPTION:
  222. * This function performs a 32 bit read from PEX configuration space.
  223. * It supports both type 0 and type 1 of Configuration Transactions
  224. * (local and over bridge). In order to read from local bus segment, use
  225. * bus number retrieved from pex_local_bus_num_get(). Other bus numbers
  226. * will result configuration transaction of type 1 (over bridge).
  227. *
  228. * INPUT:
  229. * pex_if - PEX interface number.
  230. * bus - PEX segment bus number.
  231. * dev - PEX device number.
  232. * func - Function number.
  233. * reg_offs - Register offset.
  234. *
  235. * OUTPUT:
  236. * None.
  237. *
  238. * RETURN:
  239. * 32bit register data, 0xffffffff on error
  240. */
  241. u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off)
  242. {
  243. u32 pex_data = 0;
  244. u32 local_dev, local_bus;
  245. u32 pex_status;
  246. pex_status = reg_read(PEX_STATUS_REG(pex_if));
  247. local_dev =
  248. ((pex_status & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
  249. local_bus =
  250. ((pex_status & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
  251. /*
  252. * In PCI Express we have only one device number
  253. * and this number is the first number we encounter
  254. * else that the local_dev
  255. * spec pex define return on config read/write on any device
  256. */
  257. if (bus == local_bus) {
  258. if (local_dev == 0) {
  259. /*
  260. * if local dev is 0 then the first number we encounter
  261. * after 0 is 1
  262. */
  263. if ((dev != 1) && (dev != local_dev))
  264. return MV_ERROR;
  265. } else {
  266. /*
  267. * if local dev is not 0 then the first number we
  268. * encounter is 0
  269. */
  270. if ((dev != 0) && (dev != local_dev))
  271. return MV_ERROR;
  272. }
  273. }
  274. /* Creating PEX address to be passed */
  275. pex_data = (bus << PXCAR_BUS_NUM_OFFS);
  276. pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
  277. pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
  278. /* Legacy register space */
  279. pex_data |= (reg_off & PXCAR_REG_NUM_MASK);
  280. /* Extended register space */
  281. pex_data |= (((reg_off & PXCAR_REAL_EXT_REG_NUM_MASK) >>
  282. PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
  283. pex_data |= PXCAR_CONFIG_EN;
  284. /* Write the address to the PEX configuration address register */
  285. reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
  286. /*
  287. * In order to let the PEX controller absorbed the address
  288. * of the read transaction we perform a validity check that
  289. * the address was written
  290. */
  291. if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
  292. return MV_ERROR;
  293. /* Cleaning Master Abort */
  294. reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
  295. PXSAC_MABORT);
  296. /* Read the Data returned in the PEX Data register */
  297. pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
  298. DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
  299. return pex_data;
  300. }