cpu.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <ahci.h>
  7. #include <cpu_func.h>
  8. #include <init.h>
  9. #include <linux/delay.h>
  10. #include <linux/mbus.h>
  11. #include <asm/io.h>
  12. #include <asm/pl310.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #include <sdhci.h>
  16. #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
  17. #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
  18. static struct mbus_win windows[] = {
  19. /* SPI */
  20. { MBUS_SPI_BASE, MBUS_SPI_SIZE,
  21. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
  22. /* NOR */
  23. { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
  24. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
  25. #ifdef CONFIG_ARMADA_MSYS
  26. /* DFX */
  27. { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
  28. #endif
  29. };
  30. void lowlevel_init(void)
  31. {
  32. /*
  33. * Dummy implementation, we only need LOWLEVEL_INIT
  34. * on Armada to configure CP15 in start.S / cpu_init_cp15()
  35. */
  36. }
  37. void reset_cpu(unsigned long ignored)
  38. {
  39. struct mvebu_system_registers *reg =
  40. (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
  41. writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask);
  42. writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst);
  43. while (1)
  44. ;
  45. }
  46. int mvebu_soc_family(void)
  47. {
  48. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  49. switch (devid) {
  50. case SOC_MV78230_ID:
  51. case SOC_MV78260_ID:
  52. case SOC_MV78460_ID:
  53. return MVEBU_SOC_AXP;
  54. case SOC_88F6720_ID:
  55. return MVEBU_SOC_A375;
  56. case SOC_88F6810_ID:
  57. case SOC_88F6820_ID:
  58. case SOC_88F6828_ID:
  59. return MVEBU_SOC_A38X;
  60. case SOC_98DX3236_ID:
  61. case SOC_98DX3336_ID:
  62. case SOC_98DX4251_ID:
  63. return MVEBU_SOC_MSYS;
  64. }
  65. return MVEBU_SOC_UNKNOWN;
  66. }
  67. #if defined(CONFIG_DISPLAY_CPUINFO)
  68. #if defined(CONFIG_ARMADA_375)
  69. /* SAR frequency values for Armada 375 */
  70. static const struct sar_freq_modes sar_freq_tab[] = {
  71. { 0, 0x0, 266, 133, 266 },
  72. { 1, 0x0, 333, 167, 167 },
  73. { 2, 0x0, 333, 167, 222 },
  74. { 3, 0x0, 333, 167, 333 },
  75. { 4, 0x0, 400, 200, 200 },
  76. { 5, 0x0, 400, 200, 267 },
  77. { 6, 0x0, 400, 200, 400 },
  78. { 7, 0x0, 500, 250, 250 },
  79. { 8, 0x0, 500, 250, 334 },
  80. { 9, 0x0, 500, 250, 500 },
  81. { 10, 0x0, 533, 267, 267 },
  82. { 11, 0x0, 533, 267, 356 },
  83. { 12, 0x0, 533, 267, 533 },
  84. { 13, 0x0, 600, 300, 300 },
  85. { 14, 0x0, 600, 300, 400 },
  86. { 15, 0x0, 600, 300, 600 },
  87. { 16, 0x0, 666, 333, 333 },
  88. { 17, 0x0, 666, 333, 444 },
  89. { 18, 0x0, 666, 333, 666 },
  90. { 19, 0x0, 800, 400, 267 },
  91. { 20, 0x0, 800, 400, 400 },
  92. { 21, 0x0, 800, 400, 534 },
  93. { 22, 0x0, 900, 450, 300 },
  94. { 23, 0x0, 900, 450, 450 },
  95. { 24, 0x0, 900, 450, 600 },
  96. { 25, 0x0, 1000, 500, 500 },
  97. { 26, 0x0, 1000, 500, 667 },
  98. { 27, 0x0, 1000, 333, 500 },
  99. { 28, 0x0, 400, 400, 400 },
  100. { 29, 0x0, 1100, 550, 550 },
  101. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  102. };
  103. #elif defined(CONFIG_ARMADA_38X)
  104. /* SAR frequency values for Armada 38x */
  105. static const struct sar_freq_modes sar_freq_tab[] = {
  106. { 0x0, 0x0, 666, 333, 333 },
  107. { 0x2, 0x0, 800, 400, 400 },
  108. { 0x4, 0x0, 1066, 533, 533 },
  109. { 0x6, 0x0, 1200, 600, 600 },
  110. { 0x8, 0x0, 1332, 666, 666 },
  111. { 0xc, 0x0, 1600, 800, 800 },
  112. { 0x10, 0x0, 1866, 933, 933 },
  113. { 0x13, 0x0, 2000, 1000, 933 },
  114. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  115. };
  116. #elif defined(CONFIG_ARMADA_MSYS)
  117. static const struct sar_freq_modes sar_freq_tab[] = {
  118. { 0x0, 0x0, 400, 400, 400 },
  119. { 0x2, 0x0, 667, 333, 667 },
  120. { 0x3, 0x0, 800, 400, 800 },
  121. { 0x5, 0x0, 800, 400, 800 },
  122. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  123. };
  124. #else
  125. /* SAR frequency values for Armada XP */
  126. static const struct sar_freq_modes sar_freq_tab[] = {
  127. { 0xa, 0x5, 800, 400, 400 },
  128. { 0x1, 0x5, 1066, 533, 533 },
  129. { 0x2, 0x5, 1200, 600, 600 },
  130. { 0x2, 0x9, 1200, 600, 400 },
  131. { 0x3, 0x5, 1333, 667, 667 },
  132. { 0x4, 0x5, 1500, 750, 750 },
  133. { 0x4, 0x9, 1500, 750, 500 },
  134. { 0xb, 0x9, 1600, 800, 533 },
  135. { 0xb, 0xa, 1600, 800, 640 },
  136. { 0xb, 0x5, 1600, 800, 800 },
  137. { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
  138. };
  139. #endif
  140. void get_sar_freq(struct sar_freq_modes *sar_freq)
  141. {
  142. u32 val;
  143. u32 freq;
  144. int i;
  145. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
  146. val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
  147. #else
  148. val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
  149. #endif
  150. freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS;
  151. #if defined(SAR2_CPU_FREQ_MASK)
  152. /*
  153. * Shift CPU0 clock frequency select bit from SAR2 register
  154. * into correct position
  155. */
  156. freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK)
  157. >> SAR2_CPU_FREQ_OFFS) << 3;
  158. #endif
  159. for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
  160. if (sar_freq_tab[i].val == freq) {
  161. #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
  162. *sar_freq = sar_freq_tab[i];
  163. return;
  164. #else
  165. int k;
  166. u8 ffc;
  167. ffc = (val & SAR_FFC_FREQ_MASK) >>
  168. SAR_FFC_FREQ_OFFS;
  169. for (k = i; sar_freq_tab[k].ffc != 0xff; k++) {
  170. if (sar_freq_tab[k].ffc == ffc) {
  171. *sar_freq = sar_freq_tab[k];
  172. return;
  173. }
  174. }
  175. i = k;
  176. #endif
  177. }
  178. }
  179. /* SAR value not found, return 0 for frequencies */
  180. *sar_freq = sar_freq_tab[i - 1];
  181. }
  182. int print_cpuinfo(void)
  183. {
  184. u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
  185. u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
  186. struct sar_freq_modes sar_freq;
  187. puts("SoC: ");
  188. switch (devid) {
  189. case SOC_MV78230_ID:
  190. puts("MV78230-");
  191. break;
  192. case SOC_MV78260_ID:
  193. puts("MV78260-");
  194. break;
  195. case SOC_MV78460_ID:
  196. puts("MV78460-");
  197. break;
  198. case SOC_88F6720_ID:
  199. puts("MV88F6720-");
  200. break;
  201. case SOC_88F6810_ID:
  202. puts("MV88F6810-");
  203. break;
  204. case SOC_88F6820_ID:
  205. puts("MV88F6820-");
  206. break;
  207. case SOC_88F6828_ID:
  208. puts("MV88F6828-");
  209. break;
  210. case SOC_98DX3236_ID:
  211. puts("98DX3236-");
  212. break;
  213. case SOC_98DX3336_ID:
  214. puts("98DX3336-");
  215. break;
  216. case SOC_98DX4251_ID:
  217. puts("98DX4251-");
  218. break;
  219. default:
  220. puts("Unknown-");
  221. break;
  222. }
  223. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  224. switch (revid) {
  225. case 1:
  226. puts("A0");
  227. break;
  228. case 2:
  229. puts("B0");
  230. break;
  231. default:
  232. printf("?? (%x)", revid);
  233. break;
  234. }
  235. }
  236. if (mvebu_soc_family() == MVEBU_SOC_A375) {
  237. switch (revid) {
  238. case MV_88F67XX_A0_ID:
  239. puts("A0");
  240. break;
  241. default:
  242. printf("?? (%x)", revid);
  243. break;
  244. }
  245. }
  246. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  247. switch (revid) {
  248. case MV_88F68XX_Z1_ID:
  249. puts("Z1");
  250. break;
  251. case MV_88F68XX_A0_ID:
  252. puts("A0");
  253. break;
  254. case MV_88F68XX_B0_ID:
  255. puts("B0");
  256. break;
  257. default:
  258. printf("?? (%x)", revid);
  259. break;
  260. }
  261. }
  262. if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
  263. switch (revid) {
  264. case 3:
  265. puts("A0");
  266. break;
  267. case 4:
  268. puts("A1");
  269. break;
  270. default:
  271. printf("?? (%x)", revid);
  272. break;
  273. }
  274. }
  275. get_sar_freq(&sar_freq);
  276. printf(" at %d MHz\n", sar_freq.p_clk);
  277. return 0;
  278. }
  279. #endif /* CONFIG_DISPLAY_CPUINFO */
  280. /*
  281. * This function initialize Controller DRAM Fastpath windows.
  282. * It takes the CS size information from the 0x1500 scratch registers
  283. * and sets the correct windows sizes and base addresses accordingly.
  284. *
  285. * These values are set in the scratch registers by the Marvell
  286. * DDR3 training code, which is executed by the SPL before the
  287. * main payload (U-Boot) is executed.
  288. */
  289. static void update_sdram_window_sizes(void)
  290. {
  291. u64 base = 0;
  292. u32 size, temp;
  293. int i;
  294. for (i = 0; i < SDRAM_MAX_CS; i++) {
  295. size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
  296. if (size != 0) {
  297. size |= ~(SDRAM_ADDR_MASK);
  298. /* Set Base Address */
  299. temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
  300. writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
  301. /*
  302. * Check if out of max window size and resize
  303. * the window
  304. */
  305. temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
  306. ~(SDRAM_ADDR_MASK)) | 1;
  307. temp |= (size & SDRAM_ADDR_MASK);
  308. writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
  309. base += ((u64)size + 1);
  310. } else {
  311. /*
  312. * Disable window if not used, otherwise this
  313. * leads to overlapping enabled windows with
  314. * pretty strange results
  315. */
  316. clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
  317. }
  318. }
  319. }
  320. void mmu_disable(void)
  321. {
  322. asm volatile(
  323. "mrc p15, 0, r0, c1, c0, 0\n"
  324. "bic r0, #1\n"
  325. "mcr p15, 0, r0, c1, c0, 0\n");
  326. }
  327. #ifdef CONFIG_ARCH_CPU_INIT
  328. static void set_cbar(u32 addr)
  329. {
  330. asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
  331. }
  332. #define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
  333. #define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
  334. #define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
  335. (((addr) & 0xF) << 6))
  336. #define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
  337. (((reg) & 0xF) << 2))
  338. static void setup_usb_phys(void)
  339. {
  340. int dev;
  341. /*
  342. * USB PLL init
  343. */
  344. /* Setup PLL frequency */
  345. /* USB REF frequency = 25 MHz */
  346. clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
  347. /* Power up PLL and PHY channel */
  348. setbits_le32(MV_USB_PHY_PLL_REG(2), BIT(9));
  349. /* Assert VCOCAL_START */
  350. setbits_le32(MV_USB_PHY_PLL_REG(1), BIT(21));
  351. mdelay(1);
  352. /*
  353. * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
  354. */
  355. for (dev = 0; dev < 3; dev++) {
  356. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), BIT(15));
  357. /* Assert REG_RCAL_START in channel REG 1 */
  358. setbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  359. udelay(40);
  360. clrbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12));
  361. }
  362. }
  363. /*
  364. * This function is not called from the SPL U-Boot version
  365. */
  366. int arch_cpu_init(void)
  367. {
  368. struct pl310_regs *const pl310 =
  369. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  370. /*
  371. * Only with disabled MMU its possible to switch the base
  372. * register address on Armada 38x. Without this the SDRAM
  373. * located at >= 0x4000.0000 is also not accessible, as its
  374. * still locked to cache.
  375. */
  376. mmu_disable();
  377. /* Linux expects the internal registers to be at 0xf1000000 */
  378. writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
  379. set_cbar(SOC_REGS_PHY_BASE + 0xC000);
  380. /*
  381. * From this stage on, the SoC detection is working. As we have
  382. * configured the internal register base to the value used
  383. * in the macros / defines in the U-Boot header (soc.h).
  384. */
  385. if (mvebu_soc_family() == MVEBU_SOC_A38X) {
  386. /*
  387. * To fully release / unlock this area from cache, we need
  388. * to flush all caches and disable the L2 cache.
  389. */
  390. icache_disable();
  391. dcache_disable();
  392. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  393. }
  394. /*
  395. * We need to call mvebu_mbus_probe() before calling
  396. * update_sdram_window_sizes() as it disables all previously
  397. * configured mbus windows and then configures them as
  398. * required for U-Boot. Calling update_sdram_window_sizes()
  399. * without this configuration will not work, as the internal
  400. * registers can't be accessed reliably because of potenial
  401. * double mapping.
  402. * After updating the SDRAM access windows we need to call
  403. * mvebu_mbus_probe() again, as this now correctly configures
  404. * the SDRAM areas that are later used by the MVEBU drivers
  405. * (e.g. USB, NETA).
  406. */
  407. /*
  408. * First disable all windows
  409. */
  410. mvebu_mbus_probe(NULL, 0);
  411. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  412. /*
  413. * Now the SDRAM access windows can be reconfigured using
  414. * the information in the SDRAM scratch pad registers
  415. */
  416. update_sdram_window_sizes();
  417. }
  418. /*
  419. * Finally the mbus windows can be configured with the
  420. * updated SDRAM sizes
  421. */
  422. mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
  423. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  424. /* Enable GBE0, GBE1, LCD and NFC PUP */
  425. clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
  426. GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
  427. NAND_PUP_EN | SPI_PUP_EN);
  428. /* Configure USB PLL and PHYs on AXP */
  429. setup_usb_phys();
  430. }
  431. /* Enable NAND and NAND arbiter */
  432. clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
  433. /* Disable MBUS error propagation */
  434. clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
  435. return 0;
  436. }
  437. #endif /* CONFIG_ARCH_CPU_INIT */
  438. u32 mvebu_get_nand_clock(void)
  439. {
  440. u32 reg;
  441. if (mvebu_soc_family() == MVEBU_SOC_A38X)
  442. reg = MVEBU_DFX_DIV_CLK_CTRL(1);
  443. else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
  444. reg = MVEBU_DFX_DIV_CLK_CTRL(8);
  445. else
  446. reg = MVEBU_CORE_DIV_CLK_CTRL(1);
  447. return CONFIG_SYS_MVEBU_PLL_CLOCK /
  448. ((readl(reg) &
  449. NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
  450. }
  451. /*
  452. * SOC specific misc init
  453. */
  454. #if defined(CONFIG_ARCH_MISC_INIT)
  455. int arch_misc_init(void)
  456. {
  457. /* Nothing yet, perhaps we need something here later */
  458. return 0;
  459. }
  460. #endif /* CONFIG_ARCH_MISC_INIT */
  461. #if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC)
  462. int board_mmc_init(bd_t *bis)
  463. {
  464. mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
  465. SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
  466. return 0;
  467. }
  468. #endif
  469. #define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
  470. #define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
  471. #define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
  472. #define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
  473. #define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
  474. static void ahci_mvebu_mbus_config(void __iomem *base)
  475. {
  476. const struct mbus_dram_target_info *dram;
  477. int i;
  478. /* mbus is not initialized in SPL; keep the ROM settings */
  479. if (IS_ENABLED(CONFIG_SPL_BUILD))
  480. return;
  481. dram = mvebu_mbus_dram_info();
  482. for (i = 0; i < 4; i++) {
  483. writel(0, base + AHCI_WINDOW_CTRL(i));
  484. writel(0, base + AHCI_WINDOW_BASE(i));
  485. writel(0, base + AHCI_WINDOW_SIZE(i));
  486. }
  487. for (i = 0; i < dram->num_cs; i++) {
  488. const struct mbus_dram_window *cs = dram->cs + i;
  489. writel((cs->mbus_attr << 8) |
  490. (dram->mbus_dram_target_id << 4) | 1,
  491. base + AHCI_WINDOW_CTRL(i));
  492. writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
  493. writel(((cs->size - 1) & 0xffff0000),
  494. base + AHCI_WINDOW_SIZE(i));
  495. }
  496. }
  497. static void ahci_mvebu_regret_option(void __iomem *base)
  498. {
  499. /*
  500. * Enable the regret bit to allow the SATA unit to regret a
  501. * request that didn't receive an acknowlegde and avoid a
  502. * deadlock
  503. */
  504. writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
  505. writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
  506. }
  507. int board_ahci_enable(void)
  508. {
  509. ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
  510. ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
  511. return 0;
  512. }
  513. #ifdef CONFIG_SCSI_AHCI_PLAT
  514. void scsi_init(void)
  515. {
  516. printf("MVEBU SATA INIT\n");
  517. board_ahci_enable();
  518. ahci_init((void __iomem *)MVEBU_SATA0_BASE);
  519. }
  520. #endif
  521. #ifdef CONFIG_USB_XHCI_MVEBU
  522. #define USB3_MAX_WINDOWS 4
  523. #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8))
  524. #define USB3_WIN_BASE(w) (0x4 + ((w) * 8))
  525. static void xhci_mvebu_mbus_config(void __iomem *base,
  526. const struct mbus_dram_target_info *dram)
  527. {
  528. int i;
  529. for (i = 0; i < USB3_MAX_WINDOWS; i++) {
  530. writel(0, base + USB3_WIN_CTRL(i));
  531. writel(0, base + USB3_WIN_BASE(i));
  532. }
  533. for (i = 0; i < dram->num_cs; i++) {
  534. const struct mbus_dram_window *cs = dram->cs + i;
  535. /* Write size, attributes and target id to control register */
  536. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  537. (dram->mbus_dram_target_id << 4) | 1,
  538. base + USB3_WIN_CTRL(i));
  539. /* Write base address to base register */
  540. writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(i));
  541. }
  542. }
  543. int board_xhci_enable(fdt_addr_t base)
  544. {
  545. const struct mbus_dram_target_info *dram;
  546. printf("MVEBU XHCI INIT controller @ 0x%lx\n", base);
  547. dram = mvebu_mbus_dram_info();
  548. xhci_mvebu_mbus_config((void __iomem *)base, dram);
  549. return 0;
  550. }
  551. #endif
  552. void enable_caches(void)
  553. {
  554. /* Avoid problem with e.g. neta ethernet driver */
  555. invalidate_dcache_all();
  556. /*
  557. * Armada 375 still has some problems with d-cache enabled in the
  558. * ethernet driver (mvpp2). So lets keep the d-cache disabled
  559. * until this is solved.
  560. */
  561. if (mvebu_soc_family() != MVEBU_SOC_A375) {
  562. /* Enable D-cache. I-cache is already enabled in start.S */
  563. dcache_enable();
  564. }
  565. }
  566. void v7_outer_cache_enable(void)
  567. {
  568. if (mvebu_soc_family() == MVEBU_SOC_AXP) {
  569. struct pl310_regs *const pl310 =
  570. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  571. u32 u;
  572. /* The L2 cache is already disabled at this point */
  573. /*
  574. * For Aurora cache in no outer mode, enable via the CP15
  575. * coprocessor broadcasting of cache commands to L2.
  576. */
  577. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  578. u |= BIT(8); /* Set the FW bit */
  579. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  580. isb();
  581. /* Enable the L2 cache */
  582. setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  583. }
  584. }
  585. void v7_outer_cache_disable(void)
  586. {
  587. struct pl310_regs *const pl310 =
  588. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  589. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  590. }