dram.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx dram init
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
  7. *
  8. * This is called by SPL to gain access to the SDR DRAM.
  9. *
  10. * This code runs from SRAM.
  11. */
  12. #include <common.h>
  13. #include <netdev.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/clk.h>
  16. #include <asm/arch/wdt.h>
  17. #include <asm/arch/emc.h>
  18. #include <asm/io.h>
  19. #include <linux/delay.h>
  20. static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
  21. static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
  22. void ddr_init(struct emc_dram_settings *dram)
  23. {
  24. uint32_t ck;
  25. /* Enable EMC interface and choose little endian mode */
  26. writel(1, &emc->ctrl);
  27. writel(0, &emc->config);
  28. /* Select maximum EMC Dynamic Memory Refresh Time */
  29. writel(0x7FF, &emc->refresh);
  30. /* Determine CLK */
  31. ck = get_sdram_clk_rate();
  32. /* Configure SDRAM */
  33. writel(dram->cmddelay, &clk->sdramclk_ctrl);
  34. writel(dram->config0, &emc->config0);
  35. writel(dram->rascas0, &emc->rascas0);
  36. writel(dram->rdconfig, &emc->read_config);
  37. /* Set timings */
  38. writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
  39. writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
  40. writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
  41. writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
  42. writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
  43. writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
  44. writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
  45. writel(dram->trrd, &emc->t_rrd);
  46. writel(dram->tmrd, &emc->t_mrd);
  47. writel(dram->tcdlr, &emc->t_cdlr);
  48. /* Dynamic refresh */
  49. writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
  50. udelay(10);
  51. /* Force all clocks, enable inverted ck, issue NOP command */
  52. writel(0x00000193, &emc->control);
  53. udelay(100);
  54. /* Keep all clocks enabled, issue a PRECHARGE ALL command */
  55. writel(0x00000113, &emc->control);
  56. /* Fast dynamic refresh for at least a few SDRAM ck cycles */
  57. writel((((128) >> 4) & 0x7FF), &emc->refresh);
  58. udelay(10);
  59. /* set correct dynamic refresh timing */
  60. writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
  61. udelay(10);
  62. /* set normal mode to CAS=3 */
  63. writel(0x00000093, &emc->control);
  64. readl(EMC_DYCS0_BASE | dram->mode);
  65. /* set extended mode to all zeroes */
  66. writel(0x00000093, &emc->control);
  67. readl(EMC_DYCS0_BASE | dram->emode);
  68. /* stop forcing clocks, keep inverted clock, issue normal mode */
  69. writel(0x00000010, &emc->control);
  70. }