ddr3.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Keystone2: DDR3 initialization
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <cpu_func.h>
  9. #include <env.h>
  10. #include <asm/io.h>
  11. #include <common.h>
  12. #include <asm/arch/msmc.h>
  13. #include <asm/arch/ddr3.h>
  14. #include <asm/arch/psc_defs.h>
  15. #include <linux/delay.h>
  16. #include <asm/ti-common/ti-edma3.h>
  17. #define DDR3_EDMA_BLK_SIZE_SHIFT 10
  18. #define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
  19. #define DDR3_EDMA_BCNT 0x8000
  20. #define DDR3_EDMA_CCNT 1
  21. #define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
  22. #define DDR3_EDMA_SLOT_NUM 1
  23. void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
  24. {
  25. unsigned int tmp;
  26. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
  27. & 0x00000001) != 0x00000001)
  28. ;
  29. __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
  30. tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
  31. tmp &= ~(phy_cfg->pgcr1_mask);
  32. tmp |= phy_cfg->pgcr1_val;
  33. __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
  34. __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
  35. __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
  36. __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
  37. __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
  38. tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
  39. tmp &= ~(phy_cfg->dcr_mask);
  40. tmp |= phy_cfg->dcr_val;
  41. __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
  42. __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
  43. __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
  44. __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
  45. __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
  46. __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
  47. __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
  48. __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
  49. __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
  50. __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
  51. __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
  52. __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
  53. __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
  54. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  55. ;
  56. if (cpu_is_k2g()) {
  57. clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
  58. phy_cfg->datx8_2_mask,
  59. phy_cfg->datx8_2_val);
  60. clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
  61. phy_cfg->datx8_3_mask,
  62. phy_cfg->datx8_3_val);
  63. clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
  64. phy_cfg->datx8_4_mask,
  65. phy_cfg->datx8_4_val);
  66. clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
  67. phy_cfg->datx8_5_mask,
  68. phy_cfg->datx8_5_val);
  69. clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
  70. phy_cfg->datx8_6_mask,
  71. phy_cfg->datx8_6_val);
  72. clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
  73. phy_cfg->datx8_7_mask,
  74. phy_cfg->datx8_7_val);
  75. clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
  76. phy_cfg->datx8_8_mask,
  77. phy_cfg->datx8_8_val);
  78. }
  79. __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
  80. while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
  81. ;
  82. }
  83. void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
  84. {
  85. __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
  86. __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
  87. __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
  88. __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
  89. __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
  90. __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
  91. __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
  92. }
  93. int ddr3_ecc_support_rmw(u32 base)
  94. {
  95. u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
  96. /* Check the DDR3 controller ID reg if the controllers
  97. supports ECC RMW or not */
  98. if (value == 0x40461C02)
  99. return 1;
  100. return 0;
  101. }
  102. static void ddr3_ecc_config(u32 base, u32 value)
  103. {
  104. u32 data;
  105. __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
  106. udelay(100000); /* delay required to synchronize across clock domains */
  107. if (value & KS2_DDR3_ECC_EN) {
  108. /* Clear the 1-bit error count */
  109. data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  110. __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  111. /* enable the ECC interrupt */
  112. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  113. KS2_DDR3_WR_ECC_ERR_SYS,
  114. base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
  115. /* Clear the ECC error interrupt status */
  116. __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
  117. KS2_DDR3_WR_ECC_ERR_SYS,
  118. base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  119. }
  120. }
  121. static void ddr3_reset_data(u32 base, u32 ddr3_size)
  122. {
  123. u32 mpax[2];
  124. u32 seg_num;
  125. u32 seg, blks, dst, edma_blks;
  126. struct edma3_slot_config slot;
  127. struct edma3_channel_config edma_channel;
  128. u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
  129. /* Setup an edma to copy the 1k block to the entire DDR */
  130. puts("\nClear entire DDR3 memory to enable ECC\n");
  131. /* save the SES MPAX regs */
  132. if (cpu_is_k2g())
  133. msmc_get_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  134. else
  135. msmc_get_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  136. /* setup edma slot 1 configuration */
  137. slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
  138. EDMA3_SLOPT_COMP_CODE(0) |
  139. EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
  140. slot.bcnt = DDR3_EDMA_BCNT;
  141. slot.acnt = DDR3_EDMA_BLK_SIZE;
  142. slot.ccnt = DDR3_EDMA_CCNT;
  143. slot.src_bidx = 0;
  144. slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
  145. slot.src_cidx = 0;
  146. slot.dst_cidx = 0;
  147. slot.link = EDMA3_PARSET_NULL_LINK;
  148. slot.bcntrld = 0;
  149. edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
  150. /* configure quik edma channel */
  151. edma_channel.slot = DDR3_EDMA_SLOT_NUM;
  152. edma_channel.chnum = 0;
  153. edma_channel.complete_code = 0;
  154. /* event trigger after dst update */
  155. edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
  156. qedma3_start(KS2_EDMA0_BASE, &edma_channel);
  157. /* DDR3 size in segments (4KB seg size) */
  158. seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
  159. for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
  160. /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
  161. access slave interface so that edma driver can access */
  162. if (cpu_is_k2g()) {
  163. msmc_map_ses_segment(K2G_MSMC_SEGMENT_ARM, 0,
  164. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  165. KS2_MSMC_DST_SEG_BASE + seg,
  166. MPAX_SEG_2G);
  167. } else {
  168. msmc_map_ses_segment(K2HKLE_MSMC_SEGMENT_ARM, 0,
  169. base >> KS2_MSMC_SEG_SIZE_SHIFT,
  170. KS2_MSMC_DST_SEG_BASE + seg,
  171. MPAX_SEG_2G);
  172. }
  173. if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
  174. edma_blks = KS2_MSMC_MAP_SEG_NUM <<
  175. (KS2_MSMC_SEG_SIZE_SHIFT
  176. - DDR3_EDMA_BLK_SIZE_SHIFT);
  177. else
  178. edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
  179. - DDR3_EDMA_BLK_SIZE_SHIFT);
  180. /* Use edma driver to scrub 2GB DDR memory */
  181. for (dst = base, blks = 0; blks < edma_blks;
  182. blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
  183. edma3_set_src_addr(KS2_EDMA0_BASE,
  184. edma_channel.slot, (u32)edma_src);
  185. edma3_set_dest_addr(KS2_EDMA0_BASE,
  186. edma_channel.slot, (u32)dst);
  187. while (edma3_check_for_transfer(KS2_EDMA0_BASE,
  188. &edma_channel))
  189. udelay(10);
  190. }
  191. }
  192. qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
  193. /* restore the SES MPAX regs */
  194. if (cpu_is_k2g())
  195. msmc_set_ses_mpax(K2G_MSMC_SEGMENT_ARM, 0, mpax);
  196. else
  197. msmc_set_ses_mpax(K2HKLE_MSMC_SEGMENT_ARM, 0, mpax);
  198. }
  199. static void ddr3_ecc_init_range(u32 base)
  200. {
  201. u32 ecc_val = KS2_DDR3_ECC_EN;
  202. u32 rmw = ddr3_ecc_support_rmw(base);
  203. if (rmw)
  204. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  205. __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
  206. ddr3_ecc_config(base, ecc_val);
  207. }
  208. void ddr3_enable_ecc(u32 base, int test)
  209. {
  210. u32 ecc_val = KS2_DDR3_ECC_ENABLE;
  211. u32 rmw = ddr3_ecc_support_rmw(base);
  212. if (test)
  213. ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
  214. if (!rmw) {
  215. if (!test)
  216. /* by default, disable ecc when rmw = 0 and no
  217. ecc test */
  218. ecc_val = 0;
  219. } else {
  220. ecc_val |= KS2_DDR3_ECC_RMW_EN;
  221. }
  222. ddr3_ecc_config(base, ecc_val);
  223. }
  224. void ddr3_disable_ecc(u32 base)
  225. {
  226. ddr3_ecc_config(base, 0);
  227. }
  228. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  229. static void cic_init(u32 base)
  230. {
  231. /* Disable CIC global interrupts */
  232. __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
  233. /* Set to normal mode, no nesting, no priority hold */
  234. __raw_writel(0, base + KS2_CIC_CTRL);
  235. __raw_writel(0, base + KS2_CIC_HOST_CTRL);
  236. /* Enable CIC global interrupts */
  237. __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
  238. }
  239. static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
  240. {
  241. /* Map the system interrupt to a CIC channel */
  242. __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
  243. /* Enable CIC system interrupt */
  244. __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
  245. /* Enable CIC Host interrupt */
  246. __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
  247. }
  248. static void ddr3_map_ecc_cic2_irq(u32 base)
  249. {
  250. cic_init(base);
  251. cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
  252. KS2_CIC2_DDR3_ECC_IRQ_NUM);
  253. }
  254. #endif
  255. void ddr3_init_ecc(u32 base, u32 ddr3_size)
  256. {
  257. if (!ddr3_ecc_support_rmw(base)) {
  258. ddr3_disable_ecc(base);
  259. return;
  260. }
  261. ddr3_ecc_init_range(base);
  262. ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
  263. /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
  264. #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
  265. ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
  266. #endif
  267. ddr3_enable_ecc(base, 0);
  268. }
  269. void ddr3_check_ecc_int(u32 base)
  270. {
  271. char *env;
  272. int ecc_test = 0;
  273. u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
  274. env = env_get("ecc_test");
  275. if (env)
  276. ecc_test = simple_strtol(env, NULL, 0);
  277. if (value & KS2_DDR3_WR_ECC_ERR_SYS)
  278. puts("DDR3 ECC write error interrupted\n");
  279. if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
  280. puts("DDR3 ECC 2-bit error interrupted\n");
  281. if (!ecc_test) {
  282. puts("Reseting the device ...\n");
  283. reset_cpu(0);
  284. }
  285. }
  286. value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
  287. if (value) {
  288. printf("1-bit ECC err count: 0x%x\n", value);
  289. value = __raw_readl(base +
  290. KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
  291. printf("1-bit ECC err address log: 0x%x\n", value);
  292. }
  293. }
  294. void ddr3_reset_ddrphy(void)
  295. {
  296. u32 tmp;
  297. /* Assert DDR3A PHY reset */
  298. tmp = readl(KS2_DDR3APLLCTL1);
  299. tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
  300. writel(tmp, KS2_DDR3APLLCTL1);
  301. /* wait 10us to catch the reset */
  302. udelay(10);
  303. /* Release DDR3A PHY reset */
  304. tmp = readl(KS2_DDR3APLLCTL1);
  305. tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
  306. __raw_writel(tmp, KS2_DDR3APLLCTL1);
  307. }
  308. #ifdef CONFIG_SOC_K2HK
  309. /**
  310. * ddr3_reset_workaround - reset workaround in case if leveling error
  311. * detected for PG 1.0 and 1.1 k2hk SoCs
  312. */
  313. void ddr3_err_reset_workaround(void)
  314. {
  315. unsigned int tmp;
  316. unsigned int tmp_a;
  317. unsigned int tmp_b;
  318. /*
  319. * Check for PGSR0 error bits of DDR3 PHY.
  320. * Check for WLERR, QSGERR, WLAERR,
  321. * RDERR, WDERR, REERR, WEERR error to see if they are set or not
  322. */
  323. tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  324. tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
  325. if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
  326. printf("DDR Leveling Error Detected!\n");
  327. printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
  328. printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
  329. /*
  330. * Write Keys to KICK registers to enable writes to registers
  331. * in boot config space
  332. */
  333. __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
  334. __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
  335. /*
  336. * Move DDR3A Module out of reset isolation by setting
  337. * MDCTL23[12] = 0
  338. */
  339. tmp_a = __raw_readl(KS2_PSC_BASE +
  340. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  341. tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
  342. __raw_writel(tmp_a, KS2_PSC_BASE +
  343. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
  344. /*
  345. * Move DDR3B Module out of reset isolation by setting
  346. * MDCTL24[12] = 0
  347. */
  348. tmp_b = __raw_readl(KS2_PSC_BASE +
  349. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  350. tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
  351. __raw_writel(tmp_b, KS2_PSC_BASE +
  352. PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
  353. /*
  354. * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
  355. * to RSTCTRL and RSTCFG
  356. */
  357. tmp = __raw_readl(KS2_RSTCTRL);
  358. tmp &= KS2_RSTCTRL_MASK;
  359. tmp |= KS2_RSTCTRL_KEY;
  360. __raw_writel(tmp, KS2_RSTCTRL);
  361. /*
  362. * Set PLL Controller to drive hard reset on SW trigger by
  363. * setting RSTCFG[13] = 0
  364. */
  365. tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
  366. tmp &= ~KS2_RSTYPE_PLL_SOFT;
  367. __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
  368. reset_cpu(0);
  369. }
  370. }
  371. #endif