scg.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <div64.h>
  7. #include <log.h>
  8. #include <asm/io.h>
  9. #include <errno.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/pcc.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <linux/delay.h>
  14. scg_p scg1_regs = (scg_p)SCG1_RBASE;
  15. static u32 scg_src_get_rate(enum scg_clk clksrc)
  16. {
  17. u32 reg;
  18. switch (clksrc) {
  19. case SCG_SOSC_CLK:
  20. reg = readl(&scg1_regs->sosccsr);
  21. if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
  22. return 0;
  23. return 24000000;
  24. case SCG_FIRC_CLK:
  25. reg = readl(&scg1_regs->firccsr);
  26. if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
  27. return 0;
  28. return 48000000;
  29. case SCG_SIRC_CLK:
  30. reg = readl(&scg1_regs->sirccsr);
  31. if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  32. return 0;
  33. return 16000000;
  34. case SCG_ROSC_CLK:
  35. reg = readl(&scg1_regs->rtccsr);
  36. if (!(reg & SCG_ROSC_CSR_ROSCVLD_MASK))
  37. return 0;
  38. return 32768;
  39. default:
  40. break;
  41. }
  42. return 0;
  43. }
  44. static u32 scg_sircdiv_get_rate(enum scg_clk clk)
  45. {
  46. u32 reg, val, rate;
  47. u32 shift, mask;
  48. switch (clk) {
  49. case SCG_SIRC_DIV1_CLK:
  50. mask = SCG_SIRCDIV_DIV1_MASK;
  51. shift = SCG_SIRCDIV_DIV1_SHIFT;
  52. break;
  53. case SCG_SIRC_DIV2_CLK:
  54. mask = SCG_SIRCDIV_DIV2_MASK;
  55. shift = SCG_SIRCDIV_DIV2_SHIFT;
  56. break;
  57. case SCG_SIRC_DIV3_CLK:
  58. mask = SCG_SIRCDIV_DIV3_MASK;
  59. shift = SCG_SIRCDIV_DIV3_SHIFT;
  60. break;
  61. default:
  62. return 0;
  63. }
  64. reg = readl(&scg1_regs->sirccsr);
  65. if (!(reg & SCG_SIRC_CSR_SIRCVLD_MASK))
  66. return 0;
  67. reg = readl(&scg1_regs->sircdiv);
  68. val = (reg & mask) >> shift;
  69. if (!val) /*clock disabled*/
  70. return 0;
  71. rate = scg_src_get_rate(SCG_SIRC_CLK);
  72. rate = rate / (1 << (val - 1));
  73. return rate;
  74. }
  75. static u32 scg_fircdiv_get_rate(enum scg_clk clk)
  76. {
  77. u32 reg, val, rate;
  78. u32 shift, mask;
  79. switch (clk) {
  80. case SCG_FIRC_DIV1_CLK:
  81. mask = SCG_FIRCDIV_DIV1_MASK;
  82. shift = SCG_FIRCDIV_DIV1_SHIFT;
  83. break;
  84. case SCG_FIRC_DIV2_CLK:
  85. mask = SCG_FIRCDIV_DIV2_MASK;
  86. shift = SCG_FIRCDIV_DIV2_SHIFT;
  87. break;
  88. case SCG_FIRC_DIV3_CLK:
  89. mask = SCG_FIRCDIV_DIV3_MASK;
  90. shift = SCG_FIRCDIV_DIV3_SHIFT;
  91. break;
  92. default:
  93. return 0;
  94. }
  95. reg = readl(&scg1_regs->firccsr);
  96. if (!(reg & SCG_FIRC_CSR_FIRCVLD_MASK))
  97. return 0;
  98. reg = readl(&scg1_regs->fircdiv);
  99. val = (reg & mask) >> shift;
  100. if (!val) /*clock disabled*/
  101. return 0;
  102. rate = scg_src_get_rate(SCG_FIRC_CLK);
  103. rate = rate / (1 << (val - 1));
  104. return rate;
  105. }
  106. static u32 scg_soscdiv_get_rate(enum scg_clk clk)
  107. {
  108. u32 reg, val, rate;
  109. u32 shift, mask;
  110. switch (clk) {
  111. case SCG_SOSC_DIV1_CLK:
  112. mask = SCG_SOSCDIV_DIV1_MASK;
  113. shift = SCG_SOSCDIV_DIV1_SHIFT;
  114. break;
  115. case SCG_SOSC_DIV2_CLK:
  116. mask = SCG_SOSCDIV_DIV2_MASK;
  117. shift = SCG_SOSCDIV_DIV2_SHIFT;
  118. break;
  119. case SCG_SOSC_DIV3_CLK:
  120. mask = SCG_SOSCDIV_DIV3_MASK;
  121. shift = SCG_SOSCDIV_DIV3_SHIFT;
  122. break;
  123. default:
  124. return 0;
  125. }
  126. reg = readl(&scg1_regs->sosccsr);
  127. if (!(reg & SCG_SOSC_CSR_SOSCVLD_MASK))
  128. return 0;
  129. reg = readl(&scg1_regs->soscdiv);
  130. val = (reg & mask) >> shift;
  131. if (!val) /*clock disabled*/
  132. return 0;
  133. rate = scg_src_get_rate(SCG_SOSC_CLK);
  134. rate = rate / (1 << (val - 1));
  135. return rate;
  136. }
  137. static u32 scg_apll_pfd_get_rate(enum scg_clk clk)
  138. {
  139. u32 reg, val, rate;
  140. u32 shift, mask, gate, valid;
  141. switch (clk) {
  142. case SCG_APLL_PFD0_CLK:
  143. gate = SCG_PLL_PFD0_GATE_MASK;
  144. valid = SCG_PLL_PFD0_VALID_MASK;
  145. mask = SCG_PLL_PFD0_FRAC_MASK;
  146. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  147. break;
  148. case SCG_APLL_PFD1_CLK:
  149. gate = SCG_PLL_PFD1_GATE_MASK;
  150. valid = SCG_PLL_PFD1_VALID_MASK;
  151. mask = SCG_PLL_PFD1_FRAC_MASK;
  152. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  153. break;
  154. case SCG_APLL_PFD2_CLK:
  155. gate = SCG_PLL_PFD2_GATE_MASK;
  156. valid = SCG_PLL_PFD2_VALID_MASK;
  157. mask = SCG_PLL_PFD2_FRAC_MASK;
  158. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  159. break;
  160. case SCG_APLL_PFD3_CLK:
  161. gate = SCG_PLL_PFD3_GATE_MASK;
  162. valid = SCG_PLL_PFD3_VALID_MASK;
  163. mask = SCG_PLL_PFD3_FRAC_MASK;
  164. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  165. break;
  166. default:
  167. return 0;
  168. }
  169. reg = readl(&scg1_regs->apllpfd);
  170. if (reg & gate || !(reg & valid))
  171. return 0;
  172. clk_debug("scg_apll_pfd_get_rate reg 0x%x\n", reg);
  173. val = (reg & mask) >> shift;
  174. rate = decode_pll(PLL_A7_APLL);
  175. rate = rate / val * 18;
  176. clk_debug("scg_apll_pfd_get_rate rate %u\n", rate);
  177. return rate;
  178. }
  179. static u32 scg_spll_pfd_get_rate(enum scg_clk clk)
  180. {
  181. u32 reg, val, rate;
  182. u32 shift, mask, gate, valid;
  183. switch (clk) {
  184. case SCG_SPLL_PFD0_CLK:
  185. gate = SCG_PLL_PFD0_GATE_MASK;
  186. valid = SCG_PLL_PFD0_VALID_MASK;
  187. mask = SCG_PLL_PFD0_FRAC_MASK;
  188. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  189. break;
  190. case SCG_SPLL_PFD1_CLK:
  191. gate = SCG_PLL_PFD1_GATE_MASK;
  192. valid = SCG_PLL_PFD1_VALID_MASK;
  193. mask = SCG_PLL_PFD1_FRAC_MASK;
  194. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  195. break;
  196. case SCG_SPLL_PFD2_CLK:
  197. gate = SCG_PLL_PFD2_GATE_MASK;
  198. valid = SCG_PLL_PFD2_VALID_MASK;
  199. mask = SCG_PLL_PFD2_FRAC_MASK;
  200. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  201. break;
  202. case SCG_SPLL_PFD3_CLK:
  203. gate = SCG_PLL_PFD3_GATE_MASK;
  204. valid = SCG_PLL_PFD3_VALID_MASK;
  205. mask = SCG_PLL_PFD3_FRAC_MASK;
  206. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  207. break;
  208. default:
  209. return 0;
  210. }
  211. reg = readl(&scg1_regs->spllpfd);
  212. if (reg & gate || !(reg & valid))
  213. return 0;
  214. clk_debug("scg_spll_pfd_get_rate reg 0x%x\n", reg);
  215. val = (reg & mask) >> shift;
  216. rate = decode_pll(PLL_A7_SPLL);
  217. rate = rate / val * 18;
  218. clk_debug("scg_spll_pfd_get_rate rate %u\n", rate);
  219. return rate;
  220. }
  221. static u32 scg_apll_get_rate(void)
  222. {
  223. u32 reg, val, rate;
  224. reg = readl(&scg1_regs->apllcfg);
  225. val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
  226. if (!val) {
  227. /* APLL clock after two dividers */
  228. rate = decode_pll(PLL_A7_APLL);
  229. val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
  230. SCG_PLL_CFG_POSTDIV1_SHIFT;
  231. rate = rate / (val + 1);
  232. val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
  233. SCG_PLL_CFG_POSTDIV2_SHIFT;
  234. rate = rate / (val + 1);
  235. } else {
  236. /* APLL PFD clock */
  237. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  238. SCG_PLL_CFG_PFDSEL_SHIFT;
  239. rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
  240. }
  241. return rate;
  242. }
  243. static u32 scg_spll_get_rate(void)
  244. {
  245. u32 reg, val, rate;
  246. reg = readl(&scg1_regs->spllcfg);
  247. val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT;
  248. clk_debug("scg_spll_get_rate reg 0x%x\n", reg);
  249. if (!val) {
  250. /* APLL clock after two dividers */
  251. rate = decode_pll(PLL_A7_SPLL);
  252. val = (reg & SCG_PLL_CFG_POSTDIV1_MASK) >>
  253. SCG_PLL_CFG_POSTDIV1_SHIFT;
  254. rate = rate / (val + 1);
  255. val = (reg & SCG_PLL_CFG_POSTDIV2_MASK) >>
  256. SCG_PLL_CFG_POSTDIV2_SHIFT;
  257. rate = rate / (val + 1);
  258. clk_debug("scg_spll_get_rate SPLL %u\n", rate);
  259. } else {
  260. /* APLL PFD clock */
  261. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  262. SCG_PLL_CFG_PFDSEL_SHIFT;
  263. rate = scg_spll_pfd_get_rate(SCG_SPLL_PFD0_CLK + val);
  264. clk_debug("scg_spll_get_rate PFD %u\n", rate);
  265. }
  266. return rate;
  267. }
  268. static u32 scg_ddr_get_rate(void)
  269. {
  270. u32 reg, val, rate, div;
  271. reg = readl(&scg1_regs->ddrccr);
  272. val = (reg & SCG_DDRCCR_DDRCS_MASK) >> SCG_DDRCCR_DDRCS_SHIFT;
  273. div = (reg & SCG_DDRCCR_DDRDIV_MASK) >> SCG_DDRCCR_DDRDIV_SHIFT;
  274. if (!div)
  275. return 0;
  276. if (!val) {
  277. reg = readl(&scg1_regs->apllcfg);
  278. val = (reg & SCG_PLL_CFG_PFDSEL_MASK) >>
  279. SCG_PLL_CFG_PFDSEL_SHIFT;
  280. rate = scg_apll_pfd_get_rate(SCG_APLL_PFD0_CLK + val);
  281. } else {
  282. rate = decode_pll(PLL_USB);
  283. }
  284. rate = rate / (1 << (div - 1));
  285. return rate;
  286. }
  287. static u32 scg_nic_get_rate(enum scg_clk clk)
  288. {
  289. u32 reg, val, rate, nic0_rate;
  290. u32 shift, mask;
  291. reg = readl(&scg1_regs->niccsr);
  292. val = (reg & SCG_NICCSR_NICCS_MASK) >> SCG_NICCSR_NICCS_SHIFT;
  293. clk_debug("scg_nic_get_rate niccsr 0x%x\n", reg);
  294. if (!val)
  295. rate = scg_src_get_rate(SCG_FIRC_CLK);
  296. else
  297. rate = scg_ddr_get_rate();
  298. clk_debug("scg_nic_get_rate parent rate %u\n", rate);
  299. val = (reg & SCG_NICCSR_NIC0DIV_MASK) >> SCG_NICCSR_NIC0DIV_SHIFT;
  300. rate = rate / (val + 1);
  301. nic0_rate = rate;
  302. clk_debug("scg_nic_get_rate NIC0 rate %u\n", rate);
  303. switch (clk) {
  304. case SCG_NIC0_CLK:
  305. return rate;
  306. case SCG_GPU_CLK:
  307. mask = SCG_NICCSR_GPUDIV_MASK;
  308. shift = SCG_NICCSR_GPUDIV_SHIFT;
  309. break;
  310. case SCG_NIC1_EXT_CLK:
  311. case SCG_NIC1_BUS_CLK:
  312. case SCG_NIC1_CLK:
  313. mask = SCG_NICCSR_NIC1DIV_MASK;
  314. shift = SCG_NICCSR_NIC1DIV_SHIFT;
  315. break;
  316. default:
  317. return 0;
  318. }
  319. val = (reg & mask) >> shift;
  320. rate = rate / (val + 1);
  321. clk_debug("scg_nic_get_rate NIC1 rate %u\n", rate);
  322. switch (clk) {
  323. case SCG_GPU_CLK:
  324. case SCG_NIC1_CLK:
  325. return rate;
  326. case SCG_NIC1_EXT_CLK:
  327. mask = SCG_NICCSR_NIC1EXTDIV_MASK;
  328. shift = SCG_NICCSR_NIC1EXTDIV_SHIFT;
  329. break;
  330. case SCG_NIC1_BUS_CLK:
  331. mask = SCG_NICCSR_NIC1BUSDIV_MASK;
  332. shift = SCG_NICCSR_NIC1BUSDIV_SHIFT;
  333. break;
  334. default:
  335. return 0;
  336. }
  337. /*
  338. * On RevB, the nic_bus and nic_ext dividers are parallel
  339. * not chained with nic div
  340. */
  341. if (soc_rev() >= CHIP_REV_2_0)
  342. rate = nic0_rate;
  343. val = (reg & mask) >> shift;
  344. rate = rate / (val + 1);
  345. clk_debug("scg_nic_get_rate NIC1 bus rate %u\n", rate);
  346. return rate;
  347. }
  348. static enum scg_clk scg_scs_array[4] = {
  349. SCG_SOSC_CLK, SCG_SIRC_CLK, SCG_FIRC_CLK, SCG_ROSC_CLK,
  350. };
  351. static u32 scg_sys_get_rate(enum scg_clk clk)
  352. {
  353. u32 reg, val, rate;
  354. if (clk != SCG_CORE_CLK && clk != SCG_BUS_CLK)
  355. return 0;
  356. reg = readl(&scg1_regs->csr);
  357. val = (reg & SCG_CCR_SCS_MASK) >> SCG_CCR_SCS_SHIFT;
  358. clk_debug("scg_sys_get_rate reg 0x%x\n", reg);
  359. switch (val) {
  360. case SCG_SCS_SYS_OSC:
  361. case SCG_SCS_SLOW_IRC:
  362. case SCG_SCS_FAST_IRC:
  363. case SCG_SCS_RTC_OSC:
  364. rate = scg_src_get_rate(scg_scs_array[val - 1]);
  365. break;
  366. case 5:
  367. rate = scg_apll_get_rate();
  368. break;
  369. case 6:
  370. rate = scg_spll_get_rate();
  371. break;
  372. default:
  373. return 0;
  374. }
  375. clk_debug("scg_sys_get_rate parent rate %u\n", rate);
  376. val = (reg & SCG_CCR_DIVCORE_MASK) >> SCG_CCR_DIVCORE_SHIFT;
  377. rate = rate / (val + 1);
  378. if (clk == SCG_BUS_CLK) {
  379. val = (reg & SCG_CCR_DIVBUS_MASK) >> SCG_CCR_DIVBUS_SHIFT;
  380. rate = rate / (val + 1);
  381. }
  382. return rate;
  383. }
  384. u32 decode_pll(enum pll_clocks pll)
  385. {
  386. u32 reg, pre_div, infreq, mult;
  387. u32 num, denom;
  388. /*
  389. * Alought there are four choices for the bypass src,
  390. * we choose OSC_24M which is the default set in ROM.
  391. */
  392. switch (pll) {
  393. case PLL_A7_SPLL:
  394. reg = readl(&scg1_regs->spllcsr);
  395. if (!(reg & SCG_SPLL_CSR_SPLLVLD_MASK))
  396. return 0;
  397. reg = readl(&scg1_regs->spllcfg);
  398. pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
  399. SCG_PLL_CFG_PREDIV_SHIFT;
  400. pre_div += 1;
  401. mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >>
  402. SCG_PLL_CFG_MULT_SHIFT;
  403. infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
  404. SCG_PLL_CFG_CLKSRC_SHIFT;
  405. if (!infreq)
  406. infreq = scg_src_get_rate(SCG_SOSC_CLK);
  407. else
  408. infreq = scg_src_get_rate(SCG_FIRC_CLK);
  409. num = readl(&scg1_regs->spllnum);
  410. denom = readl(&scg1_regs->splldenom);
  411. infreq = infreq / pre_div;
  412. if (denom)
  413. return infreq * mult + infreq * num / denom;
  414. else
  415. return infreq * mult;
  416. case PLL_A7_APLL:
  417. reg = readl(&scg1_regs->apllcsr);
  418. if (!(reg & SCG_APLL_CSR_APLLVLD_MASK))
  419. return 0;
  420. reg = readl(&scg1_regs->apllcfg);
  421. pre_div = (reg & SCG_PLL_CFG_PREDIV_MASK) >>
  422. SCG_PLL_CFG_PREDIV_SHIFT;
  423. pre_div += 1;
  424. mult = (reg & SCG_APLL_CFG_MULT_MASK) >>
  425. SCG_PLL_CFG_MULT_SHIFT;
  426. infreq = (reg & SCG_PLL_CFG_CLKSRC_MASK) >>
  427. SCG_PLL_CFG_CLKSRC_SHIFT;
  428. if (!infreq)
  429. infreq = scg_src_get_rate(SCG_SOSC_CLK);
  430. else
  431. infreq = scg_src_get_rate(SCG_FIRC_CLK);
  432. num = readl(&scg1_regs->apllnum);
  433. denom = readl(&scg1_regs->aplldenom);
  434. infreq = infreq / pre_div;
  435. if (denom)
  436. return infreq * mult + infreq * num / denom;
  437. else
  438. return infreq * mult;
  439. case PLL_USB:
  440. reg = readl(&scg1_regs->upllcsr);
  441. if (!(reg & SCG_UPLL_CSR_UPLLVLD_MASK))
  442. return 0;
  443. return 480000000u;
  444. case PLL_MIPI:
  445. return 480000000u;
  446. default:
  447. printf("Unsupported pll clocks %d\n", pll);
  448. break;
  449. }
  450. return 0;
  451. }
  452. u32 scg_clk_get_rate(enum scg_clk clk)
  453. {
  454. switch (clk) {
  455. case SCG_SIRC_DIV1_CLK:
  456. case SCG_SIRC_DIV2_CLK:
  457. case SCG_SIRC_DIV3_CLK:
  458. return scg_sircdiv_get_rate(clk);
  459. case SCG_FIRC_DIV1_CLK:
  460. case SCG_FIRC_DIV2_CLK:
  461. case SCG_FIRC_DIV3_CLK:
  462. return scg_fircdiv_get_rate(clk);
  463. case SCG_SOSC_DIV1_CLK:
  464. case SCG_SOSC_DIV2_CLK:
  465. case SCG_SOSC_DIV3_CLK:
  466. return scg_soscdiv_get_rate(clk);
  467. case SCG_CORE_CLK:
  468. case SCG_BUS_CLK:
  469. return scg_sys_get_rate(clk);
  470. case SCG_SPLL_PFD0_CLK:
  471. case SCG_SPLL_PFD1_CLK:
  472. case SCG_SPLL_PFD2_CLK:
  473. case SCG_SPLL_PFD3_CLK:
  474. return scg_spll_pfd_get_rate(clk);
  475. case SCG_APLL_PFD0_CLK:
  476. case SCG_APLL_PFD1_CLK:
  477. case SCG_APLL_PFD2_CLK:
  478. case SCG_APLL_PFD3_CLK:
  479. return scg_apll_pfd_get_rate(clk);
  480. case SCG_DDR_CLK:
  481. return scg_ddr_get_rate();
  482. case SCG_NIC0_CLK:
  483. case SCG_GPU_CLK:
  484. case SCG_NIC1_CLK:
  485. case SCG_NIC1_BUS_CLK:
  486. case SCG_NIC1_EXT_CLK:
  487. return scg_nic_get_rate(clk);
  488. case USB_PLL_OUT:
  489. return decode_pll(PLL_USB);
  490. case MIPI_PLL_OUT:
  491. return decode_pll(PLL_MIPI);
  492. case SCG_SOSC_CLK:
  493. case SCG_FIRC_CLK:
  494. case SCG_SIRC_CLK:
  495. case SCG_ROSC_CLK:
  496. return scg_src_get_rate(clk);
  497. default:
  498. return 0;
  499. }
  500. }
  501. int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
  502. {
  503. u32 reg;
  504. u32 shift, mask, gate, valid;
  505. u32 addr;
  506. if (frac < 12 || frac > 35)
  507. return -EINVAL;
  508. switch (clk) {
  509. case SCG_SPLL_PFD0_CLK:
  510. case SCG_APLL_PFD0_CLK:
  511. gate = SCG_PLL_PFD0_GATE_MASK;
  512. valid = SCG_PLL_PFD0_VALID_MASK;
  513. mask = SCG_PLL_PFD0_FRAC_MASK;
  514. shift = SCG_PLL_PFD0_FRAC_SHIFT;
  515. if (clk == SCG_SPLL_PFD0_CLK)
  516. addr = (u32)(&scg1_regs->spllpfd);
  517. else
  518. addr = (u32)(&scg1_regs->apllpfd);
  519. break;
  520. case SCG_SPLL_PFD1_CLK:
  521. case SCG_APLL_PFD1_CLK:
  522. gate = SCG_PLL_PFD1_GATE_MASK;
  523. valid = SCG_PLL_PFD1_VALID_MASK;
  524. mask = SCG_PLL_PFD1_FRAC_MASK;
  525. shift = SCG_PLL_PFD1_FRAC_SHIFT;
  526. if (clk == SCG_SPLL_PFD1_CLK)
  527. addr = (u32)(&scg1_regs->spllpfd);
  528. else
  529. addr = (u32)(&scg1_regs->apllpfd);
  530. break;
  531. case SCG_SPLL_PFD2_CLK:
  532. case SCG_APLL_PFD2_CLK:
  533. gate = SCG_PLL_PFD2_GATE_MASK;
  534. valid = SCG_PLL_PFD2_VALID_MASK;
  535. mask = SCG_PLL_PFD2_FRAC_MASK;
  536. shift = SCG_PLL_PFD2_FRAC_SHIFT;
  537. if (clk == SCG_SPLL_PFD2_CLK)
  538. addr = (u32)(&scg1_regs->spllpfd);
  539. else
  540. addr = (u32)(&scg1_regs->apllpfd);
  541. break;
  542. case SCG_SPLL_PFD3_CLK:
  543. case SCG_APLL_PFD3_CLK:
  544. gate = SCG_PLL_PFD3_GATE_MASK;
  545. valid = SCG_PLL_PFD3_VALID_MASK;
  546. mask = SCG_PLL_PFD3_FRAC_MASK;
  547. shift = SCG_PLL_PFD3_FRAC_SHIFT;
  548. if (clk == SCG_SPLL_PFD3_CLK)
  549. addr = (u32)(&scg1_regs->spllpfd);
  550. else
  551. addr = (u32)(&scg1_regs->apllpfd);
  552. break;
  553. default:
  554. return -EINVAL;
  555. }
  556. /* Gate the PFD */
  557. reg = readl(addr);
  558. reg |= gate;
  559. writel(reg, addr);
  560. /* Write Frac divider */
  561. reg &= ~mask;
  562. reg |= (frac << shift) & mask;
  563. writel(reg, addr);
  564. /*
  565. * Un-gate the PFD
  566. * (Need un-gate before checking valid, not align with RM)
  567. */
  568. reg &= ~gate;
  569. writel(reg, addr);
  570. /* Wait for PFD clock being valid */
  571. do {
  572. reg = readl(addr);
  573. } while (!(reg & valid));
  574. return 0;
  575. }
  576. #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
  577. int scg_enable_usb_pll(bool usb_control)
  578. {
  579. u32 sosc_rate;
  580. s32 timeout = 1000000;
  581. u32 reg;
  582. struct usbphy_regs *usbphy =
  583. (struct usbphy_regs *)USBPHY_RBASE;
  584. sosc_rate = scg_src_get_rate(SCG_SOSC_CLK);
  585. if (!sosc_rate)
  586. return -EPERM;
  587. reg = readl(SIM0_RBASE + 0x3C);
  588. if (usb_control)
  589. reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  590. else
  591. reg |= SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  592. writel(reg, SIM0_RBASE + 0x3C);
  593. if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
  594. writel(0x1c00000, &usbphy->usb1_pll_480_ctrl_clr);
  595. switch (sosc_rate) {
  596. case 24000000:
  597. writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
  598. break;
  599. case 30000000:
  600. writel(0x800000, &usbphy->usb1_pll_480_ctrl_set);
  601. break;
  602. case 19200000:
  603. writel(0x1400000, &usbphy->usb1_pll_480_ctrl_set);
  604. break;
  605. default:
  606. writel(0xc00000, &usbphy->usb1_pll_480_ctrl_set);
  607. break;
  608. }
  609. /* Enable the regulator first */
  610. writel(PLL_USB_REG_ENABLE_MASK,
  611. &usbphy->usb1_pll_480_ctrl_set);
  612. /* Wait at least 15us */
  613. udelay(15);
  614. /* Enable the power */
  615. writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
  616. /* Wait lock */
  617. while (timeout--) {
  618. if (readl(&usbphy->usb1_pll_480_ctrl) &
  619. PLL_USB_LOCK_MASK)
  620. break;
  621. }
  622. if (timeout <= 0) {
  623. /* If timeout, we power down the pll */
  624. writel(PLL_USB_PWR_MASK,
  625. &usbphy->usb1_pll_480_ctrl_clr);
  626. return -ETIME;
  627. }
  628. }
  629. /* Clear the bypass */
  630. writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
  631. /* Enable the PLL clock out to USB */
  632. writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
  633. &usbphy->usb1_pll_480_ctrl_set);
  634. if (!usb_control) {
  635. while (timeout--) {
  636. if (readl(&scg1_regs->upllcsr) &
  637. SCG_UPLL_CSR_UPLLVLD_MASK)
  638. break;
  639. }
  640. if (timeout <= 0) {
  641. reg = readl(SIM0_RBASE + 0x3C);
  642. reg &= ~SIM_MISC_CTRL0_USB_PLL_EN_MASK;
  643. writel(reg, SIM0_RBASE + 0x3C);
  644. return -ETIME;
  645. }
  646. }
  647. return 0;
  648. }
  649. /* A7 domain system clock source is SPLL */
  650. #define SCG1_RCCR_SCS_NUM ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT)
  651. /* A7 Core clck = SPLL PFD0 / 1 = 500MHz / 1 = 500MHz */
  652. #define SCG1_RCCR_DIVCORE_NUM ((0x0) << SCG_CCR_DIVCORE_SHIFT)
  653. #define SCG1_RCCR_CFG_MASK (SCG_CCR_SCS_MASK | SCG_CCR_DIVBUS_MASK)
  654. /* A7 Plat clck = A7 Core Clock / 2 = 250MHz / 1 = 250MHz */
  655. #define SCG1_RCCR_DIVBUS_NUM ((0x1) << SCG_CCR_DIVBUS_SHIFT)
  656. #define SCG1_RCCR_CFG_NUM (SCG1_RCCR_SCS_NUM | SCG1_RCCR_DIVBUS_NUM)
  657. void scg_a7_rccr_init(void)
  658. {
  659. u32 rccr_reg_val = 0;
  660. rccr_reg_val = readl(&scg1_regs->rccr);
  661. rccr_reg_val &= (~SCG1_RCCR_CFG_MASK);
  662. rccr_reg_val |= (SCG1_RCCR_CFG_NUM);
  663. writel(rccr_reg_val, &scg1_regs->rccr);
  664. }
  665. /* POSTDIV2 = 1 */
  666. #define SCG1_SPLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
  667. /* POSTDIV1 = 1 */
  668. #define SCG1_SPLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
  669. /* MULT = 22 */
  670. #define SCG1_SPLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
  671. /* PFD0 output clock selected */
  672. #define SCG1_SPLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
  673. /* PREDIV = 1 */
  674. #define SCG1_SPLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
  675. /* SPLL output clocks (including PFD outputs) selected */
  676. #define SCG1_SPLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
  677. /* SPLL PFD output clock selected */
  678. #define SCG1_SPLL_CFG_PLLSEL_NUM ((0x1) << SCG_PLL_CFG_PLLSEL_SHIFT)
  679. /* Clock source is System OSC */
  680. #define SCG1_SPLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
  681. #define SCG1_SPLL_CFG_NUM_24M_OSC (SCG1_SPLL_CFG_POSTDIV2_NUM | \
  682. SCG1_SPLL_CFG_POSTDIV1_NUM | \
  683. (22 << SCG_PLL_CFG_MULT_SHIFT) | \
  684. SCG1_SPLL_CFG_PFDSEL_NUM | \
  685. SCG1_SPLL_CFG_PREDIV_NUM | \
  686. SCG1_SPLL_CFG_BYPASS_NUM | \
  687. SCG1_SPLL_CFG_PLLSEL_NUM | \
  688. SCG1_SPLL_CFG_CLKSRC_NUM)
  689. /*413Mhz = A7 SPLL(528MHz) * 18/23 */
  690. #define SCG1_SPLL_PFD0_FRAC_NUM ((23) << SCG_PLL_PFD0_FRAC_SHIFT)
  691. void scg_a7_spll_init(void)
  692. {
  693. u32 val = 0;
  694. /* Disable A7 System PLL */
  695. val = readl(&scg1_regs->spllcsr);
  696. val &= ~SCG_SPLL_CSR_SPLLEN_MASK;
  697. writel(val, &scg1_regs->spllcsr);
  698. /*
  699. * Per block guide,
  700. * "When changing PFD values, it is recommneded PFDx clock
  701. * gets gated first by writing a value of 1 to PFDx_CLKGATE register,
  702. * then program the new PFD value, then poll the PFDx_VALID
  703. * flag to set before writing a value of 0 to PFDx_CLKGATE
  704. * to ungate the PFDx clock and allow PFDx clock to run"
  705. */
  706. /* Gate off A7 SPLL PFD0 ~ PDF4 */
  707. val = readl(&scg1_regs->spllpfd);
  708. val |= (SCG_PLL_PFD3_GATE_MASK |
  709. SCG_PLL_PFD2_GATE_MASK |
  710. SCG_PLL_PFD1_GATE_MASK |
  711. SCG_PLL_PFD0_GATE_MASK);
  712. writel(val, &scg1_regs->spllpfd);
  713. /* ================ A7 SPLL Configuration Start ============== */
  714. /* Configure A7 System PLL */
  715. writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);
  716. /* Enable A7 System PLL */
  717. val = readl(&scg1_regs->spllcsr);
  718. val |= SCG_SPLL_CSR_SPLLEN_MASK;
  719. writel(val, &scg1_regs->spllcsr);
  720. /* Wait for A7 SPLL clock ready */
  721. while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))
  722. ;
  723. /* Configure A7 SPLL PFD0 */
  724. val = readl(&scg1_regs->spllpfd);
  725. val &= ~SCG_PLL_PFD0_FRAC_MASK;
  726. val |= SCG1_SPLL_PFD0_FRAC_NUM;
  727. writel(val, &scg1_regs->spllpfd);
  728. /* Un-gate A7 SPLL PFD0 */
  729. val = readl(&scg1_regs->spllpfd);
  730. val &= ~SCG_PLL_PFD0_GATE_MASK;
  731. writel(val, &scg1_regs->spllpfd);
  732. /* Wait for A7 SPLL PFD0 clock being valid */
  733. while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))
  734. ;
  735. /* ================ A7 SPLL Configuration End ============== */
  736. }
  737. /* DDR clock source is APLL PFD0 (396MHz) */
  738. #define SCG1_DDRCCR_DDRCS_NUM ((0x0) << SCG_DDRCCR_DDRCS_SHIFT)
  739. /* DDR clock = APLL PFD0 / 1 = 396MHz / 1 = 396MHz */
  740. #define SCG1_DDRCCR_DDRDIV_NUM ((0x1) << SCG_DDRCCR_DDRDIV_SHIFT)
  741. /* DDR clock = APLL PFD0 / 2 = 396MHz / 2 = 198MHz */
  742. #define SCG1_DDRCCR_DDRDIV_LF_NUM ((0x2) << SCG_DDRCCR_DDRDIV_SHIFT)
  743. #define SCG1_DDRCCR_CFG_NUM (SCG1_DDRCCR_DDRCS_NUM | \
  744. SCG1_DDRCCR_DDRDIV_NUM)
  745. #define SCG1_DDRCCR_CFG_LF_NUM (SCG1_DDRCCR_DDRCS_NUM | \
  746. SCG1_DDRCCR_DDRDIV_LF_NUM)
  747. void scg_a7_ddrclk_init(void)
  748. {
  749. writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);
  750. }
  751. /* SCG1(A7) APLLCFG configurations */
  752. /* divide by 1 <<28 */
  753. #define SCG1_APLL_CFG_POSTDIV2_NUM ((0x0) << SCG_PLL_CFG_POSTDIV2_SHIFT)
  754. /* divide by 1 <<24 */
  755. #define SCG1_APLL_CFG_POSTDIV1_NUM ((0x0) << SCG_PLL_CFG_POSTDIV1_SHIFT)
  756. /* MULT is 22 <<16 */
  757. #define SCG1_APLL_CFG_MULT_NUM ((22) << SCG_PLL_CFG_MULT_SHIFT)
  758. /* PFD0 output clock selected <<14 */
  759. #define SCG1_APLL_CFG_PFDSEL_NUM ((0) << SCG_PLL_CFG_PFDSEL_SHIFT)
  760. /* PREDIV = 1 <<8 */
  761. #define SCG1_APLL_CFG_PREDIV_NUM ((0x0) << SCG_PLL_CFG_PREDIV_SHIFT)
  762. /* APLL output clocks (including PFD outputs) selected <<2 */
  763. #define SCG1_APLL_CFG_BYPASS_NUM ((0x0) << SCG_PLL_CFG_BYPASS_SHIFT)
  764. /* APLL PFD output clock selected <<1 */
  765. #define SCG1_APLL_CFG_PLLSEL_NUM ((0x0) << SCG_PLL_CFG_PLLSEL_SHIFT)
  766. /* Clock source is System OSC <<0 */
  767. #define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
  768. /* SCG1(A7) FIRC DIV configurations */
  769. /* Disable FIRC DIV3 */
  770. #define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
  771. /* FIRC DIV2 = 48MHz / 1 = 48MHz */
  772. #define SCG1_FIRCDIV_DIV2_NUM ((0x1) << SCG_FIRCDIV_DIV2_SHIFT)
  773. /* Disable FIRC DIV1 */
  774. #define SCG1_FIRCDIV_DIV1_NUM ((0x0) << SCG_FIRCDIV_DIV1_SHIFT)
  775. void scg_a7_firc_init(void)
  776. {
  777. /* Wait for FIRC clock ready */
  778. while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))
  779. ;
  780. /* Configure A7 FIRC DIV1 ~ DIV3 */
  781. writel((SCG1_FIRCDIV_DIV3_NUM |
  782. SCG1_FIRCDIV_DIV2_NUM |
  783. SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);
  784. }
  785. /* SCG1(A7) NICCCR configurations */
  786. /* NIC clock source is DDR clock (396/198MHz) */
  787. #define SCG1_NICCCR_NICCS_NUM ((0x1) << SCG_NICCCR_NICCS_SHIFT)
  788. /* NIC0 clock = DDR Clock / 2 = 396MHz / 2 = 198MHz */
  789. #define SCG1_NICCCR_NIC0_DIV_NUM ((0x1) << SCG_NICCCR_NIC0_DIV_SHIFT)
  790. /* NIC0 clock = DDR Clock / 1 = 198MHz / 1 = 198MHz */
  791. #define SCG1_NICCCR_NIC0_DIV_LF_NUM ((0x0) << SCG_NICCCR_NIC0_DIV_SHIFT)
  792. /* NIC1 clock = NIC0 Clock / 1 = 198MHz / 2 = 198MHz */
  793. #define SCG1_NICCCR_NIC1_DIV_NUM ((0x0) << SCG_NICCCR_NIC1_DIV_SHIFT)
  794. /* NIC1 bus clock = NIC1 Clock / 3 = 198MHz / 3 = 66MHz */
  795. #define SCG1_NICCCR_NIC1_DIVBUS_NUM ((0x2) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
  796. #define SCG1_NICCCR_CFG_NUM (SCG1_NICCCR_NICCS_NUM | \
  797. SCG1_NICCCR_NIC0_DIV_NUM | \
  798. SCG1_NICCCR_NIC1_DIV_NUM | \
  799. SCG1_NICCCR_NIC1_DIVBUS_NUM)
  800. void scg_a7_nicclk_init(void)
  801. {
  802. writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);
  803. }
  804. /* SCG1(A7) FIRC DIV configurations */
  805. /* Enable FIRC DIV3 */
  806. #define SCG1_SOSCDIV_DIV3_NUM ((0x1) << SCG_SOSCDIV_DIV3_SHIFT)
  807. /* FIRC DIV2 = 48MHz / 1 = 48MHz */
  808. #define SCG1_SOSCDIV_DIV2_NUM ((0x1) << SCG_SOSCDIV_DIV2_SHIFT)
  809. /* Enable FIRC DIV1 */
  810. #define SCG1_SOSCDIV_DIV1_NUM ((0x1) << SCG_SOSCDIV_DIV1_SHIFT)
  811. void scg_a7_soscdiv_init(void)
  812. {
  813. /* Wait for FIRC clock ready */
  814. while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))
  815. ;
  816. /* Configure A7 FIRC DIV1 ~ DIV3 */
  817. writel((SCG1_SOSCDIV_DIV3_NUM | SCG1_SOSCDIV_DIV2_NUM |
  818. SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);
  819. }
  820. void scg_a7_sys_clk_sel(enum scg_sys_src clk)
  821. {
  822. u32 rccr_reg_val = 0;
  823. clk_debug("%s: system clock selected as %s\n", "[SCG]",
  824. clk == SCG_SCS_SYS_OSC ? "SYS_OSC" :
  825. clk == SCG_SCS_SLOW_IRC ? "SLOW_IRC" :
  826. clk == SCG_SCS_FAST_IRC ? "FAST_IRC" :
  827. clk == SCG_SCS_RTC_OSC ? "RTC_OSC" :
  828. clk == SCG_SCS_AUX_PLL ? "AUX_PLL" :
  829. clk == SCG_SCS_SYS_PLL ? "SYS_PLL" :
  830. clk == SCG_SCS_USBPHY_PLL ? "USBPHY_PLL" :
  831. "Invalid source"
  832. );
  833. rccr_reg_val = readl(&scg1_regs->rccr);
  834. rccr_reg_val &= ~SCG_CCR_SCS_MASK;
  835. rccr_reg_val |= (clk << SCG_CCR_SCS_SHIFT);
  836. writel(rccr_reg_val, &scg1_regs->rccr);
  837. }
  838. void scg_a7_info(void)
  839. {
  840. debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));
  841. debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));
  842. debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));
  843. debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));
  844. }
  845. void scg_a7_init_core_clk(void)
  846. {
  847. u32 val = 0;
  848. /*
  849. * The normal target frequency for ULP B0 is 500Mhz,
  850. * but ROM set it to 413Mhz, need to change SPLL PFD0 FRAC
  851. */
  852. if (soc_rev() >= CHIP_REV_2_0) {
  853. /* Switch RCCR SCG to SOSC, firstly check the SOSC is valid */
  854. if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) {
  855. val = readl(&scg1_regs->rccr);
  856. val &= (~SCG_CCR_SCS_MASK);
  857. val |= ((SCG_SCS_SYS_OSC) << SCG_CCR_SCS_SHIFT);
  858. writel(val, &scg1_regs->rccr);
  859. /* Switch the PLLS to SPLL clk */
  860. val = readl(&scg1_regs->spllcfg);
  861. val &= ~SCG_PLL_CFG_PLLSEL_MASK;
  862. writel(val, &scg1_regs->spllcfg);
  863. /*
  864. * Re-configure PFD0 to 19,
  865. * A7 SPLL(528MHz) * 18 / 19 = 500MHz
  866. */
  867. scg_enable_pll_pfd(SCG_SPLL_PFD0_CLK, 19);
  868. /* Switch the PLLS to SPLL PFD0 */
  869. val = readl(&scg1_regs->spllcfg);
  870. val |= SCG_PLL_CFG_PLLSEL_MASK;
  871. writel(val, &scg1_regs->spllcfg);
  872. /* Set RCCR SCG to SPLL clk out */
  873. val = readl(&scg1_regs->rccr);
  874. val &= (~SCG_CCR_SCS_MASK);
  875. val |= ((SCG_SCS_SYS_PLL) << SCG_CCR_SCS_SHIFT);
  876. writel(val, &scg1_regs->rccr);
  877. }
  878. }
  879. }