clock_imx8mq.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <errno.h>
  14. #include <linux/delay.h>
  15. #include <linux/iopoll.h>
  16. static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  17. static u32 get_root_clk(enum clk_root_index clock_id);
  18. static u32 decode_frac_pll(enum clk_root_src frac_pll)
  19. {
  20. u32 pll_cfg0, pll_cfg1, pllout;
  21. u32 pll_refclk_sel, pll_refclk;
  22. u32 divr_val, divq_val, divf_val, divff, divfi;
  23. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  24. switch (frac_pll) {
  25. case ARM_PLL_CLK:
  26. pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
  27. pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
  28. pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
  29. pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
  30. break;
  31. default:
  32. printf("Frac PLL %d not supporte\n", frac_pll);
  33. return 0;
  34. }
  35. pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
  36. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  37. /* Power down */
  38. if (pll_cfg0 & FRAC_PLL_PD_MASK)
  39. return 0;
  40. /* output not enabled */
  41. if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
  42. return 0;
  43. pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
  44. if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
  45. pll_refclk = 25000000u;
  46. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
  47. pll_refclk = 27000000u;
  48. else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
  49. pll_refclk = 27000000u;
  50. else
  51. pll_refclk = 0;
  52. if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
  53. return pll_refclk;
  54. divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
  55. FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
  56. divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
  57. divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
  58. FRAC_PLL_FRAC_DIV_CTL_SHIFT;
  59. divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
  60. divf_val = 1 + divfi + divff / (1 << 24);
  61. pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
  62. ((divq_val + 1) * 2);
  63. return pllout / (pllout_div + 1);
  64. }
  65. static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
  66. {
  67. u32 pll_cfg0, pll_cfg1, pll_cfg2;
  68. u32 pll_refclk_sel, pll_refclk;
  69. u32 divr1, divr2, divf1, divf2, divq, div;
  70. u32 sse;
  71. u32 pll_clke;
  72. u32 pllout_div_shift, pllout_div_mask, pllout_div;
  73. u32 pllout;
  74. switch (sscg_pll) {
  75. case SYSTEM_PLL1_800M_CLK:
  76. case SYSTEM_PLL1_400M_CLK:
  77. case SYSTEM_PLL1_266M_CLK:
  78. case SYSTEM_PLL1_200M_CLK:
  79. case SYSTEM_PLL1_160M_CLK:
  80. case SYSTEM_PLL1_133M_CLK:
  81. case SYSTEM_PLL1_100M_CLK:
  82. case SYSTEM_PLL1_80M_CLK:
  83. case SYSTEM_PLL1_40M_CLK:
  84. pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
  85. pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
  86. pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
  87. pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
  88. pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
  89. break;
  90. case SYSTEM_PLL2_1000M_CLK:
  91. case SYSTEM_PLL2_500M_CLK:
  92. case SYSTEM_PLL2_333M_CLK:
  93. case SYSTEM_PLL2_250M_CLK:
  94. case SYSTEM_PLL2_200M_CLK:
  95. case SYSTEM_PLL2_166M_CLK:
  96. case SYSTEM_PLL2_125M_CLK:
  97. case SYSTEM_PLL2_100M_CLK:
  98. case SYSTEM_PLL2_50M_CLK:
  99. pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
  100. pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
  101. pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
  102. pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
  103. pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
  104. break;
  105. case SYSTEM_PLL3_CLK:
  106. pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
  107. pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
  108. pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
  109. pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
  110. pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
  111. break;
  112. case DRAM_PLL1_CLK:
  113. pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
  114. pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
  115. pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
  116. pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
  117. pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
  118. break;
  119. default:
  120. printf("sscg pll %d not supporte\n", sscg_pll);
  121. return 0;
  122. }
  123. switch (sscg_pll) {
  124. case DRAM_PLL1_CLK:
  125. pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
  126. div = 1;
  127. break;
  128. case SYSTEM_PLL3_CLK:
  129. pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
  130. div = 1;
  131. break;
  132. case SYSTEM_PLL2_1000M_CLK:
  133. case SYSTEM_PLL1_800M_CLK:
  134. pll_clke = SSCG_PLL_CLKE_MASK;
  135. div = 1;
  136. break;
  137. case SYSTEM_PLL2_500M_CLK:
  138. case SYSTEM_PLL1_400M_CLK:
  139. pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
  140. div = 2;
  141. break;
  142. case SYSTEM_PLL2_333M_CLK:
  143. case SYSTEM_PLL1_266M_CLK:
  144. pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
  145. div = 3;
  146. break;
  147. case SYSTEM_PLL2_250M_CLK:
  148. case SYSTEM_PLL1_200M_CLK:
  149. pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
  150. div = 4;
  151. break;
  152. case SYSTEM_PLL2_200M_CLK:
  153. case SYSTEM_PLL1_160M_CLK:
  154. pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
  155. div = 5;
  156. break;
  157. case SYSTEM_PLL2_166M_CLK:
  158. case SYSTEM_PLL1_133M_CLK:
  159. pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
  160. div = 6;
  161. break;
  162. case SYSTEM_PLL2_125M_CLK:
  163. case SYSTEM_PLL1_100M_CLK:
  164. pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
  165. div = 8;
  166. break;
  167. case SYSTEM_PLL2_100M_CLK:
  168. case SYSTEM_PLL1_80M_CLK:
  169. pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
  170. div = 10;
  171. break;
  172. case SYSTEM_PLL2_50M_CLK:
  173. case SYSTEM_PLL1_40M_CLK:
  174. pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
  175. div = 20;
  176. break;
  177. default:
  178. printf("sscg pll %d not supporte\n", sscg_pll);
  179. return 0;
  180. }
  181. /* Power down */
  182. if (pll_cfg0 & SSCG_PLL_PD_MASK)
  183. return 0;
  184. /* output not enabled */
  185. if ((pll_cfg0 & pll_clke) == 0)
  186. return 0;
  187. pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
  188. pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
  189. pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
  190. if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
  191. pll_refclk = 25000000u;
  192. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
  193. pll_refclk = 27000000u;
  194. else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
  195. pll_refclk = 27000000u;
  196. else
  197. pll_refclk = 0;
  198. /* We assume bypass1/2 are the same value */
  199. if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
  200. (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
  201. return pll_refclk;
  202. divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
  203. SSCG_PLL_REF_DIVR1_SHIFT;
  204. divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
  205. SSCG_PLL_REF_DIVR2_SHIFT;
  206. divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
  207. SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
  208. divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
  209. SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
  210. divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
  211. SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
  212. sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
  213. if (sse)
  214. sse = 8;
  215. else
  216. sse = 2;
  217. pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
  218. (divr2 + 1) * (divf2 + 1) / (divq + 1);
  219. return pllout / (pllout_div + 1) / div;
  220. }
  221. static u32 get_root_src_clk(enum clk_root_src root_src)
  222. {
  223. switch (root_src) {
  224. case OSC_25M_CLK:
  225. return 25000000;
  226. case OSC_27M_CLK:
  227. return 27000000;
  228. case OSC_32K_CLK:
  229. return 32768;
  230. case ARM_PLL_CLK:
  231. return decode_frac_pll(root_src);
  232. case SYSTEM_PLL1_800M_CLK:
  233. case SYSTEM_PLL1_400M_CLK:
  234. case SYSTEM_PLL1_266M_CLK:
  235. case SYSTEM_PLL1_200M_CLK:
  236. case SYSTEM_PLL1_160M_CLK:
  237. case SYSTEM_PLL1_133M_CLK:
  238. case SYSTEM_PLL1_100M_CLK:
  239. case SYSTEM_PLL1_80M_CLK:
  240. case SYSTEM_PLL1_40M_CLK:
  241. case SYSTEM_PLL2_1000M_CLK:
  242. case SYSTEM_PLL2_500M_CLK:
  243. case SYSTEM_PLL2_333M_CLK:
  244. case SYSTEM_PLL2_250M_CLK:
  245. case SYSTEM_PLL2_200M_CLK:
  246. case SYSTEM_PLL2_166M_CLK:
  247. case SYSTEM_PLL2_125M_CLK:
  248. case SYSTEM_PLL2_100M_CLK:
  249. case SYSTEM_PLL2_50M_CLK:
  250. case SYSTEM_PLL3_CLK:
  251. return decode_sscg_pll(root_src);
  252. case ARM_A53_ALT_CLK:
  253. return get_root_clk(ARM_A53_CLK_ROOT);
  254. default:
  255. return 0;
  256. }
  257. return 0;
  258. }
  259. static u32 get_root_clk(enum clk_root_index clock_id)
  260. {
  261. enum clk_root_src root_src;
  262. u32 post_podf, pre_podf, root_src_clk;
  263. if (clock_root_enabled(clock_id) <= 0)
  264. return 0;
  265. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  266. return 0;
  267. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  268. return 0;
  269. if (clock_get_src(clock_id, &root_src) < 0)
  270. return 0;
  271. root_src_clk = get_root_src_clk(root_src);
  272. return root_src_clk / (post_podf + 1) / (pre_podf + 1);
  273. }
  274. #ifdef CONFIG_MXC_OCOTP
  275. void enable_ocotp_clk(unsigned char enable)
  276. {
  277. clock_enable(CCGR_OCOTP, !!enable);
  278. }
  279. #endif
  280. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  281. {
  282. /* 0 - 3 is valid i2c num */
  283. if (i2c_num > 3)
  284. return -EINVAL;
  285. clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  286. return 0;
  287. }
  288. u32 get_arm_core_clk(void)
  289. {
  290. enum clk_root_src root_src;
  291. u32 root_src_clk;
  292. if (clock_get_src(CORE_SEL_CFG, &root_src) < 0)
  293. return 0;
  294. root_src_clk = get_root_src_clk(root_src);
  295. return root_src_clk;
  296. }
  297. unsigned int mxc_get_clock(enum mxc_clock clk)
  298. {
  299. u32 val;
  300. switch (clk) {
  301. case MXC_ARM_CLK:
  302. return get_arm_core_clk();
  303. case MXC_IPG_CLK:
  304. clock_get_target_val(IPG_CLK_ROOT, &val);
  305. val = val & 0x3;
  306. return get_root_clk(AHB_CLK_ROOT) / (val + 1);
  307. case MXC_ESDHC_CLK:
  308. return get_root_clk(USDHC1_CLK_ROOT);
  309. case MXC_ESDHC2_CLK:
  310. return get_root_clk(USDHC2_CLK_ROOT);
  311. default:
  312. return get_root_clk(clk);
  313. }
  314. }
  315. u32 imx_get_uartclk(void)
  316. {
  317. return mxc_get_clock(UART1_CLK_ROOT);
  318. }
  319. void mxs_set_lcdclk(u32 base_addr, u32 freq)
  320. {
  321. /*
  322. * LCDIF_PIXEL_CLK: select 800MHz root clock,
  323. * select pre divider 8, output is 100 MHz
  324. */
  325. clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
  326. CLK_ROOT_SOURCE_SEL(4) |
  327. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
  328. }
  329. void init_wdog_clk(void)
  330. {
  331. clock_enable(CCGR_WDOG1, 0);
  332. clock_enable(CCGR_WDOG2, 0);
  333. clock_enable(CCGR_WDOG3, 0);
  334. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  335. CLK_ROOT_SOURCE_SEL(0));
  336. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  337. CLK_ROOT_SOURCE_SEL(0));
  338. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  339. CLK_ROOT_SOURCE_SEL(0));
  340. clock_enable(CCGR_WDOG1, 1);
  341. clock_enable(CCGR_WDOG2, 1);
  342. clock_enable(CCGR_WDOG3, 1);
  343. }
  344. void init_nand_clk(void)
  345. {
  346. clock_enable(CCGR_RAWNAND, 0);
  347. clock_set_target_val(NAND_CLK_ROOT,
  348. CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
  349. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
  350. clock_enable(CCGR_RAWNAND, 1);
  351. }
  352. void init_uart_clk(u32 index)
  353. {
  354. /* Set uart clock root 25M OSC */
  355. switch (index) {
  356. case 0:
  357. clock_enable(CCGR_UART1, 0);
  358. clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
  359. CLK_ROOT_SOURCE_SEL(0));
  360. clock_enable(CCGR_UART1, 1);
  361. return;
  362. case 1:
  363. clock_enable(CCGR_UART2, 0);
  364. clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
  365. CLK_ROOT_SOURCE_SEL(0));
  366. clock_enable(CCGR_UART2, 1);
  367. return;
  368. case 2:
  369. clock_enable(CCGR_UART3, 0);
  370. clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
  371. CLK_ROOT_SOURCE_SEL(0));
  372. clock_enable(CCGR_UART3, 1);
  373. return;
  374. case 3:
  375. clock_enable(CCGR_UART4, 0);
  376. clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
  377. CLK_ROOT_SOURCE_SEL(0));
  378. clock_enable(CCGR_UART4, 1);
  379. return;
  380. default:
  381. printf("Invalid uart index\n");
  382. return;
  383. }
  384. }
  385. void init_clk_usdhc(u32 index)
  386. {
  387. /*
  388. * set usdhc clock root
  389. * sys pll1 400M
  390. */
  391. switch (index) {
  392. case 0:
  393. clock_enable(CCGR_USDHC1, 0);
  394. clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
  395. CLK_ROOT_SOURCE_SEL(1));
  396. clock_enable(CCGR_USDHC1, 1);
  397. return;
  398. case 1:
  399. clock_enable(CCGR_USDHC2, 0);
  400. clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
  401. CLK_ROOT_SOURCE_SEL(1));
  402. clock_enable(CCGR_USDHC2, 1);
  403. return;
  404. default:
  405. printf("Invalid usdhc index\n");
  406. return;
  407. }
  408. }
  409. int set_clk_qspi(void)
  410. {
  411. /*
  412. * set qspi root
  413. * sys pll1 100M
  414. */
  415. clock_enable(CCGR_QSPI, 0);
  416. clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
  417. CLK_ROOT_SOURCE_SEL(7));
  418. clock_enable(CCGR_QSPI, 1);
  419. return 0;
  420. }
  421. #ifdef CONFIG_FEC_MXC
  422. int set_clk_enet(enum enet_freq type)
  423. {
  424. u32 target;
  425. u32 enet1_ref;
  426. switch (type) {
  427. case ENET_125MHZ:
  428. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  429. break;
  430. case ENET_50MHZ:
  431. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  432. break;
  433. case ENET_25MHZ:
  434. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  435. break;
  436. default:
  437. return -EINVAL;
  438. }
  439. /* disable the clock first */
  440. clock_enable(CCGR_ENET1, 0);
  441. clock_enable(CCGR_SIM_ENET, 0);
  442. /* set enet axi clock 266Mhz */
  443. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
  444. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  445. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  446. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  447. target = CLK_ROOT_ON | enet1_ref |
  448. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  449. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  450. clock_set_target_val(ENET_REF_CLK_ROOT, target);
  451. target = CLK_ROOT_ON |
  452. ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  453. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  454. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  455. clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
  456. /* enable clock */
  457. clock_enable(CCGR_SIM_ENET, 1);
  458. clock_enable(CCGR_ENET1, 1);
  459. return 0;
  460. }
  461. #endif
  462. u32 imx_get_fecclk(void)
  463. {
  464. return get_root_clk(ENET_AXI_CLK_ROOT);
  465. }
  466. static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
  467. DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
  468. CLK_ROOT_PRE_DIV2),
  469. DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
  470. CLK_ROOT_PRE_DIV2),
  471. DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
  472. CLK_ROOT_PRE_DIV2),
  473. };
  474. void dram_enable_bypass(ulong clk_val)
  475. {
  476. int i;
  477. struct dram_bypass_clk_setting *config;
  478. for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
  479. if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
  480. break;
  481. }
  482. if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
  483. printf("No matched freq table %lu\n", clk_val);
  484. return;
  485. }
  486. config = &imx8mq_dram_bypass_tbl[i];
  487. clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
  488. CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
  489. CLK_ROOT_PRE_DIV(config->alt_pre_div));
  490. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  491. CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
  492. CLK_ROOT_PRE_DIV(config->apb_pre_div));
  493. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  494. CLK_ROOT_SOURCE_SEL(1));
  495. }
  496. void dram_disable_bypass(void)
  497. {
  498. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  499. CLK_ROOT_SOURCE_SEL(0));
  500. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  501. CLK_ROOT_SOURCE_SEL(4) |
  502. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
  503. }
  504. #ifdef CONFIG_SPL_BUILD
  505. void dram_pll_init(ulong pll_val)
  506. {
  507. u32 val;
  508. void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
  509. void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
  510. /* Bypass */
  511. setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
  512. setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
  513. switch (pll_val) {
  514. case MHZ(800):
  515. val = readl(pll_cfg_reg2);
  516. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  517. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  518. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  519. SSCG_PLL_REF_DIVR2_MASK);
  520. val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
  521. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
  522. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  523. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  524. writel(val, pll_cfg_reg2);
  525. break;
  526. case MHZ(600):
  527. val = readl(pll_cfg_reg2);
  528. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  529. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  530. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  531. SSCG_PLL_REF_DIVR2_MASK);
  532. val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
  533. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
  534. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  535. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  536. writel(val, pll_cfg_reg2);
  537. break;
  538. case MHZ(400):
  539. val = readl(pll_cfg_reg2);
  540. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  541. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  542. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  543. SSCG_PLL_REF_DIVR2_MASK);
  544. val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
  545. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
  546. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
  547. val |= SSCG_PLL_REF_DIVR2_VAL(29);
  548. writel(val, pll_cfg_reg2);
  549. break;
  550. case MHZ(167):
  551. val = readl(pll_cfg_reg2);
  552. val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
  553. SSCG_PLL_FEEDBACK_DIV_F2_MASK |
  554. SSCG_PLL_FEEDBACK_DIV_F1_MASK |
  555. SSCG_PLL_REF_DIVR2_MASK);
  556. val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
  557. val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
  558. val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
  559. val |= SSCG_PLL_REF_DIVR2_VAL(30);
  560. writel(val, pll_cfg_reg2);
  561. break;
  562. default:
  563. break;
  564. }
  565. /* Clear power down bit */
  566. clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
  567. /* Eanble ARM_PLL/SYS_PLL */
  568. setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
  569. /* Clear bypass */
  570. clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
  571. __udelay(100);
  572. clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
  573. /* Wait lock */
  574. while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
  575. ;
  576. }
  577. static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
  578. {
  579. void __iomem *pll_cfg0, __iomem *pll_cfg1;
  580. u32 val_cfg0, val_cfg1, divq;
  581. int ret;
  582. switch (pll) {
  583. case ANATOP_ARM_PLL:
  584. pll_cfg0 = &ana_pll->arm_pll_cfg0;
  585. pll_cfg1 = &ana_pll->arm_pll_cfg1;
  586. if (val == FRAC_PLL_OUT_1000M) {
  587. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
  588. divq = 0;
  589. } else {
  590. val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
  591. divq = 1;
  592. }
  593. val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
  594. FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
  595. FRAC_PLL_REFCLK_DIV_VAL(4) |
  596. FRAC_PLL_OUTPUT_DIV_VAL(divq);
  597. break;
  598. default:
  599. return -EINVAL;
  600. }
  601. /* bypass the clock */
  602. setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  603. /* Set the value */
  604. writel(val_cfg1, pll_cfg1);
  605. writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
  606. val_cfg0 = readl(pll_cfg0);
  607. /* unbypass the clock */
  608. clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
  609. ret = readl_poll_timeout(pll_cfg0, val_cfg0,
  610. val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
  611. if (ret)
  612. printf("%s timeout\n", __func__);
  613. clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
  614. return 0;
  615. }
  616. int clock_init(void)
  617. {
  618. u32 grade;
  619. clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
  620. CLK_ROOT_SOURCE_SEL(0));
  621. /*
  622. * 8MQ only supports two grades: consumer and industrial.
  623. * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
  624. */
  625. grade = get_cpu_temp_grade(NULL, NULL);
  626. if (!grade)
  627. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
  628. else
  629. frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M);
  630. /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */
  631. clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1));
  632. /*
  633. * According to ANAMIX SPEC
  634. * sys pll1 fixed at 800MHz
  635. * sys pll2 fixed at 1GHz
  636. * Here we only enable the outputs.
  637. */
  638. setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
  639. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  640. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  641. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  642. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  643. setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
  644. SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
  645. SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
  646. SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
  647. SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
  648. clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
  649. CLK_ROOT_SOURCE_SEL(1));
  650. init_wdog_clk();
  651. clock_enable(CCGR_TSENSOR, 1);
  652. clock_enable(CCGR_OCOTP, 1);
  653. /* config GIC ROOT to sys_pll2_200m */
  654. clock_enable(CCGR_GIC, 0);
  655. clock_set_target_val(GIC_CLK_ROOT,
  656. CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
  657. clock_enable(CCGR_GIC, 1);
  658. return 0;
  659. }
  660. #endif
  661. /*
  662. * Dump some clockes.
  663. */
  664. #ifndef CONFIG_SPL_BUILD
  665. static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  666. char *const argv[])
  667. {
  668. u32 freq;
  669. freq = decode_frac_pll(ARM_PLL_CLK);
  670. printf("ARM_PLL %8d MHz\n", freq / 1000000);
  671. freq = decode_sscg_pll(DRAM_PLL1_CLK);
  672. printf("DRAM_PLL %8d MHz\n", freq / 1000000);
  673. freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
  674. printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
  675. freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
  676. printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
  677. freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
  678. printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
  679. freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
  680. printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
  681. freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
  682. printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
  683. freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
  684. printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
  685. freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
  686. printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
  687. freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
  688. printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
  689. freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
  690. printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
  691. freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
  692. printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
  693. freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
  694. printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
  695. freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
  696. printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
  697. freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
  698. printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
  699. freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
  700. printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
  701. freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
  702. printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
  703. freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
  704. printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
  705. freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
  706. printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
  707. freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
  708. printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
  709. freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
  710. printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
  711. freq = mxc_get_clock(UART1_CLK_ROOT);
  712. printf("UART1 %8d MHz\n", freq / 1000000);
  713. freq = mxc_get_clock(USDHC1_CLK_ROOT);
  714. printf("USDHC1 %8d MHz\n", freq / 1000000);
  715. freq = mxc_get_clock(QSPI_CLK_ROOT);
  716. printf("QSPI %8d MHz\n", freq / 1000000);
  717. return 0;
  718. }
  719. U_BOOT_CMD(
  720. clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
  721. "display clocks",
  722. ""
  723. );
  724. #endif