clock_imx8mm.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/io.h>
  12. #include <div64.h>
  13. #include <errno.h>
  14. #include <linux/delay.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  17. void enable_ocotp_clk(unsigned char enable)
  18. {
  19. clock_enable(CCGR_OCOTP, !!enable);
  20. }
  21. int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
  22. {
  23. /* 0 - 3 is valid i2c num */
  24. if (i2c_num > 3)
  25. return -EINVAL;
  26. clock_enable(CCGR_I2C1 + i2c_num, !!enable);
  27. return 0;
  28. }
  29. #ifdef CONFIG_SPL_BUILD
  30. static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
  31. PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
  32. PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
  33. PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
  34. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  35. PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
  36. PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
  37. PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
  38. PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
  39. PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
  40. PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
  41. };
  42. static int fracpll_configure(enum pll_clocks pll, u32 freq)
  43. {
  44. int i;
  45. u32 tmp, div_val;
  46. void *pll_base;
  47. struct imx_int_pll_rate_table *rate;
  48. for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
  49. if (freq == imx8mm_fracpll_tbl[i].rate)
  50. break;
  51. }
  52. if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
  53. printf("No matched freq table %u\n", freq);
  54. return -EINVAL;
  55. }
  56. rate = &imx8mm_fracpll_tbl[i];
  57. switch (pll) {
  58. case ANATOP_DRAM_PLL:
  59. setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
  60. setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
  61. writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
  62. pll_base = &ana_pll->dram_pll_gnrl_ctl;
  63. break;
  64. case ANATOP_VIDEO_PLL:
  65. pll_base = &ana_pll->video_pll1_gnrl_ctl;
  66. break;
  67. default:
  68. return 0;
  69. }
  70. /* Bypass clock and set lock to pll output lock */
  71. tmp = readl(pll_base);
  72. tmp |= BYPASS_MASK;
  73. writel(tmp, pll_base);
  74. /* Enable RST */
  75. tmp &= ~RST_MASK;
  76. writel(tmp, pll_base);
  77. div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
  78. (rate->sdiv << SDIV_SHIFT);
  79. writel(div_val, pll_base + 4);
  80. writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
  81. __udelay(100);
  82. /* Disable RST */
  83. tmp |= RST_MASK;
  84. writel(tmp, pll_base);
  85. /* Wait Lock*/
  86. while (!(readl(pll_base) & LOCK_STATUS))
  87. ;
  88. /* Bypass */
  89. tmp &= ~BYPASS_MASK;
  90. writel(tmp, pll_base);
  91. return 0;
  92. }
  93. void dram_pll_init(ulong pll_val)
  94. {
  95. fracpll_configure(ANATOP_DRAM_PLL, pll_val);
  96. }
  97. static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
  98. DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
  99. CLK_ROOT_PRE_DIV2),
  100. DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
  101. CLK_ROOT_PRE_DIV2),
  102. DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
  103. CLK_ROOT_PRE_DIV2),
  104. };
  105. void dram_enable_bypass(ulong clk_val)
  106. {
  107. int i;
  108. struct dram_bypass_clk_setting *config;
  109. for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
  110. if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
  111. break;
  112. }
  113. if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
  114. printf("No matched freq table %lu\n", clk_val);
  115. return;
  116. }
  117. config = &imx8mm_dram_bypass_tbl[i];
  118. clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
  119. CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
  120. CLK_ROOT_PRE_DIV(config->alt_pre_div));
  121. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  122. CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
  123. CLK_ROOT_PRE_DIV(config->apb_pre_div));
  124. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  125. CLK_ROOT_SOURCE_SEL(1));
  126. }
  127. void dram_disable_bypass(void)
  128. {
  129. clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
  130. CLK_ROOT_SOURCE_SEL(0));
  131. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  132. CLK_ROOT_SOURCE_SEL(4) |
  133. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
  134. }
  135. #endif
  136. void init_uart_clk(u32 index)
  137. {
  138. /*
  139. * set uart clock root
  140. * 24M OSC
  141. */
  142. switch (index) {
  143. case 0:
  144. clock_enable(CCGR_UART1, 0);
  145. clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
  146. CLK_ROOT_SOURCE_SEL(0));
  147. clock_enable(CCGR_UART1, 1);
  148. return;
  149. case 1:
  150. clock_enable(CCGR_UART2, 0);
  151. clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
  152. CLK_ROOT_SOURCE_SEL(0));
  153. clock_enable(CCGR_UART2, 1);
  154. return;
  155. case 2:
  156. clock_enable(CCGR_UART3, 0);
  157. clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
  158. CLK_ROOT_SOURCE_SEL(0));
  159. clock_enable(CCGR_UART3, 1);
  160. return;
  161. case 3:
  162. clock_enable(CCGR_UART4, 0);
  163. clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
  164. CLK_ROOT_SOURCE_SEL(0));
  165. clock_enable(CCGR_UART4, 1);
  166. return;
  167. default:
  168. printf("Invalid uart index\n");
  169. return;
  170. }
  171. }
  172. void init_wdog_clk(void)
  173. {
  174. clock_enable(CCGR_WDOG1, 0);
  175. clock_enable(CCGR_WDOG2, 0);
  176. clock_enable(CCGR_WDOG3, 0);
  177. clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
  178. CLK_ROOT_SOURCE_SEL(0));
  179. clock_enable(CCGR_WDOG1, 1);
  180. clock_enable(CCGR_WDOG2, 1);
  181. clock_enable(CCGR_WDOG3, 1);
  182. }
  183. int clock_init(void)
  184. {
  185. u32 val_cfg0;
  186. /*
  187. * The gate is not exported to clk tree, so configure them here.
  188. * According to ANAMIX SPEC
  189. * sys pll1 fixed at 800MHz
  190. * sys pll2 fixed at 1GHz
  191. * Here we only enable the outputs.
  192. */
  193. val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
  194. val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
  195. INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
  196. INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
  197. INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
  198. INTPLL_DIV20_CLKE_MASK;
  199. writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
  200. val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
  201. val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
  202. INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
  203. INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
  204. INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
  205. INTPLL_DIV20_CLKE_MASK;
  206. writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
  207. /* config GIC to sys_pll2_100m */
  208. clock_enable(CCGR_GIC, 0);
  209. clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
  210. CLK_ROOT_SOURCE_SEL(3));
  211. clock_enable(CCGR_GIC, 1);
  212. clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
  213. CLK_ROOT_SOURCE_SEL(1));
  214. clock_enable(CCGR_DDR1, 0);
  215. clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
  216. CLK_ROOT_SOURCE_SEL(1));
  217. clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
  218. CLK_ROOT_SOURCE_SEL(1));
  219. clock_enable(CCGR_DDR1, 1);
  220. init_wdog_clk();
  221. clock_enable(CCGR_TEMP_SENSOR, 1);
  222. clock_enable(CCGR_SEC_DEBUG, 1);
  223. return 0;
  224. };
  225. u32 imx_get_uartclk(void)
  226. {
  227. return 24000000U;
  228. }
  229. static u32 decode_intpll(enum clk_root_src intpll)
  230. {
  231. u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
  232. u32 main_div, pre_div, post_div, div;
  233. u64 freq;
  234. switch (intpll) {
  235. case ARM_PLL_CLK:
  236. pll_gnrl_ctl = readl(&ana_pll->arm_pll_gnrl_ctl);
  237. pll_div_ctl = readl(&ana_pll->arm_pll_div_ctl);
  238. break;
  239. case GPU_PLL_CLK:
  240. pll_gnrl_ctl = readl(&ana_pll->gpu_pll_gnrl_ctl);
  241. pll_div_ctl = readl(&ana_pll->gpu_pll_div_ctl);
  242. break;
  243. case VPU_PLL_CLK:
  244. pll_gnrl_ctl = readl(&ana_pll->vpu_pll_gnrl_ctl);
  245. pll_div_ctl = readl(&ana_pll->vpu_pll_div_ctl);
  246. break;
  247. case SYSTEM_PLL1_800M_CLK:
  248. case SYSTEM_PLL1_400M_CLK:
  249. case SYSTEM_PLL1_266M_CLK:
  250. case SYSTEM_PLL1_200M_CLK:
  251. case SYSTEM_PLL1_160M_CLK:
  252. case SYSTEM_PLL1_133M_CLK:
  253. case SYSTEM_PLL1_100M_CLK:
  254. case SYSTEM_PLL1_80M_CLK:
  255. case SYSTEM_PLL1_40M_CLK:
  256. pll_gnrl_ctl = readl(&ana_pll->sys_pll1_gnrl_ctl);
  257. pll_div_ctl = readl(&ana_pll->sys_pll1_div_ctl);
  258. break;
  259. case SYSTEM_PLL2_1000M_CLK:
  260. case SYSTEM_PLL2_500M_CLK:
  261. case SYSTEM_PLL2_333M_CLK:
  262. case SYSTEM_PLL2_250M_CLK:
  263. case SYSTEM_PLL2_200M_CLK:
  264. case SYSTEM_PLL2_166M_CLK:
  265. case SYSTEM_PLL2_125M_CLK:
  266. case SYSTEM_PLL2_100M_CLK:
  267. case SYSTEM_PLL2_50M_CLK:
  268. pll_gnrl_ctl = readl(&ana_pll->sys_pll2_gnrl_ctl);
  269. pll_div_ctl = readl(&ana_pll->sys_pll2_div_ctl);
  270. break;
  271. case SYSTEM_PLL3_CLK:
  272. pll_gnrl_ctl = readl(&ana_pll->sys_pll3_gnrl_ctl);
  273. pll_div_ctl = readl(&ana_pll->sys_pll3_div_ctl);
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
  279. if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0)
  280. return 0;
  281. if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0)
  282. return 0;
  283. /*
  284. * When BYPASS is equal to 1, PLL enters the bypass mode
  285. * regardless of the values of RESETB
  286. */
  287. if (pll_gnrl_ctl & INTPLL_BYPASS_MASK)
  288. return 24000000u;
  289. if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) {
  290. puts("pll not locked\n");
  291. return 0;
  292. }
  293. switch (intpll) {
  294. case ARM_PLL_CLK:
  295. case GPU_PLL_CLK:
  296. case VPU_PLL_CLK:
  297. case SYSTEM_PLL3_CLK:
  298. case SYSTEM_PLL1_800M_CLK:
  299. case SYSTEM_PLL2_1000M_CLK:
  300. pll_clke_mask = INTPLL_CLKE_MASK;
  301. div = 1;
  302. break;
  303. case SYSTEM_PLL1_400M_CLK:
  304. case SYSTEM_PLL2_500M_CLK:
  305. pll_clke_mask = INTPLL_DIV2_CLKE_MASK;
  306. div = 2;
  307. break;
  308. case SYSTEM_PLL1_266M_CLK:
  309. case SYSTEM_PLL2_333M_CLK:
  310. pll_clke_mask = INTPLL_DIV3_CLKE_MASK;
  311. div = 3;
  312. break;
  313. case SYSTEM_PLL1_200M_CLK:
  314. case SYSTEM_PLL2_250M_CLK:
  315. pll_clke_mask = INTPLL_DIV4_CLKE_MASK;
  316. div = 4;
  317. break;
  318. case SYSTEM_PLL1_160M_CLK:
  319. case SYSTEM_PLL2_200M_CLK:
  320. pll_clke_mask = INTPLL_DIV5_CLKE_MASK;
  321. div = 5;
  322. break;
  323. case SYSTEM_PLL1_133M_CLK:
  324. case SYSTEM_PLL2_166M_CLK:
  325. pll_clke_mask = INTPLL_DIV6_CLKE_MASK;
  326. div = 6;
  327. break;
  328. case SYSTEM_PLL1_100M_CLK:
  329. case SYSTEM_PLL2_125M_CLK:
  330. pll_clke_mask = INTPLL_DIV8_CLKE_MASK;
  331. div = 8;
  332. break;
  333. case SYSTEM_PLL1_80M_CLK:
  334. case SYSTEM_PLL2_100M_CLK:
  335. pll_clke_mask = INTPLL_DIV10_CLKE_MASK;
  336. div = 10;
  337. break;
  338. case SYSTEM_PLL1_40M_CLK:
  339. case SYSTEM_PLL2_50M_CLK:
  340. pll_clke_mask = INTPLL_DIV20_CLKE_MASK;
  341. div = 20;
  342. break;
  343. default:
  344. return -EINVAL;
  345. }
  346. if ((pll_gnrl_ctl & pll_clke_mask) == 0)
  347. return 0;
  348. main_div = (pll_div_ctl & INTPLL_MAIN_DIV_MASK) >>
  349. INTPLL_MAIN_DIV_SHIFT;
  350. pre_div = (pll_div_ctl & INTPLL_PRE_DIV_MASK) >>
  351. INTPLL_PRE_DIV_SHIFT;
  352. post_div = (pll_div_ctl & INTPLL_POST_DIV_MASK) >>
  353. INTPLL_POST_DIV_SHIFT;
  354. /* FFVCO = (m * FFIN) / p, FFOUT = (m * FFIN) / (p * 2^s) */
  355. freq = 24000000ULL * main_div;
  356. return lldiv(freq, pre_div * (1 << post_div) * div);
  357. }
  358. static u32 decode_fracpll(enum clk_root_src frac_pll)
  359. {
  360. u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
  361. u32 main_div, pre_div, post_div, k;
  362. switch (frac_pll) {
  363. case DRAM_PLL1_CLK:
  364. pll_gnrl_ctl = readl(&ana_pll->dram_pll_gnrl_ctl);
  365. pll_fdiv_ctl0 = readl(&ana_pll->dram_pll_fdiv_ctl0);
  366. pll_fdiv_ctl1 = readl(&ana_pll->dram_pll_fdiv_ctl1);
  367. break;
  368. case AUDIO_PLL1_CLK:
  369. pll_gnrl_ctl = readl(&ana_pll->audio_pll1_gnrl_ctl);
  370. pll_fdiv_ctl0 = readl(&ana_pll->audio_pll1_fdiv_ctl0);
  371. pll_fdiv_ctl1 = readl(&ana_pll->audio_pll1_fdiv_ctl1);
  372. break;
  373. case AUDIO_PLL2_CLK:
  374. pll_gnrl_ctl = readl(&ana_pll->audio_pll2_gnrl_ctl);
  375. pll_fdiv_ctl0 = readl(&ana_pll->audio_pll2_fdiv_ctl0);
  376. pll_fdiv_ctl1 = readl(&ana_pll->audio_pll2_fdiv_ctl1);
  377. break;
  378. case VIDEO_PLL_CLK:
  379. pll_gnrl_ctl = readl(&ana_pll->video_pll1_gnrl_ctl);
  380. pll_fdiv_ctl0 = readl(&ana_pll->video_pll1_fdiv_ctl0);
  381. pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1);
  382. break;
  383. default:
  384. printf("Not supported\n");
  385. return 0;
  386. }
  387. /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */
  388. if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0)
  389. return 0;
  390. if ((pll_gnrl_ctl & RST_MASK) == 0)
  391. return 0;
  392. /*
  393. * When BYPASS is equal to 1, PLL enters the bypass mode
  394. * regardless of the values of RESETB
  395. */
  396. if (pll_gnrl_ctl & BYPASS_MASK)
  397. return 24000000u;
  398. if (!(pll_gnrl_ctl & LOCK_STATUS)) {
  399. puts("pll not locked\n");
  400. return 0;
  401. }
  402. if (!(pll_gnrl_ctl & CLKE_MASK))
  403. return 0;
  404. main_div = (pll_fdiv_ctl0 & MDIV_MASK) >>
  405. MDIV_SHIFT;
  406. pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >>
  407. PDIV_SHIFT;
  408. post_div = (pll_fdiv_ctl0 & SDIV_MASK) >>
  409. SDIV_SHIFT;
  410. k = pll_fdiv_ctl1 & KDIV_MASK;
  411. return lldiv((main_div * 65536 + k) * 24000000ULL,
  412. 65536 * pre_div * (1 << post_div));
  413. }
  414. static u32 get_root_src_clk(enum clk_root_src root_src)
  415. {
  416. switch (root_src) {
  417. case OSC_24M_CLK:
  418. return 24000000u;
  419. case OSC_HDMI_CLK:
  420. return 26000000u;
  421. case OSC_32K_CLK:
  422. return 32000u;
  423. case ARM_PLL_CLK:
  424. case GPU_PLL_CLK:
  425. case VPU_PLL_CLK:
  426. case SYSTEM_PLL1_800M_CLK:
  427. case SYSTEM_PLL1_400M_CLK:
  428. case SYSTEM_PLL1_266M_CLK:
  429. case SYSTEM_PLL1_200M_CLK:
  430. case SYSTEM_PLL1_160M_CLK:
  431. case SYSTEM_PLL1_133M_CLK:
  432. case SYSTEM_PLL1_100M_CLK:
  433. case SYSTEM_PLL1_80M_CLK:
  434. case SYSTEM_PLL1_40M_CLK:
  435. case SYSTEM_PLL2_1000M_CLK:
  436. case SYSTEM_PLL2_500M_CLK:
  437. case SYSTEM_PLL2_333M_CLK:
  438. case SYSTEM_PLL2_250M_CLK:
  439. case SYSTEM_PLL2_200M_CLK:
  440. case SYSTEM_PLL2_166M_CLK:
  441. case SYSTEM_PLL2_125M_CLK:
  442. case SYSTEM_PLL2_100M_CLK:
  443. case SYSTEM_PLL2_50M_CLK:
  444. case SYSTEM_PLL3_CLK:
  445. return decode_intpll(root_src);
  446. case DRAM_PLL1_CLK:
  447. case AUDIO_PLL1_CLK:
  448. case AUDIO_PLL2_CLK:
  449. case VIDEO_PLL_CLK:
  450. return decode_fracpll(root_src);
  451. default:
  452. return 0;
  453. }
  454. return 0;
  455. }
  456. static u32 get_root_clk(enum clk_root_index clock_id)
  457. {
  458. enum clk_root_src root_src;
  459. u32 post_podf, pre_podf, root_src_clk;
  460. if (clock_root_enabled(clock_id) <= 0)
  461. return 0;
  462. if (clock_get_prediv(clock_id, &pre_podf) < 0)
  463. return 0;
  464. if (clock_get_postdiv(clock_id, &post_podf) < 0)
  465. return 0;
  466. if (clock_get_src(clock_id, &root_src) < 0)
  467. return 0;
  468. root_src_clk = get_root_src_clk(root_src);
  469. return root_src_clk / (post_podf + 1) / (pre_podf + 1);
  470. }
  471. u32 mxc_get_clock(enum mxc_clock clk)
  472. {
  473. u32 val;
  474. switch (clk) {
  475. case MXC_ARM_CLK:
  476. return get_root_clk(ARM_A53_CLK_ROOT);
  477. case MXC_IPG_CLK:
  478. clock_get_target_val(IPG_CLK_ROOT, &val);
  479. val = val & 0x3;
  480. return get_root_clk(AHB_CLK_ROOT) / 2 / (val + 1);
  481. case MXC_CSPI_CLK:
  482. return get_root_clk(ECSPI1_CLK_ROOT);
  483. case MXC_ESDHC_CLK:
  484. return get_root_clk(USDHC1_CLK_ROOT);
  485. case MXC_ESDHC2_CLK:
  486. return get_root_clk(USDHC2_CLK_ROOT);
  487. case MXC_ESDHC3_CLK:
  488. return get_root_clk(USDHC3_CLK_ROOT);
  489. case MXC_I2C_CLK:
  490. return get_root_clk(I2C1_CLK_ROOT);
  491. case MXC_UART_CLK:
  492. return get_root_clk(UART1_CLK_ROOT);
  493. case MXC_QSPI_CLK:
  494. return get_root_clk(QSPI_CLK_ROOT);
  495. default:
  496. printf("Unsupported mxc_clock %d\n", clk);
  497. break;
  498. }
  499. return 0;
  500. }
  501. #ifdef CONFIG_FEC_MXC
  502. int set_clk_enet(enum enet_freq type)
  503. {
  504. u32 target;
  505. u32 enet1_ref;
  506. switch (type) {
  507. case ENET_125MHZ:
  508. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
  509. break;
  510. case ENET_50MHZ:
  511. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
  512. break;
  513. case ENET_25MHZ:
  514. enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
  515. break;
  516. default:
  517. return -EINVAL;
  518. }
  519. /* disable the clock first */
  520. clock_enable(CCGR_ENET1, 0);
  521. clock_enable(CCGR_SIM_ENET, 0);
  522. /* set enet axi clock 266Mhz */
  523. target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
  524. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  525. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  526. clock_set_target_val(ENET_AXI_CLK_ROOT, target);
  527. target = CLK_ROOT_ON | enet1_ref |
  528. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  529. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
  530. clock_set_target_val(ENET_REF_CLK_ROOT, target);
  531. target = CLK_ROOT_ON |
  532. ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
  533. CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
  534. CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
  535. clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
  536. /* enable clock */
  537. clock_enable(CCGR_SIM_ENET, 1);
  538. clock_enable(CCGR_ENET1, 1);
  539. return 0;
  540. }
  541. #endif