timer.c 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2003
  4. * Texas Instruments <www.ti.com>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Marius Groeger <mgroeger@sysgo.de>
  9. *
  10. * (C) Copyright 2002
  11. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  12. * Alex Zuepke <azu@sysgo.de>
  13. *
  14. * (C) Copyright 2002-2004
  15. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  16. *
  17. * (C) Copyright 2004
  18. * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
  19. *
  20. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  21. */
  22. #include <common.h>
  23. #include <init.h>
  24. #include <time.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/timer_defs.h>
  27. #include <div64.h>
  28. #include <linux/delay.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. static struct davinci_timer * const timer =
  31. (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
  32. #define TIMER_LOAD_VAL 0xffffffff
  33. #define TIM_CLK_DIV 16
  34. int timer_init(void)
  35. {
  36. /* We are using timer34 in unchained 32-bit mode, full speed */
  37. writel(0x0, &timer->tcr);
  38. writel(0x0, &timer->tgcr);
  39. writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
  40. writel(0x0, &timer->tim34);
  41. writel(TIMER_LOAD_VAL, &timer->prd34);
  42. writel(2 << 22, &timer->tcr);
  43. gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
  44. gd->arch.timer_reset_value = 0;
  45. return(0);
  46. }
  47. /*
  48. * Get the current 64 bit timer tick count
  49. */
  50. unsigned long long get_ticks(void)
  51. {
  52. unsigned long now = readl(&timer->tim34);
  53. /* increment tbu if tbl has rolled over */
  54. if (now < gd->arch.tbl)
  55. gd->arch.tbu++;
  56. gd->arch.tbl = now;
  57. return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
  58. }
  59. ulong get_timer(ulong base)
  60. {
  61. unsigned long long timer_diff;
  62. timer_diff = get_ticks() - gd->arch.timer_reset_value;
  63. return lldiv(timer_diff,
  64. (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
  65. }
  66. void __udelay(unsigned long usec)
  67. {
  68. unsigned long long endtime;
  69. endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
  70. 1000000UL);
  71. endtime += get_ticks();
  72. while (get_ticks() < endtime)
  73. ;
  74. }
  75. /*
  76. * This function is derived from PowerPC code (timebase clock frequency).
  77. * On ARM it returns the number of timer ticks per second.
  78. */
  79. ulong get_tbclk(void)
  80. {
  81. return gd->arch.timer_rate_hz;
  82. }
  83. #ifdef CONFIG_HW_WATCHDOG
  84. static struct davinci_timer * const wdttimer =
  85. (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
  86. /*
  87. * See prufw2.pdf for using Timer as a WDT
  88. */
  89. void davinci_hw_watchdog_enable(void)
  90. {
  91. writel(0x0, &wdttimer->tcr);
  92. writel(0x0, &wdttimer->tgcr);
  93. /* TIMMODE = 2h */
  94. writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
  95. writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
  96. writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
  97. writel(2 << 22, &wdttimer->tcr);
  98. writel(0x0, &wdttimer->tim12);
  99. writel(0x0, &wdttimer->tim34);
  100. /* set WDEN bit, WDKEY 0xa5c6 */
  101. writel(0xa5c64000, &wdttimer->wdtcr);
  102. /* clear counter register */
  103. writel(0xda7e4000, &wdttimer->wdtcr);
  104. }
  105. void davinci_hw_watchdog_reset(void)
  106. {
  107. writel(0xa5c64000, &wdttimer->wdtcr);
  108. writel(0xda7e4000, &wdttimer->wdtcr);
  109. }
  110. #endif