timer.c 2.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Lineo, Inc. <www.lineo.com>
  5. * Bernhard Kuhn <bkuhn@lineo.com>
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. *
  11. * (C) Copyright 2002
  12. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13. * Alex Zuepke <azu@sysgo.de>
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <time.h>
  18. #include <linux/delay.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/at91_tc.h>
  22. #include <asm/arch/clk.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /* the number of clocks per CONFIG_SYS_HZ */
  25. #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
  26. int timer_init(void)
  27. {
  28. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  29. at91_periph_clk_enable(ATMEL_ID_TC0);
  30. writel(0, &tc->bcr);
  31. writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
  32. AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
  33. writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
  34. /* set to MCLK/2 and restart the timer
  35. when the value in TC_RC is reached */
  36. writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
  37. writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
  38. writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
  39. writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
  40. gd->arch.lastinc = 0;
  41. gd->arch.tbl = 0;
  42. return 0;
  43. }
  44. /*
  45. * timer without interrupts
  46. */
  47. ulong get_timer_raw(void)
  48. {
  49. at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
  50. u32 now;
  51. now = readl(&tc->tc[0].cv) & 0x0000ffff;
  52. if (now >= gd->arch.lastinc) {
  53. /* normal mode */
  54. gd->arch.tbl += now - gd->arch.lastinc;
  55. } else {
  56. /* we have an overflow ... */
  57. gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
  58. }
  59. gd->arch.lastinc = now;
  60. return gd->arch.tbl;
  61. }
  62. static ulong get_timer_masked(void)
  63. {
  64. return get_timer_raw()/TIMER_LOAD_VAL;
  65. }
  66. ulong get_timer(ulong base)
  67. {
  68. return get_timer_masked() - base;
  69. }
  70. void __udelay(unsigned long usec)
  71. {
  72. u32 tmo;
  73. u32 endtime;
  74. signed long diff;
  75. tmo = CONFIG_SYS_HZ_CLOCK / 1000;
  76. tmo *= usec;
  77. tmo /= 1000;
  78. endtime = get_timer_raw() + tmo;
  79. do {
  80. u32 now = get_timer_raw();
  81. diff = endtime - now;
  82. } while (diff >= 0);
  83. }
  84. /*
  85. * This function is derived from PowerPC code (read timebase as long long).
  86. * On ARM it just returns the timer value.
  87. */
  88. unsigned long long get_ticks(void)
  89. {
  90. return get_timer(0);
  91. }
  92. /*
  93. * This function is derived from PowerPC code (timebase clock frequency).
  94. * On ARM it returns the number of timer ticks per second.
  95. */
  96. ulong get_tbclk(void)
  97. {
  98. return CONFIG_SYS_HZ;
  99. }