mp.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <image.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <asm/system.h>
  11. #include <asm/arch/mp.h>
  12. #include <asm/arch/soc.h>
  13. #include <linux/delay.h>
  14. #include "cpu.h"
  15. #include <asm/arch-fsl-layerscape/soc.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. void *get_spin_tbl_addr(void)
  18. {
  19. return &__spin_table;
  20. }
  21. phys_addr_t determine_mp_bootpg(void)
  22. {
  23. return (phys_addr_t)&secondary_boot_code;
  24. }
  25. void update_os_arch_secondary_cores(uint8_t os_arch)
  26. {
  27. u64 *table = get_spin_tbl_addr();
  28. int i;
  29. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  30. if (os_arch == IH_ARCH_DEFAULT)
  31. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  32. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
  33. else
  34. table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  35. SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
  36. }
  37. }
  38. #ifdef CONFIG_FSL_LSCH3
  39. void wake_secondary_core_n(int cluster, int core, int cluster_cores)
  40. {
  41. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  42. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  43. u32 mpidr = 0;
  44. mpidr = ((cluster << 8) | core);
  45. /*
  46. * mpidr_el1 register value of core which needs to be released
  47. * is written to scratchrw[6] register
  48. */
  49. gur_out32(&gur->scratchrw[6], mpidr);
  50. asm volatile("dsb st" : : : "memory");
  51. rst->brrl |= 1 << ((cluster * cluster_cores) + core);
  52. asm volatile("dsb st" : : : "memory");
  53. /*
  54. * scratchrw[6] register value is polled
  55. * when the value becomes zero, this means that this core is up
  56. * and running, next core can be released now
  57. */
  58. while (gur_in32(&gur->scratchrw[6]) != 0)
  59. ;
  60. }
  61. #endif
  62. int fsl_layerscape_wake_seconday_cores(void)
  63. {
  64. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  65. #ifdef CONFIG_FSL_LSCH3
  66. struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
  67. u32 svr, ver, cluster, type;
  68. int j = 0, cluster_cores = 0;
  69. #elif defined(CONFIG_FSL_LSCH2)
  70. struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
  71. #endif
  72. u32 cores, cpu_up_mask = 1;
  73. int i, timeout = 10;
  74. u64 *table = get_spin_tbl_addr();
  75. #ifdef COUNTER_FREQUENCY_REAL
  76. /* update for secondary cores */
  77. __real_cntfrq = COUNTER_FREQUENCY_REAL;
  78. flush_dcache_range((unsigned long)&__real_cntfrq,
  79. (unsigned long)&__real_cntfrq + 8);
  80. #endif
  81. cores = cpu_mask();
  82. /* Clear spin table so that secondary processors
  83. * observe the correct value after waking up from wfe.
  84. */
  85. memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
  86. flush_dcache_range((unsigned long)table,
  87. (unsigned long)table +
  88. (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
  89. printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
  90. #ifdef CONFIG_FSL_LSCH3
  91. gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
  92. gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
  93. svr = gur_in32(&gur->svr);
  94. ver = SVR_SOC_VER(svr);
  95. if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
  96. gur_out32(&gur->scratchrw[6], 1);
  97. asm volatile("dsb st" : : : "memory");
  98. rst->brrl = cores;
  99. asm volatile("dsb st" : : : "memory");
  100. } else {
  101. /*
  102. * Release the cores out of reset one-at-a-time to avoid
  103. * power spikes
  104. */
  105. i = 0;
  106. cluster = in_le32(&gur->tp_cluster[i].lower);
  107. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  108. type = initiator_type(cluster, j);
  109. if (type &&
  110. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  111. cluster_cores++;
  112. }
  113. do {
  114. cluster = in_le32(&gur->tp_cluster[i].lower);
  115. for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
  116. type = initiator_type(cluster, j);
  117. if (type &&
  118. TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
  119. wake_secondary_core_n(i, j,
  120. cluster_cores);
  121. }
  122. i++;
  123. } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
  124. }
  125. #elif defined(CONFIG_FSL_LSCH2)
  126. scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
  127. scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
  128. asm volatile("dsb st" : : : "memory");
  129. gur_out32(&gur->brrl, cores);
  130. asm volatile("dsb st" : : : "memory");
  131. /* Bootup online cores */
  132. scfg_out32(&scfg->corebcr, cores);
  133. #endif
  134. /* This is needed as a precautionary measure.
  135. * If some code before this has accidentally released the secondary
  136. * cores then the pre-bootloader code will trap them in a "wfe" unless
  137. * the scratchrw[6] is set. In this case we need a sev here to get these
  138. * cores moving again.
  139. */
  140. asm volatile("sev");
  141. while (timeout--) {
  142. flush_dcache_range((unsigned long)table, (unsigned long)table +
  143. CONFIG_MAX_CPUS * 64);
  144. for (i = 1; i < CONFIG_MAX_CPUS; i++) {
  145. if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
  146. SPIN_TABLE_ELEM_STATUS_IDX])
  147. cpu_up_mask |= 1 << i;
  148. }
  149. if (hweight32(cpu_up_mask) == hweight32(cores))
  150. break;
  151. udelay(10);
  152. }
  153. if (timeout <= 0) {
  154. printf("Not all cores (0x%x) are up (0x%x)\n",
  155. cores, cpu_up_mask);
  156. return 1;
  157. }
  158. printf("All (%d) cores are up.\n", hweight32(cores));
  159. return 0;
  160. }
  161. int is_core_valid(unsigned int core)
  162. {
  163. return !!((1 << core) & cpu_mask());
  164. }
  165. static int is_pos_valid(unsigned int pos)
  166. {
  167. return !!((1 << pos) & cpu_pos_mask());
  168. }
  169. int is_core_online(u64 cpu_id)
  170. {
  171. u64 *table;
  172. int pos = id_to_core(cpu_id);
  173. table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
  174. return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
  175. }
  176. int cpu_reset(u32 nr)
  177. {
  178. puts("Feature is not implemented.\n");
  179. return 0;
  180. }
  181. int cpu_disable(u32 nr)
  182. {
  183. puts("Feature is not implemented.\n");
  184. return 0;
  185. }
  186. static int core_to_pos(int nr)
  187. {
  188. u32 cores = cpu_pos_mask();
  189. int i, count = 0;
  190. if (nr == 0) {
  191. return 0;
  192. } else if (nr >= hweight32(cores)) {
  193. puts("Not a valid core number.\n");
  194. return -1;
  195. }
  196. for (i = 1; i < 32; i++) {
  197. if (is_pos_valid(i)) {
  198. count++;
  199. if (count == nr)
  200. break;
  201. }
  202. }
  203. if (count != nr)
  204. return -1;
  205. return i;
  206. }
  207. int cpu_status(u32 nr)
  208. {
  209. u64 *table;
  210. int pos;
  211. if (nr == 0) {
  212. table = (u64 *)get_spin_tbl_addr();
  213. printf("table base @ 0x%p\n", table);
  214. } else {
  215. pos = core_to_pos(nr);
  216. if (pos < 0)
  217. return -1;
  218. table = (u64 *)get_spin_tbl_addr() + pos *
  219. WORDS_PER_SPIN_TABLE_ENTRY;
  220. printf("table @ 0x%p\n", table);
  221. printf(" addr - 0x%016llx\n",
  222. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
  223. printf(" status - 0x%016llx\n",
  224. table[SPIN_TABLE_ELEM_STATUS_IDX]);
  225. printf(" lpid - 0x%016llx\n",
  226. table[SPIN_TABLE_ELEM_LPID_IDX]);
  227. }
  228. return 0;
  229. }
  230. int cpu_release(u32 nr, int argc, char *const argv[])
  231. {
  232. u64 boot_addr;
  233. u64 *table = (u64 *)get_spin_tbl_addr();
  234. int pos;
  235. pos = core_to_pos(nr);
  236. if (pos <= 0)
  237. return -1;
  238. table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
  239. boot_addr = simple_strtoull(argv[0], NULL, 16);
  240. table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
  241. flush_dcache_range((unsigned long)table,
  242. (unsigned long)table + SPIN_TABLE_ELEM_SIZE);
  243. asm volatile("dsb st");
  244. smp_kick_all_cpus(); /* only those with entry addr set will run */
  245. /*
  246. * When the first release command runs, all cores are set to go. Those
  247. * without a valid entry address will be trapped by "wfe". "sev" kicks
  248. * them off to check the address again. When set, they continue to run.
  249. */
  250. asm volatile("sev");
  251. return 0;
  252. }