fsl_lsch2_serdes.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <linux/delay.h>
  9. #include <linux/errno.h>
  10. #include <asm/arch/fsl_serdes.h>
  11. #include <asm/arch/soc.h>
  12. #ifdef CONFIG_SYS_FSL_SRDS_1
  13. static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  14. #endif
  15. #ifdef CONFIG_SYS_FSL_SRDS_2
  16. static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  17. #endif
  18. int is_serdes_configured(enum srds_prtcl device)
  19. {
  20. int ret = 0;
  21. #ifdef CONFIG_SYS_FSL_SRDS_1
  22. if (!serdes1_prtcl_map[NONE])
  23. fsl_serdes_init();
  24. ret |= serdes1_prtcl_map[device];
  25. #endif
  26. #ifdef CONFIG_SYS_FSL_SRDS_2
  27. if (!serdes2_prtcl_map[NONE])
  28. fsl_serdes_init();
  29. ret |= serdes2_prtcl_map[device];
  30. #endif
  31. return !!ret;
  32. }
  33. int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  34. {
  35. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  36. u32 cfg = gur_in32(&gur->rcwsr[4]);
  37. int i;
  38. switch (sd) {
  39. #ifdef CONFIG_SYS_FSL_SRDS_1
  40. case FSL_SRDS_1:
  41. cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  42. cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  43. break;
  44. #endif
  45. #ifdef CONFIG_SYS_FSL_SRDS_2
  46. case FSL_SRDS_2:
  47. cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  48. cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  49. break;
  50. #endif
  51. default:
  52. printf("invalid SerDes%d\n", sd);
  53. break;
  54. }
  55. /* Is serdes enabled at all? */
  56. if (unlikely(cfg == 0))
  57. return -ENODEV;
  58. for (i = 0; i < SRDS_MAX_LANES; i++) {
  59. if (serdes_get_prtcl(sd, cfg, i) == device)
  60. return i;
  61. }
  62. return -ENODEV;
  63. }
  64. int get_serdes_protocol(void)
  65. {
  66. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  67. u32 cfg = gur_in32(&gur->rcwsr[4]) &
  68. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  69. cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  70. return cfg;
  71. }
  72. const char *serdes_clock_to_string(u32 clock)
  73. {
  74. switch (clock) {
  75. case SRDS_PLLCR0_RFCK_SEL_100:
  76. return "100";
  77. case SRDS_PLLCR0_RFCK_SEL_125:
  78. return "125";
  79. case SRDS_PLLCR0_RFCK_SEL_156_25:
  80. return "156.25";
  81. default:
  82. return "100";
  83. }
  84. }
  85. void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
  86. u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  87. {
  88. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  89. u32 cfg;
  90. int lane;
  91. if (serdes_prtcl_map[NONE])
  92. return;
  93. memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
  94. cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
  95. cfg >>= sd_prctl_shift;
  96. printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  97. if (!is_serdes_prtcl_valid(sd, cfg))
  98. printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  99. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  100. enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  101. if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  102. debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  103. else
  104. serdes_prtcl_map[lane_prtcl] = 1;
  105. }
  106. /* Set the first element to indicate serdes has been initialized */
  107. serdes_prtcl_map[NONE] = 1;
  108. }
  109. __weak int get_serdes_volt(void)
  110. {
  111. return -1;
  112. }
  113. __weak int set_serdes_volt(int svdd)
  114. {
  115. return -1;
  116. }
  117. int setup_serdes_volt(u32 svdd)
  118. {
  119. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  120. struct ccsr_serdes *serdes1_base;
  121. #ifdef CONFIG_SYS_FSL_SRDS_2
  122. struct ccsr_serdes *serdes2_base;
  123. #endif
  124. u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]);
  125. u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]);
  126. u32 cfg_tmp, reg = 0;
  127. int svdd_cur, svdd_tar;
  128. int ret;
  129. int i;
  130. /* Only support switch SVDD to 900mV/1000mV */
  131. if (svdd != 900 && svdd != 1000)
  132. return -EINVAL;
  133. svdd_tar = svdd;
  134. svdd_cur = get_serdes_volt();
  135. if (svdd_cur < 0)
  136. return -EINVAL;
  137. debug("%s: current SVDD: %dmV; target SVDD: %dmV\n",
  138. __func__, svdd_cur, svdd_tar);
  139. if (svdd_cur == svdd_tar)
  140. return 0;
  141. serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
  142. #ifdef CONFIG_SYS_FSL_SRDS_2
  143. serdes2_base = (void *)serdes1_base + 0x10000;
  144. #endif
  145. /* Put the all enabled lanes in reset */
  146. #ifdef CONFIG_SYS_FSL_SRDS_1
  147. cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  148. cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  149. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  150. reg = in_be32(&serdes1_base->lane[i].gcr0);
  151. reg &= 0xFF9FFFFF;
  152. out_be32(&serdes1_base->lane[i].gcr0, reg);
  153. }
  154. #endif
  155. #ifdef CONFIG_SYS_FSL_SRDS_2
  156. cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  157. cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  158. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  159. reg = in_be32(&serdes2_base->lane[i].gcr0);
  160. reg &= 0xFF9FFFFF;
  161. out_be32(&serdes2_base->lane[i].gcr0, reg);
  162. }
  163. #endif
  164. /* Put the all enabled PLL in reset */
  165. #ifdef CONFIG_SYS_FSL_SRDS_1
  166. cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
  167. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  168. reg = in_be32(&serdes1_base->bank[i].rstctl);
  169. reg &= 0xFFFFFFBF;
  170. reg |= 0x10000000;
  171. out_be32(&serdes1_base->bank[i].rstctl, reg);
  172. udelay(1);
  173. reg = in_be32(&serdes1_base->bank[i].rstctl);
  174. reg &= 0xFFFFFF1F;
  175. out_be32(&serdes1_base->bank[i].rstctl, reg);
  176. }
  177. udelay(1);
  178. #endif
  179. #ifdef CONFIG_SYS_FSL_SRDS_2
  180. cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
  181. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  182. reg = in_be32(&serdes2_base->bank[i].rstctl);
  183. reg &= 0xFFFFFFBF;
  184. reg |= 0x10000000;
  185. out_be32(&serdes2_base->bank[i].rstctl, reg);
  186. udelay(1);
  187. reg = in_be32(&serdes2_base->bank[i].rstctl);
  188. reg &= 0xFFFFFF1F;
  189. out_be32(&serdes2_base->bank[i].rstctl, reg);
  190. }
  191. udelay(1);
  192. #endif
  193. /* Put the Rx/Tx calibration into reset */
  194. #ifdef CONFIG_SYS_FSL_SRDS_1
  195. reg = in_be32(&serdes1_base->srdstcalcr);
  196. reg &= 0xF7FFFFFF;
  197. out_be32(&serdes1_base->srdstcalcr, reg);
  198. reg = in_be32(&serdes1_base->srdsrcalcr);
  199. reg &= 0xF7FFFFFF;
  200. out_be32(&serdes1_base->srdsrcalcr, reg);
  201. #endif
  202. #ifdef CONFIG_SYS_FSL_SRDS_2
  203. reg = in_be32(&serdes2_base->srdstcalcr);
  204. reg &= 0xF7FFFFFF;
  205. out_be32(&serdes2_base->srdstcalcr, reg);
  206. reg = in_be32(&serdes2_base->srdsrcalcr);
  207. reg &= 0xF7FFFFFF;
  208. out_be32(&serdes2_base->srdsrcalcr, reg);
  209. #endif
  210. /*
  211. * If SVDD set failed, will not return directly, so that the
  212. * serdes lanes can complete reseting.
  213. */
  214. ret = set_serdes_volt(svdd_tar);
  215. if (ret)
  216. printf("%s: Failed to set SVDD\n", __func__);
  217. /* Wait for SVDD to stabilize */
  218. udelay(100);
  219. /* For each PLL that’s not disabled via RCW */
  220. #ifdef CONFIG_SYS_FSL_SRDS_1
  221. cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
  222. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  223. reg = in_be32(&serdes1_base->bank[i].rstctl);
  224. reg |= 0x00000020;
  225. out_be32(&serdes1_base->bank[i].rstctl, reg);
  226. udelay(1);
  227. reg = in_be32(&serdes1_base->bank[i].rstctl);
  228. reg |= 0x00000080;
  229. out_be32(&serdes1_base->bank[i].rstctl, reg);
  230. /* Take the Rx/Tx calibration out of reset */
  231. if (!(cfg_tmp == 0x3 && i == 1)) {
  232. udelay(1);
  233. reg = in_be32(&serdes1_base->srdstcalcr);
  234. reg |= 0x08000000;
  235. out_be32(&serdes1_base->srdstcalcr, reg);
  236. reg = in_be32(&serdes1_base->srdsrcalcr);
  237. reg |= 0x08000000;
  238. out_be32(&serdes1_base->srdsrcalcr, reg);
  239. }
  240. }
  241. udelay(1);
  242. #endif
  243. #ifdef CONFIG_SYS_FSL_SRDS_2
  244. cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
  245. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  246. reg = in_be32(&serdes2_base->bank[i].rstctl);
  247. reg |= 0x00000020;
  248. out_be32(&serdes2_base->bank[i].rstctl, reg);
  249. udelay(1);
  250. reg = in_be32(&serdes2_base->bank[i].rstctl);
  251. reg |= 0x00000080;
  252. out_be32(&serdes2_base->bank[i].rstctl, reg);
  253. /* Take the Rx/Tx calibration out of reset */
  254. if (!(cfg_tmp == 0x3 && i == 1)) {
  255. udelay(1);
  256. reg = in_be32(&serdes2_base->srdstcalcr);
  257. reg |= 0x08000000;
  258. out_be32(&serdes2_base->srdstcalcr, reg);
  259. reg = in_be32(&serdes2_base->srdsrcalcr);
  260. reg |= 0x08000000;
  261. out_be32(&serdes2_base->srdsrcalcr, reg);
  262. }
  263. }
  264. udelay(1);
  265. #endif
  266. /* Wait for at lesat 625us to ensure the PLLs being reset are locked */
  267. udelay(800);
  268. #ifdef CONFIG_SYS_FSL_SRDS_1
  269. cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
  270. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  271. /* if the PLL is not locked, set RST_ERR */
  272. reg = in_be32(&serdes1_base->bank[i].pllcr0);
  273. if (!((reg >> 23) & 0x1)) {
  274. reg = in_be32(&serdes1_base->bank[i].rstctl);
  275. reg |= 0x20000000;
  276. out_be32(&serdes1_base->bank[i].rstctl, reg);
  277. } else {
  278. udelay(1);
  279. reg = in_be32(&serdes1_base->bank[i].rstctl);
  280. reg &= 0xFFFFFFEF;
  281. reg |= 0x00000040;
  282. out_be32(&serdes1_base->bank[i].rstctl, reg);
  283. udelay(1);
  284. }
  285. }
  286. #endif
  287. #ifdef CONFIG_SYS_FSL_SRDS_2
  288. cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
  289. for (i = 0; i < 2 && !(cfg_tmp & (0x1 << (1 - i))); i++) {
  290. reg = in_be32(&serdes2_base->bank[i].pllcr0);
  291. if (!((reg >> 23) & 0x1)) {
  292. reg = in_be32(&serdes2_base->bank[i].rstctl);
  293. reg |= 0x20000000;
  294. out_be32(&serdes2_base->bank[i].rstctl, reg);
  295. } else {
  296. udelay(1);
  297. reg = in_be32(&serdes2_base->bank[i].rstctl);
  298. reg &= 0xFFFFFFEF;
  299. reg |= 0x00000040;
  300. out_be32(&serdes2_base->bank[i].rstctl, reg);
  301. udelay(1);
  302. }
  303. }
  304. #endif
  305. /* Take the all enabled lanes out of reset */
  306. #ifdef CONFIG_SYS_FSL_SRDS_1
  307. cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  308. cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  309. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  310. reg = in_be32(&serdes1_base->lane[i].gcr0);
  311. reg |= 0x00600000;
  312. out_be32(&serdes1_base->lane[i].gcr0, reg);
  313. }
  314. #endif
  315. #ifdef CONFIG_SYS_FSL_SRDS_2
  316. cfg_tmp = cfg_rcw4 & FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  317. cfg_tmp >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  318. for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
  319. reg = in_be32(&serdes2_base->lane[i].gcr0);
  320. reg |= 0x00600000;
  321. out_be32(&serdes2_base->lane[i].gcr0, reg);
  322. }
  323. #endif
  324. /* For each PLL being reset, and achieved PLL lock set RST_DONE */
  325. #ifdef CONFIG_SYS_FSL_SRDS_1
  326. cfg_tmp = (cfg_rcw5 >> 22) & 0x3;
  327. for (i = 0; i < 2; i++) {
  328. reg = in_be32(&serdes1_base->bank[i].pllcr0);
  329. if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  330. reg = in_be32(&serdes1_base->bank[i].rstctl);
  331. reg |= 0x40000000;
  332. out_be32(&serdes1_base->bank[i].rstctl, reg);
  333. }
  334. }
  335. #endif
  336. #ifdef CONFIG_SYS_FSL_SRDS_2
  337. cfg_tmp = (cfg_rcw5 >> 20) & 0x3;
  338. for (i = 0; i < 2; i++) {
  339. reg = in_be32(&serdes2_base->bank[i].pllcr0);
  340. if (!(cfg_tmp & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
  341. reg = in_be32(&serdes2_base->bank[i].rstctl);
  342. reg |= 0x40000000;
  343. out_be32(&serdes2_base->bank[i].rstctl, reg);
  344. }
  345. }
  346. #endif
  347. return ret;
  348. }
  349. void fsl_serdes_init(void)
  350. {
  351. #ifdef CONFIG_SYS_FSL_SRDS_1
  352. serdes_init(FSL_SRDS_1,
  353. CONFIG_SYS_FSL_SERDES_ADDR,
  354. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
  355. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
  356. serdes1_prtcl_map);
  357. #endif
  358. #ifdef CONFIG_SYS_FSL_SRDS_2
  359. serdes_init(FSL_SRDS_2,
  360. CONFIG_SYS_FSL_SERDES_ADDR,
  361. FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
  362. FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
  363. serdes2_prtcl_map);
  364. #endif
  365. }