clk-core.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Broadcom Corporation.
  4. */
  5. /*
  6. *
  7. * bcm281xx architecture clock framework
  8. *
  9. */
  10. #include <common.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <bitfield.h>
  16. #include <asm/arch/sysmap.h>
  17. #include <asm/kona-common/clk.h>
  18. #include "clk-core.h"
  19. #define CLK_WR_ACCESS_PASSWORD 0x00a5a501
  20. #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
  21. #define POLICY_CTL_GO 1 /* Load and refresh policy masks */
  22. #define POLICY_CTL_GO_ATL 4 /* Active Load */
  23. /* Helper function */
  24. int clk_get_and_enable(char *clkstr)
  25. {
  26. int ret = 0;
  27. struct clk *c;
  28. debug("%s: %s\n", __func__, clkstr);
  29. c = clk_get(clkstr);
  30. if (c) {
  31. ret = clk_enable(c);
  32. if (ret)
  33. return ret;
  34. } else {
  35. printf("%s: Couldn't find %s\n", __func__, clkstr);
  36. return -EINVAL;
  37. }
  38. return ret;
  39. }
  40. /*
  41. * Poll a register in a CCU's address space, returning when the
  42. * specified bit in that register's value is set (or clear). Delay
  43. * a microsecond after each read of the register. Returns true if
  44. * successful, or false if we gave up trying.
  45. *
  46. * Caller must ensure the CCU lock is held.
  47. */
  48. #define CLK_GATE_DELAY_USEC 2000
  49. static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
  50. {
  51. unsigned int tries;
  52. u32 bit_mask = 1 << bit;
  53. for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
  54. u32 val;
  55. bool bit_val;
  56. val = readl(base + offset);
  57. bit_val = (val & bit_mask) ? 1 : 0;
  58. if (bit_val == want)
  59. return 0; /* success */
  60. udelay(1);
  61. }
  62. debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
  63. __func__, base + offset, bit, want);
  64. return -ETIMEDOUT;
  65. }
  66. /* Enable a peripheral clock */
  67. static int peri_clk_enable(struct clk *c, int enable)
  68. {
  69. int ret = 0;
  70. u32 reg;
  71. struct peri_clock *peri_clk = to_peri_clk(c);
  72. struct peri_clk_data *cd = peri_clk->data;
  73. struct bcm_clk_gate *gate = &cd->gate;
  74. void *base = (void *)c->ccu_clk_mgr_base;
  75. debug("%s: %s\n", __func__, c->name);
  76. clk_get_rate(c); /* Make sure rate and sel are filled in */
  77. /* enable access */
  78. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  79. if (enable) {
  80. debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
  81. __func__, c->name, c->rate, c->div, c->sel,
  82. c->parent->rate);
  83. /*
  84. * clkgate - only software controllable gates are
  85. * supported by u-boot which includes all clocks
  86. * that matter. This avoids bringing in a lot of extra
  87. * complexity as done in the kernel framework.
  88. */
  89. if (gate_exists(gate)) {
  90. reg = readl(base + cd->gate.offset);
  91. reg |= (1 << cd->gate.en_bit);
  92. writel(reg, base + cd->gate.offset);
  93. }
  94. /* div and pll select */
  95. if (divider_exists(&cd->div)) {
  96. reg = readl(base + cd->div.offset);
  97. bitfield_replace(reg, cd->div.shift, cd->div.width,
  98. c->div - 1);
  99. writel(reg, base + cd->div.offset);
  100. }
  101. /* frequency selector */
  102. if (selector_exists(&cd->sel)) {
  103. reg = readl(base + cd->sel.offset);
  104. bitfield_replace(reg, cd->sel.shift, cd->sel.width,
  105. c->sel);
  106. writel(reg, base + cd->sel.offset);
  107. }
  108. /* trigger */
  109. if (trigger_exists(&cd->trig)) {
  110. writel((1 << cd->trig.bit), base + cd->trig.offset);
  111. /* wait for trigger status bit to go to 0 */
  112. ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
  113. if (ret)
  114. return ret;
  115. }
  116. /* wait for running (status_bit = 1) */
  117. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
  118. if (ret)
  119. return ret;
  120. } else {
  121. debug("%s disable clock %s\n", __func__, c->name);
  122. /* clkgate */
  123. reg = readl(base + cd->gate.offset);
  124. reg &= ~(1 << cd->gate.en_bit);
  125. writel(reg, base + cd->gate.offset);
  126. /* wait for stop (status_bit = 0) */
  127. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
  128. }
  129. /* disable access */
  130. writel(0, base + WR_ACCESS_OFFSET);
  131. return ret;
  132. }
  133. /* Set the rate of a peripheral clock */
  134. static int peri_clk_set_rate(struct clk *c, unsigned long rate)
  135. {
  136. int ret = 0;
  137. int i;
  138. unsigned long diff;
  139. unsigned long new_rate = 0, div = 1;
  140. struct peri_clock *peri_clk = to_peri_clk(c);
  141. struct peri_clk_data *cd = peri_clk->data;
  142. const char **clock;
  143. debug("%s: %s\n", __func__, c->name);
  144. diff = rate;
  145. i = 0;
  146. for (clock = cd->clocks; *clock; clock++, i++) {
  147. struct refclk *ref = refclk_str_to_clk(*clock);
  148. if (!ref) {
  149. printf("%s: Lookup of %s failed\n", __func__, *clock);
  150. return -EINVAL;
  151. }
  152. /* round to the new rate */
  153. div = ref->clk.rate / rate;
  154. if (div == 0)
  155. div = 1;
  156. new_rate = ref->clk.rate / div;
  157. /* get the min diff */
  158. if (abs(new_rate - rate) < diff) {
  159. diff = abs(new_rate - rate);
  160. c->sel = i;
  161. c->parent = &ref->clk;
  162. c->rate = new_rate;
  163. c->div = div;
  164. }
  165. }
  166. debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
  167. c->name, c->rate, c->div, c->sel, c->parent->rate);
  168. return ret;
  169. }
  170. /* Get the rate of a peripheral clock */
  171. static unsigned long peri_clk_get_rate(struct clk *c)
  172. {
  173. struct peri_clock *peri_clk = to_peri_clk(c);
  174. struct peri_clk_data *cd = peri_clk->data;
  175. void *base = (void *)c->ccu_clk_mgr_base;
  176. int div = 1;
  177. const char **clock;
  178. struct refclk *ref;
  179. u32 reg;
  180. debug("%s: %s\n", __func__, c->name);
  181. if (selector_exists(&cd->sel)) {
  182. reg = readl(base + cd->sel.offset);
  183. c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
  184. } else {
  185. /*
  186. * For peri clocks that don't have a selector, the single
  187. * reference clock will always exist at index 0.
  188. */
  189. c->sel = 0;
  190. }
  191. if (divider_exists(&cd->div)) {
  192. reg = readl(base + cd->div.offset);
  193. div = bitfield_extract(reg, cd->div.shift, cd->div.width);
  194. div += 1;
  195. }
  196. clock = cd->clocks;
  197. ref = refclk_str_to_clk(clock[c->sel]);
  198. if (!ref) {
  199. printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
  200. return 0;
  201. }
  202. c->parent = &ref->clk;
  203. c->div = div;
  204. c->rate = c->parent->rate / c->div;
  205. debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
  206. c->parent->rate, div, c->sel, c->rate);
  207. return c->rate;
  208. }
  209. /* Peripheral clock operations */
  210. struct clk_ops peri_clk_ops = {
  211. .enable = peri_clk_enable,
  212. .set_rate = peri_clk_set_rate,
  213. .get_rate = peri_clk_get_rate,
  214. };
  215. /* Enable a CCU clock */
  216. static int ccu_clk_enable(struct clk *c, int enable)
  217. {
  218. struct ccu_clock *ccu_clk = to_ccu_clk(c);
  219. void *base = (void *)c->ccu_clk_mgr_base;
  220. int ret = 0;
  221. u32 reg;
  222. debug("%s: %s\n", __func__, c->name);
  223. if (!enable)
  224. return -EINVAL; /* CCU clock cannot shutdown */
  225. /* enable access */
  226. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  227. /* config enable for policy engine */
  228. writel(1, base + ccu_clk->lvm_en_offset);
  229. /* wait for bit to go to 0 */
  230. ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
  231. if (ret)
  232. return ret;
  233. /* freq ID */
  234. if (!ccu_clk->freq_bit_shift)
  235. ccu_clk->freq_bit_shift = 8;
  236. /* Set frequency id for each of the 4 policies */
  237. reg = ccu_clk->freq_id |
  238. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
  239. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
  240. (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
  241. writel(reg, base + ccu_clk->policy_freq_offset);
  242. /* enable all clock mask */
  243. writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
  244. writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
  245. writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
  246. writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
  247. if (ccu_clk->num_policy_masks == 2) {
  248. writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
  249. writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
  250. writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
  251. writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
  252. }
  253. /* start policy engine */
  254. reg = readl(base + ccu_clk->policy_ctl_offset);
  255. reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
  256. writel(reg, base + ccu_clk->policy_ctl_offset);
  257. /* wait till started */
  258. ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
  259. if (ret)
  260. return ret;
  261. /* disable access */
  262. writel(0, base + WR_ACCESS_OFFSET);
  263. return ret;
  264. }
  265. /* Get the CCU clock rate */
  266. static unsigned long ccu_clk_get_rate(struct clk *c)
  267. {
  268. struct ccu_clock *ccu_clk = to_ccu_clk(c);
  269. debug("%s: %s\n", __func__, c->name);
  270. c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
  271. return c->rate;
  272. }
  273. /* CCU clock operations */
  274. struct clk_ops ccu_clk_ops = {
  275. .enable = ccu_clk_enable,
  276. .get_rate = ccu_clk_get_rate,
  277. };
  278. /* Enable a bus clock */
  279. static int bus_clk_enable(struct clk *c, int enable)
  280. {
  281. struct bus_clock *bus_clk = to_bus_clk(c);
  282. struct bus_clk_data *cd = bus_clk->data;
  283. void *base = (void *)c->ccu_clk_mgr_base;
  284. int ret = 0;
  285. u32 reg;
  286. debug("%s: %s\n", __func__, c->name);
  287. /* enable access */
  288. writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
  289. /* enable gating */
  290. reg = readl(base + cd->gate.offset);
  291. if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
  292. debug("%s already %s\n", c->name,
  293. enable ? "enabled" : "disabled");
  294. else {
  295. int want = (enable) ? 1 : 0;
  296. reg |= (1 << cd->gate.hw_sw_sel_bit);
  297. if (enable)
  298. reg |= (1 << cd->gate.en_bit);
  299. else
  300. reg &= ~(1 << cd->gate.en_bit);
  301. writel(reg, base + cd->gate.offset);
  302. ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
  303. want);
  304. if (ret)
  305. return ret;
  306. }
  307. /* disable access */
  308. writel(0, base + WR_ACCESS_OFFSET);
  309. return ret;
  310. }
  311. /* Get the rate of a bus clock */
  312. static unsigned long bus_clk_get_rate(struct clk *c)
  313. {
  314. struct bus_clock *bus_clk = to_bus_clk(c);
  315. struct ccu_clock *ccu_clk;
  316. debug("%s: %s\n", __func__, c->name);
  317. ccu_clk = to_ccu_clk(c->parent);
  318. c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
  319. c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
  320. return c->rate;
  321. }
  322. /* Bus clock operations */
  323. struct clk_ops bus_clk_ops = {
  324. .enable = bus_clk_enable,
  325. .get_rate = bus_clk_get_rate,
  326. };
  327. /* Enable a reference clock */
  328. static int ref_clk_enable(struct clk *c, int enable)
  329. {
  330. debug("%s: %s\n", __func__, c->name);
  331. return 0;
  332. }
  333. /* Reference clock operations */
  334. struct clk_ops ref_clk_ops = {
  335. .enable = ref_clk_enable,
  336. };
  337. /*
  338. * clk.h implementation follows
  339. */
  340. /* Initialize the clock framework */
  341. int clk_init(void)
  342. {
  343. debug("%s:\n", __func__);
  344. return 0;
  345. }
  346. /* Get a clock handle, give a name string */
  347. struct clk *clk_get(const char *con_id)
  348. {
  349. int i;
  350. struct clk_lookup *clk_tblp;
  351. debug("%s: %s\n", __func__, con_id);
  352. clk_tblp = arch_clk_tbl;
  353. for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
  354. if (clk_tblp->con_id) {
  355. if (!con_id || strcmp(clk_tblp->con_id, con_id))
  356. continue;
  357. return clk_tblp->clk;
  358. }
  359. }
  360. return NULL;
  361. }
  362. /* Enable a clock */
  363. int clk_enable(struct clk *c)
  364. {
  365. int ret = 0;
  366. debug("%s: %s\n", __func__, c->name);
  367. if (!c->ops || !c->ops->enable)
  368. return -1;
  369. /* enable parent clock first */
  370. if (c->parent)
  371. ret = clk_enable(c->parent);
  372. if (ret)
  373. return ret;
  374. if (!c->use_cnt) {
  375. c->use_cnt++;
  376. ret = c->ops->enable(c, 1);
  377. }
  378. return ret;
  379. }
  380. /* Disable a clock */
  381. void clk_disable(struct clk *c)
  382. {
  383. debug("%s: %s\n", __func__, c->name);
  384. if (!c->ops || !c->ops->enable)
  385. return;
  386. if (c->use_cnt) {
  387. c->use_cnt--;
  388. c->ops->enable(c, 0);
  389. }
  390. /* disable parent */
  391. if (c->parent)
  392. clk_disable(c->parent);
  393. }
  394. /* Get the clock rate */
  395. unsigned long clk_get_rate(struct clk *c)
  396. {
  397. unsigned long rate;
  398. if (!c || !c->ops || !c->ops->get_rate)
  399. return 0;
  400. debug("%s: %s\n", __func__, c->name);
  401. rate = c->ops->get_rate(c);
  402. debug("%s: rate = %ld\n", __func__, rate);
  403. return rate;
  404. }
  405. /* Set the clock rate */
  406. int clk_set_rate(struct clk *c, unsigned long rate)
  407. {
  408. int ret;
  409. if (!c || !c->ops || !c->ops->set_rate)
  410. return -EINVAL;
  411. debug("%s: %s rate=%ld\n", __func__, c->name, rate);
  412. if (c->use_cnt)
  413. return -EINVAL;
  414. ret = c->ops->set_rate(c, rate);
  415. return ret;
  416. }
  417. /* Not required for this arch */
  418. /*
  419. long clk_round_rate(struct clk *clk, unsigned long rate);
  420. int clk_set_parent(struct clk *clk, struct clk *parent);
  421. struct clk *clk_get_parent(struct clk *clk);
  422. */