pic32mzda.dtsi 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Microchip Technology, Inc.
  4. * Purna Chandra Mandal, <purna.mandal@microchip.com>
  5. */
  6. #include <dt-bindings/interrupt-controller/irq.h>
  7. #include <dt-bindings/clock/microchip,clock.h>
  8. #include <dt-bindings/gpio/gpio.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "microchip,pic32mzda", "microchip,pic32mz";
  12. aliases {
  13. gpio0 = &gpioA;
  14. gpio1 = &gpioB;
  15. gpio2 = &gpioC;
  16. gpio3 = &gpioD;
  17. gpio4 = &gpioE;
  18. gpio5 = &gpioF;
  19. gpio6 = &gpioG;
  20. gpio7 = &gpioH;
  21. gpio8 = &gpioJ;
  22. gpio9 = &gpioK;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. compatible = "mips,mips14kc";
  29. device-type = "cpu";
  30. reg = <0>;
  31. };
  32. };
  33. clock: clk@1f801200 {
  34. compatible = "microchip,pic32mzda-clk";
  35. reg = <0x1f801200 0x1000>;
  36. #clock-cells = <1>;
  37. };
  38. uart1: serial@1f822000 {
  39. compatible = "microchip,pic32mzda-uart";
  40. reg = <0x1f822000 0x50>;
  41. interrupt-parent = <&evic>;
  42. interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
  43. status = "disabled";
  44. clocks = <&clock PB2CLK>;
  45. };
  46. uart2: serial@1f822200 {
  47. compatible = "microchip,pic32mzda-uart";
  48. reg = <0x1f822200 0x50>;
  49. interrupt-parent = <&evic>;
  50. interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
  51. clocks = <&clock PB2CLK>;
  52. status = "disabled";
  53. };
  54. uart6: serial@1f822a00 {
  55. compatible = "microchip,pic32mzda-uart";
  56. reg = <0x1f822a00 0x50>;
  57. interrupt-parent = <&evic>;
  58. interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
  59. clocks = <&clock PB2CLK>;
  60. status = "disabled";
  61. };
  62. evic: interrupt-controller@1f810000 {
  63. compatible = "microchip,pic32mzda-evic";
  64. interrupt-controller;
  65. #interrupt-cells = <2>;
  66. reg = <0x1f810000 0x1000>;
  67. };
  68. pinctrl: pinctrl@1f801400 {
  69. #address-cells = <1>;
  70. #size-cells = <1>;
  71. compatible = "microchip,pic32mzda-pinctrl";
  72. reg = <0x1f801400 0x100>, /* in */
  73. <0x1f801500 0x200>, /* out */
  74. <0x1f860000 0xa00>; /* port */
  75. reg-names = "ppsin","ppsout","port";
  76. status = "disabled";
  77. gpioA: gpio0@1f860000 {
  78. compatible = "microchip,pic32mzda-gpio";
  79. reg = <0x1f860000 0xe0>;
  80. gpio-controller;
  81. #gpio-cells = <2>;
  82. };
  83. gpioB: gpio1@1f860100 {
  84. compatible = "microchip,pic32mzda-gpio";
  85. reg = <0x1f860100 0xe0>;
  86. gpio-controller;
  87. #gpio-cells = <2>;
  88. };
  89. gpioC: gpio2@1f860200 {
  90. compatible = "microchip,pic32mzda-gpio";
  91. reg = <0x1f860200 0xe0>;
  92. gpio-controller;
  93. #gpio-cells = <2>;
  94. };
  95. gpioD: gpio3@1f860300 {
  96. compatible = "microchip,pic32mzda-gpio";
  97. reg = <0x1f860300 0xe0>;
  98. gpio-controller;
  99. #gpio-cells = <2>;
  100. };
  101. gpioE: gpio4@1f860400 {
  102. compatible = "microchip,pic32mzda-gpio";
  103. reg = <0x1f860400 0xe0>;
  104. gpio-controller;
  105. #gpio-cells = <2>;
  106. };
  107. gpioF: gpio5@1f860500 {
  108. compatible = "microchip,pic32mzda-gpio";
  109. reg = <0x1f860500 0xe0>;
  110. gpio-controller;
  111. #gpio-cells = <2>;
  112. };
  113. gpioG: gpio6@1f860600 {
  114. compatible = "microchip,pic32mzda-gpio";
  115. reg = <0x1f860600 0xe0>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. };
  119. gpioH: gpio7@1f860700 {
  120. compatible = "microchip,pic32mzda-gpio";
  121. reg = <0x1f860700 0xe0>;
  122. gpio-controller;
  123. #gpio-cells = <2>;
  124. };
  125. gpioJ: gpio9@1f860800 {
  126. compatible = "microchip,pic32mzda-gpio";
  127. reg = <0x1f860800 0xe0>;
  128. gpio-controller;
  129. #gpio-cells = <2>;
  130. };
  131. gpioK: gpio10@1f860900 {
  132. compatible = "microchip,pic32mzda-gpio";
  133. reg = <0x1f860900 0xe0>;
  134. gpio-controller;
  135. #gpio-cells = <2>;
  136. };
  137. };
  138. sdhci: sdhci@1f8ec000 {
  139. compatible = "microchip,pic32mzda-sdhci";
  140. reg = <0x1f8ec000 0x100>;
  141. interrupt-parent = <&evic>;
  142. interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
  143. clocks = <&clock REF4CLK>, <&clock PB5CLK>;
  144. clock-names = "base_clk", "sys_clk";
  145. clock-freq-min-max = <25000000>,<25000000>;
  146. bus-width = <4>;
  147. status = "disabled";
  148. };
  149. ethernet: ethernet@1f882000 {
  150. compatible = "microchip,pic32mzda-eth";
  151. reg = <0x1f882000 0x1000>;
  152. interrupt-parent = <&evic>;
  153. interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
  154. clocks = <&clock PB5CLK>;
  155. status = "disabled";
  156. #address-cells = <1>;
  157. #size-cells = <0>;
  158. };
  159. usb: musb@1f8e3000 {
  160. compatible = "microchip,pic32mzda-usb";
  161. reg = <0x1f8e3000 0x1000>,
  162. <0x1f884000 0x1000>;
  163. reg-names = "mc", "control";
  164. interrupt-parent = <&evic>;
  165. interrupts = <132 IRQ_TYPE_EDGE_RISING>,
  166. <133 IRQ_TYPE_LEVEL_HIGH>;
  167. clocks = <&clock PB5CLK>;
  168. clock-names = "usb_clk";
  169. status = "disabled";
  170. };
  171. };