pcie_dw_mvebu.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. *
  5. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  6. *
  7. * Based on:
  8. * - drivers/pci/pcie_imx.c
  9. * - drivers/pci/pci_mvebu.c
  10. * - drivers/pci/pcie_xilinx.c
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <pci.h>
  15. #include <asm/io.h>
  16. #include <asm-generic/gpio.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /* PCI Config space registers */
  19. #define PCIE_CONFIG_BAR0 0x10
  20. #define PCIE_LINK_STATUS_REG 0x80
  21. #define PCIE_LINK_STATUS_SPEED_OFF 16
  22. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  23. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  24. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  25. /* Resizable bar capability registers */
  26. #define RESIZABLE_BAR_CAP 0x250
  27. #define RESIZABLE_BAR_CTL0 0x254
  28. #define RESIZABLE_BAR_CTL1 0x258
  29. /* iATU registers */
  30. #define PCIE_ATU_VIEWPORT 0x900
  31. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  32. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  33. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  34. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  35. #define PCIE_ATU_CR1 0x904
  36. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  37. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  38. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  39. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  40. #define PCIE_ATU_CR2 0x908
  41. #define PCIE_ATU_ENABLE (0x1 << 31)
  42. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  43. #define PCIE_ATU_LOWER_BASE 0x90C
  44. #define PCIE_ATU_UPPER_BASE 0x910
  45. #define PCIE_ATU_LIMIT 0x914
  46. #define PCIE_ATU_LOWER_TARGET 0x918
  47. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  48. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  49. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  50. #define PCIE_ATU_UPPER_TARGET 0x91C
  51. #define PCIE_LINK_CAPABILITY 0x7C
  52. #define PCIE_LINK_CTL_2 0xA0
  53. #define TARGET_LINK_SPEED_MASK 0xF
  54. #define LINK_SPEED_GEN_1 0x1
  55. #define LINK_SPEED_GEN_2 0x2
  56. #define LINK_SPEED_GEN_3 0x3
  57. #define PCIE_GEN3_RELATED 0x890
  58. #define GEN3_EQU_DISABLE (1 << 16)
  59. #define GEN3_ZRXDC_NON_COMP (1 << 0)
  60. #define PCIE_GEN3_EQU_CTRL 0x8A8
  61. #define GEN3_EQU_EVAL_2MS_DISABLE (1 << 5)
  62. #define PCIE_ROOT_COMPLEX_MODE_MASK (0xF << 4)
  63. #define PCIE_LINK_UP_TIMEOUT_MS 100
  64. #define PCIE_GLOBAL_CONTROL 0x8000
  65. #define PCIE_APP_LTSSM_EN (1 << 2)
  66. #define PCIE_DEVICE_TYPE_OFFSET (4)
  67. #define PCIE_DEVICE_TYPE_MASK (0xF)
  68. #define PCIE_DEVICE_TYPE_EP (0x0) /* Endpoint */
  69. #define PCIE_DEVICE_TYPE_LEP (0x1) /* Legacy endpoint */
  70. #define PCIE_DEVICE_TYPE_RC (0x4) /* Root complex */
  71. #define PCIE_GLOBAL_STATUS 0x8008
  72. #define PCIE_GLB_STS_RDLH_LINK_UP (1 << 1)
  73. #define PCIE_GLB_STS_PHY_LINK_UP (1 << 9)
  74. #define PCIE_ARCACHE_TRC 0x8050
  75. #define PCIE_AWCACHE_TRC 0x8054
  76. #define ARCACHE_SHAREABLE_CACHEABLE 0x3511
  77. #define AWCACHE_SHAREABLE_CACHEABLE 0x5311
  78. #define LINK_SPEED_GEN_1 0x1
  79. #define LINK_SPEED_GEN_2 0x2
  80. #define LINK_SPEED_GEN_3 0x3
  81. /**
  82. * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
  83. *
  84. * @ctrl_base: The base address of the register space
  85. * @cfg_base: The base address of the configuration space
  86. * @cfg_size: The size of the configuration space which is needed
  87. * as it gets written into the PCIE_ATU_LIMIT register
  88. * @first_busno: This driver supports multiple PCIe controllers.
  89. * first_busno stores the bus number of the PCIe root-port
  90. * number which may vary depending on the PCIe setup
  91. * (PEX switches etc).
  92. */
  93. struct pcie_dw_mvebu {
  94. void *ctrl_base;
  95. void *cfg_base;
  96. fdt_size_t cfg_size;
  97. int first_busno;
  98. /* IO and MEM PCI regions */
  99. struct pci_region io;
  100. struct pci_region mem;
  101. };
  102. static int pcie_dw_get_link_speed(const void *regs_base)
  103. {
  104. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  105. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  106. }
  107. static int pcie_dw_get_link_width(const void *regs_base)
  108. {
  109. return (readl(regs_base + PCIE_LINK_STATUS_REG) &
  110. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  111. }
  112. /**
  113. * pcie_dw_prog_outbound_atu() - Configure ATU for outbound accesses
  114. *
  115. * @pcie: Pointer to the PCI controller state
  116. * @index: ATU region index
  117. * @type: ATU accsess type
  118. * @cpu_addr: the physical address for the translation entry
  119. * @pci_addr: the pcie bus address for the translation entry
  120. * @size: the size of the translation entry
  121. */
  122. static void pcie_dw_prog_outbound_atu(struct pcie_dw_mvebu *pcie, int index,
  123. int type, u64 cpu_addr, u64 pci_addr,
  124. u32 size)
  125. {
  126. writel(PCIE_ATU_REGION_OUTBOUND | index,
  127. pcie->ctrl_base + PCIE_ATU_VIEWPORT);
  128. writel(lower_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_LOWER_BASE);
  129. writel(upper_32_bits(cpu_addr), pcie->ctrl_base + PCIE_ATU_UPPER_BASE);
  130. writel(lower_32_bits(cpu_addr + size - 1),
  131. pcie->ctrl_base + PCIE_ATU_LIMIT);
  132. writel(lower_32_bits(pci_addr),
  133. pcie->ctrl_base + PCIE_ATU_LOWER_TARGET);
  134. writel(upper_32_bits(pci_addr),
  135. pcie->ctrl_base + PCIE_ATU_UPPER_TARGET);
  136. writel(type, pcie->ctrl_base + PCIE_ATU_CR1);
  137. writel(PCIE_ATU_ENABLE, pcie->ctrl_base + PCIE_ATU_CR2);
  138. }
  139. /**
  140. * set_cfg_address() - Configure the PCIe controller config space access
  141. *
  142. * @pcie: Pointer to the PCI controller state
  143. * @d: PCI device to access
  144. * @where: Offset in the configuration space
  145. *
  146. * Configures the PCIe controller to access the configuration space of
  147. * a specific PCIe device and returns the address to use for this
  148. * access.
  149. *
  150. * Return: Address that can be used to access the configation space
  151. * of the requested device / offset
  152. */
  153. static uintptr_t set_cfg_address(struct pcie_dw_mvebu *pcie,
  154. pci_dev_t d, uint where)
  155. {
  156. uintptr_t va_address;
  157. u32 atu_type;
  158. /*
  159. * Region #0 is used for Outbound CFG space access.
  160. * Direction = Outbound
  161. * Region Index = 0
  162. */
  163. if (PCI_BUS(d) == (pcie->first_busno + 1))
  164. /* For local bus, change TLP Type field to 4. */
  165. atu_type = PCIE_ATU_TYPE_CFG0;
  166. else
  167. /* Otherwise, change TLP Type field to 5. */
  168. atu_type = PCIE_ATU_TYPE_CFG1;
  169. if (PCI_BUS(d) == pcie->first_busno) {
  170. /* Accessing root port configuration space. */
  171. va_address = (uintptr_t)pcie->ctrl_base;
  172. } else {
  173. d = PCI_MASK_BUS(d) | (PCI_BUS(d) - pcie->first_busno);
  174. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  175. atu_type, (u64)pcie->cfg_base,
  176. d << 8, pcie->cfg_size);
  177. va_address = (uintptr_t)pcie->cfg_base;
  178. }
  179. va_address += where & ~0x3;
  180. return va_address;
  181. }
  182. /**
  183. * pcie_dw_addr_valid() - Check for valid bus address
  184. *
  185. * @d: The PCI device to access
  186. * @first_busno: Bus number of the PCIe controller root complex
  187. *
  188. * Return 1 (true) if the PCI device can be accessed by this controller.
  189. *
  190. * Return: 1 on valid, 0 on invalid
  191. */
  192. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  193. {
  194. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  195. return 0;
  196. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  197. return 0;
  198. return 1;
  199. }
  200. /**
  201. * pcie_dw_mvebu_read_config() - Read from configuration space
  202. *
  203. * @bus: Pointer to the PCI bus
  204. * @bdf: Identifies the PCIe device to access
  205. * @offset: The offset into the device's configuration space
  206. * @valuep: A pointer at which to store the read value
  207. * @size: Indicates the size of access to perform
  208. *
  209. * Read a value of size @size from offset @offset within the configuration
  210. * space of the device identified by the bus, device & function numbers in @bdf
  211. * on the PCI bus @bus.
  212. *
  213. * Return: 0 on success
  214. */
  215. static int pcie_dw_mvebu_read_config(struct udevice *bus, pci_dev_t bdf,
  216. uint offset, ulong *valuep,
  217. enum pci_size_t size)
  218. {
  219. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  220. uintptr_t va_address;
  221. ulong value;
  222. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  223. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  224. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  225. debug("- out of range\n");
  226. *valuep = pci_get_ff(size);
  227. return 0;
  228. }
  229. va_address = set_cfg_address(pcie, bdf, offset);
  230. value = readl(va_address);
  231. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  232. *valuep = pci_conv_32_to_size(value, offset, size);
  233. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  234. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  235. pcie->io.bus_start, pcie->io.size);
  236. return 0;
  237. }
  238. /**
  239. * pcie_dw_mvebu_write_config() - Write to configuration space
  240. *
  241. * @bus: Pointer to the PCI bus
  242. * @bdf: Identifies the PCIe device to access
  243. * @offset: The offset into the device's configuration space
  244. * @value: The value to write
  245. * @size: Indicates the size of access to perform
  246. *
  247. * Write the value @value of size @size from offset @offset within the
  248. * configuration space of the device identified by the bus, device & function
  249. * numbers in @bdf on the PCI bus @bus.
  250. *
  251. * Return: 0 on success
  252. */
  253. static int pcie_dw_mvebu_write_config(struct udevice *bus, pci_dev_t bdf,
  254. uint offset, ulong value,
  255. enum pci_size_t size)
  256. {
  257. struct pcie_dw_mvebu *pcie = dev_get_priv(bus);
  258. uintptr_t va_address;
  259. ulong old;
  260. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  261. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  262. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  263. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  264. debug("- out of range\n");
  265. return 0;
  266. }
  267. va_address = set_cfg_address(pcie, bdf, offset);
  268. old = readl(va_address);
  269. value = pci_conv_size_to_32(old, value, offset, size);
  270. writel(value, va_address);
  271. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
  272. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  273. pcie->io.bus_start, pcie->io.size);
  274. return 0;
  275. }
  276. /**
  277. * pcie_dw_configure() - Configure link capabilities and speed
  278. *
  279. * @regs_base: A pointer to the PCIe controller registers
  280. * @cap_speed: The capabilities and speed to configure
  281. *
  282. * Configure the link capabilities and speed in the PCIe root complex.
  283. */
  284. static void pcie_dw_configure(const void *regs_base, u32 cap_speed)
  285. {
  286. /*
  287. * TODO (shadi@marvell.com, sr@denx.de):
  288. * Need to read the serdes speed from the dts and according to it
  289. * configure the PCIe gen
  290. */
  291. /* Set link to GEN 3 */
  292. clrsetbits_le32(regs_base + PCIE_LINK_CTL_2,
  293. TARGET_LINK_SPEED_MASK, cap_speed);
  294. clrsetbits_le32(regs_base + PCIE_LINK_CAPABILITY,
  295. TARGET_LINK_SPEED_MASK, cap_speed);
  296. setbits_le32(regs_base + PCIE_GEN3_EQU_CTRL, GEN3_EQU_EVAL_2MS_DISABLE);
  297. }
  298. /**
  299. * is_link_up() - Return the link state
  300. *
  301. * @regs_base: A pointer to the PCIe controller registers
  302. *
  303. * Return: 1 (true) for active line and 0 (false) for no link
  304. */
  305. static int is_link_up(const void *regs_base)
  306. {
  307. u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
  308. u32 reg;
  309. reg = readl(regs_base + PCIE_GLOBAL_STATUS);
  310. if ((reg & mask) == mask)
  311. return 1;
  312. return 0;
  313. }
  314. /**
  315. * wait_link_up() - Wait for the link to come up
  316. *
  317. * @regs_base: A pointer to the PCIe controller registers
  318. *
  319. * Return: 1 (true) for active line and 0 (false) for no link (timeout)
  320. */
  321. static int wait_link_up(const void *regs_base)
  322. {
  323. unsigned long timeout;
  324. timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
  325. while (!is_link_up(regs_base)) {
  326. if (get_timer(0) > timeout)
  327. return 0;
  328. };
  329. return 1;
  330. }
  331. /**
  332. * pcie_dw_mvebu_pcie_link_up() - Configure the PCIe root port
  333. *
  334. * @regs_base: A pointer to the PCIe controller registers
  335. * @cap_speed: The capabilities and speed to configure
  336. *
  337. * Configure the PCIe controller root complex depending on the
  338. * requested link capabilities and speed.
  339. *
  340. * Return: 1 (true) for active line and 0 (false) for no link
  341. */
  342. static int pcie_dw_mvebu_pcie_link_up(const void *regs_base, u32 cap_speed)
  343. {
  344. if (!is_link_up(regs_base)) {
  345. /* Disable LTSSM state machine to enable configuration */
  346. clrbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  347. PCIE_APP_LTSSM_EN);
  348. }
  349. clrsetbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  350. PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_OFFSET,
  351. PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_OFFSET);
  352. /* Set the PCIe master AXI attributes */
  353. writel(ARCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_ARCACHE_TRC);
  354. writel(AWCACHE_SHAREABLE_CACHEABLE, regs_base + PCIE_AWCACHE_TRC);
  355. /* DW pre link configurations */
  356. pcie_dw_configure(regs_base, cap_speed);
  357. if (!is_link_up(regs_base)) {
  358. /* Configuration done. Start LTSSM */
  359. setbits_le32(regs_base + PCIE_GLOBAL_CONTROL,
  360. PCIE_APP_LTSSM_EN);
  361. }
  362. /* Check that link was established */
  363. if (!wait_link_up(regs_base))
  364. return 0;
  365. /*
  366. * Link can be established in Gen 1. still need to wait
  367. * till MAC nagaotiation is completed
  368. */
  369. udelay(100);
  370. return 1;
  371. }
  372. /**
  373. * pcie_dw_set_host_bars() - Configure the host BARs
  374. *
  375. * @regs_base: A pointer to the PCIe controller registers
  376. *
  377. * Configure the host BARs of the PCIe controller root port so that
  378. * PCI(e) devices may access the system memory.
  379. */
  380. static void pcie_dw_set_host_bars(const void *regs_base)
  381. {
  382. u32 size = gd->ram_size;
  383. u64 max_size;
  384. u32 reg;
  385. u32 bar0;
  386. /* Verify the maximal BAR size */
  387. reg = readl(regs_base + RESIZABLE_BAR_CAP);
  388. max_size = 1ULL << (5 + (reg + (1 << 4)));
  389. if (size > max_size) {
  390. size = max_size;
  391. printf("Warning: PCIe BARs can't map all DRAM space\n");
  392. }
  393. /* Set the BAR base and size towards DDR */
  394. bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf;
  395. bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32;
  396. writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0);
  397. reg = ((size >> 20) - 1) << 12;
  398. writel(size, regs_base + RESIZABLE_BAR_CTL0);
  399. }
  400. /**
  401. * pcie_dw_mvebu_probe() - Probe the PCIe bus for active link
  402. *
  403. * @dev: A pointer to the device being operated on
  404. *
  405. * Probe for an active link on the PCIe bus and configure the controller
  406. * to enable this port.
  407. *
  408. * Return: 0 on success, else -ENODEV
  409. */
  410. static int pcie_dw_mvebu_probe(struct udevice *dev)
  411. {
  412. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  413. struct udevice *ctlr = pci_get_controller(dev);
  414. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  415. #if CONFIG_IS_ENABLED(DM_GPIO)
  416. struct gpio_desc reset_gpio;
  417. gpio_request_by_name(dev, "marvell,reset-gpio", 0, &reset_gpio,
  418. GPIOD_IS_OUT);
  419. /*
  420. * Issue reset to add-in card trough the dedicated GPIO.
  421. * Some boards are connecting the card reset pin to common system
  422. * reset wire and others are using separate GPIO port.
  423. * In the last case we have to release a reset of the addon card
  424. * using this GPIO.
  425. */
  426. if (dm_gpio_is_valid(&reset_gpio)) {
  427. dm_gpio_set_value(&reset_gpio, 1); /* assert */
  428. mdelay(200);
  429. dm_gpio_set_value(&reset_gpio, 0); /* de-assert */
  430. mdelay(200);
  431. }
  432. #else
  433. debug("PCIE Reset on GPIO support is missing\n");
  434. #endif /* DM_GPIO */
  435. pcie->first_busno = dev->seq;
  436. /* Don't register host if link is down */
  437. if (!pcie_dw_mvebu_pcie_link_up(pcie->ctrl_base, LINK_SPEED_GEN_3)) {
  438. printf("PCIE-%d: Link down\n", dev->seq);
  439. } else {
  440. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
  441. pcie_dw_get_link_speed(pcie->ctrl_base),
  442. pcie_dw_get_link_width(pcie->ctrl_base),
  443. hose->first_busno);
  444. }
  445. /* Store the IO and MEM windows settings for future use by the ATU */
  446. pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
  447. pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
  448. pcie->io.size = hose->regions[0].size; /* IO size */
  449. pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
  450. pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
  451. pcie->mem.size = hose->regions[1].size; /* MEM size */
  452. pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
  453. PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
  454. pcie->mem.bus_start, pcie->mem.size);
  455. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  456. clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION,
  457. 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16);
  458. pcie_dw_set_host_bars(pcie->ctrl_base);
  459. return 0;
  460. }
  461. /**
  462. * pcie_dw_mvebu_ofdata_to_platdata() - Translate from DT to device state
  463. *
  464. * @dev: A pointer to the device being operated on
  465. *
  466. * Translate relevant data from the device tree pertaining to device @dev into
  467. * state that the driver will later make use of. This state is stored in the
  468. * device's private data structure.
  469. *
  470. * Return: 0 on success, else -EINVAL
  471. */
  472. static int pcie_dw_mvebu_ofdata_to_platdata(struct udevice *dev)
  473. {
  474. struct pcie_dw_mvebu *pcie = dev_get_priv(dev);
  475. /* Get the controller base address */
  476. pcie->ctrl_base = (void *)devfdt_get_addr_index(dev, 0);
  477. if ((fdt_addr_t)pcie->ctrl_base == FDT_ADDR_T_NONE)
  478. return -EINVAL;
  479. /* Get the config space base address and size */
  480. pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1,
  481. &pcie->cfg_size);
  482. if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
  483. return -EINVAL;
  484. return 0;
  485. }
  486. static const struct dm_pci_ops pcie_dw_mvebu_ops = {
  487. .read_config = pcie_dw_mvebu_read_config,
  488. .write_config = pcie_dw_mvebu_write_config,
  489. };
  490. static const struct udevice_id pcie_dw_mvebu_ids[] = {
  491. { .compatible = "marvell,armada8k-pcie" },
  492. { }
  493. };
  494. U_BOOT_DRIVER(pcie_dw_mvebu) = {
  495. .name = "pcie_dw_mvebu",
  496. .id = UCLASS_PCI,
  497. .of_match = pcie_dw_mvebu_ids,
  498. .ops = &pcie_dw_mvebu_ops,
  499. .ofdata_to_platdata = pcie_dw_mvebu_ofdata_to_platdata,
  500. .probe = pcie_dw_mvebu_probe,
  501. .priv_auto_alloc_size = sizeof(struct pcie_dw_mvebu),
  502. };