pci-aardvark.c 19 KB

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  1. /*
  2. * ***************************************************************************
  3. * Copyright (C) 2015 Marvell International Ltd.
  4. * ***************************************************************************
  5. * This program is free software: you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation, either version 2 of the License, or any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. * ***************************************************************************
  17. */
  18. /* pcie_advk.c
  19. *
  20. * Ported from Linux driver - driver/pci/host/pci-aardvark.c
  21. *
  22. * Author: Victor Gu <xigu@marvell.com>
  23. * Hezi Shahmoon <hezi.shahmoon@marvell.com>
  24. *
  25. */
  26. #include <common.h>
  27. #include <dm.h>
  28. #include <pci.h>
  29. #include <asm/io.h>
  30. #include <asm-generic/gpio.h>
  31. #include <linux/ioport.h>
  32. /* PCIe core registers */
  33. #define PCIE_CORE_CMD_STATUS_REG 0x4
  34. #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
  35. #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
  36. #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
  37. #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
  38. #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
  39. #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
  40. #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
  41. #define PCIE_CORE_LINK_TRAINING BIT(5)
  42. #define PCIE_CORE_ERR_CAPCTL_REG 0x118
  43. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
  44. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
  45. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK BIT(7)
  46. #define PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV BIT(8)
  47. /* PIO registers base address and register offsets */
  48. #define PIO_BASE_ADDR 0x4000
  49. #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
  50. #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
  51. #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
  52. #define PIO_STAT (PIO_BASE_ADDR + 0x4)
  53. #define PIO_COMPLETION_STATUS_SHIFT 7
  54. #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
  55. #define PIO_COMPLETION_STATUS_OK 0
  56. #define PIO_COMPLETION_STATUS_UR 1
  57. #define PIO_COMPLETION_STATUS_CRS 2
  58. #define PIO_COMPLETION_STATUS_CA 4
  59. #define PIO_NON_POSTED_REQ BIT(10)
  60. #define PIO_ERR_STATUS BIT(11)
  61. #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
  62. #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
  63. #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
  64. #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
  65. #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
  66. #define PIO_START (PIO_BASE_ADDR + 0x1c)
  67. #define PIO_ISR (PIO_BASE_ADDR + 0x20)
  68. /* Aardvark Control registers */
  69. #define CONTROL_BASE_ADDR 0x4800
  70. #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
  71. #define PCIE_GEN_SEL_MSK 0x3
  72. #define PCIE_GEN_SEL_SHIFT 0x0
  73. #define SPEED_GEN_1 0
  74. #define SPEED_GEN_2 1
  75. #define SPEED_GEN_3 2
  76. #define IS_RC_MSK 1
  77. #define IS_RC_SHIFT 2
  78. #define LANE_CNT_MSK 0x18
  79. #define LANE_CNT_SHIFT 0x3
  80. #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
  81. #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
  82. #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
  83. #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
  84. #define LINK_TRAINING_EN BIT(6)
  85. #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
  86. #define PCIE_CORE_CTRL2_RESERVED 0x7
  87. #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
  88. #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
  89. #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
  90. /* LMI registers base address and register offsets */
  91. #define LMI_BASE_ADDR 0x6000
  92. #define CFG_REG (LMI_BASE_ADDR + 0x0)
  93. #define LTSSM_SHIFT 24
  94. #define LTSSM_MASK 0x3f
  95. #define LTSSM_L0 0x10
  96. /* PCIe core controller registers */
  97. #define CTRL_CORE_BASE_ADDR 0x18000
  98. #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
  99. #define CTRL_MODE_SHIFT 0x0
  100. #define CTRL_MODE_MASK 0x1
  101. #define PCIE_CORE_MODE_DIRECT 0x0
  102. #define PCIE_CORE_MODE_COMMAND 0x1
  103. /* Transaction types */
  104. #define PCIE_CONFIG_RD_TYPE0 0x8
  105. #define PCIE_CONFIG_RD_TYPE1 0x9
  106. #define PCIE_CONFIG_WR_TYPE0 0xa
  107. #define PCIE_CONFIG_WR_TYPE1 0xb
  108. /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
  109. #define PCIE_BDF(dev) (dev << 4)
  110. #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
  111. #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
  112. #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
  113. #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
  114. #define PCIE_CONF_ADDR(bus, devfn, where) \
  115. (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
  116. PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
  117. /* PCIe Retries & Timeout definitions */
  118. #define MAX_RETRIES 10
  119. #define PIO_WAIT_TIMEOUT 100
  120. #define LINK_WAIT_TIMEOUT 100000
  121. #define CFG_RD_UR_VAL 0xFFFFFFFF
  122. #define CFG_RD_CRS_VAL 0xFFFF0001
  123. /**
  124. * struct pcie_advk - Advk PCIe controller state
  125. *
  126. * @reg_base: The base address of the register space.
  127. * @first_busno: This driver supports multiple PCIe controllers.
  128. * first_busno stores the bus number of the PCIe root-port
  129. * number which may vary depending on the PCIe setup
  130. * (PEX switches etc).
  131. * @device: The pointer to PCI uclass device.
  132. */
  133. struct pcie_advk {
  134. void *base;
  135. int first_busno;
  136. struct udevice *dev;
  137. };
  138. static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
  139. {
  140. writel(val, pcie->base + reg);
  141. }
  142. static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
  143. {
  144. return readl(pcie->base + reg);
  145. }
  146. /**
  147. * pcie_advk_addr_valid() - Check for valid bus address
  148. *
  149. * @bdf: The PCI device to access
  150. * @first_busno: Bus number of the PCIe controller root complex
  151. *
  152. * Return: 1 on valid, 0 on invalid
  153. */
  154. static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
  155. {
  156. /*
  157. * In PCIE-E only a single device (0) can exist
  158. * on the local bus. Beyound the local bus, there might be
  159. * a Switch and everything is possible.
  160. */
  161. if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
  162. return 0;
  163. return 1;
  164. }
  165. /**
  166. * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
  167. *
  168. * @pcie: The PCI device to access
  169. *
  170. * Wait up to 1 micro second for PIO access to be accomplished.
  171. *
  172. * Return 1 (true) if PIO access is accomplished.
  173. * Return 0 (false) if PIO access is timed out.
  174. */
  175. static int pcie_advk_wait_pio(struct pcie_advk *pcie)
  176. {
  177. uint start, isr;
  178. uint count;
  179. for (count = 0; count < MAX_RETRIES; count++) {
  180. start = advk_readl(pcie, PIO_START);
  181. isr = advk_readl(pcie, PIO_ISR);
  182. if (!start && isr)
  183. return 1;
  184. /*
  185. * Do not check the PIO state too frequently,
  186. * 100us delay is appropriate.
  187. */
  188. udelay(PIO_WAIT_TIMEOUT);
  189. }
  190. dev_err(pcie->dev, "config read/write timed out\n");
  191. return 0;
  192. }
  193. /**
  194. * pcie_advk_check_pio_status() - Validate PIO status and get the read result
  195. *
  196. * @pcie: Pointer to the PCI bus
  197. * @read: Read from or write to configuration space - true(read) false(write)
  198. * @read_val: Pointer to the read result, only valid when read is true
  199. *
  200. */
  201. static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
  202. bool read,
  203. uint *read_val)
  204. {
  205. uint reg;
  206. unsigned int status;
  207. char *strcomp_status, *str_posted;
  208. reg = advk_readl(pcie, PIO_STAT);
  209. status = (reg & PIO_COMPLETION_STATUS_MASK) >>
  210. PIO_COMPLETION_STATUS_SHIFT;
  211. switch (status) {
  212. case PIO_COMPLETION_STATUS_OK:
  213. if (reg & PIO_ERR_STATUS) {
  214. strcomp_status = "COMP_ERR";
  215. break;
  216. }
  217. /* Get the read result */
  218. if (read)
  219. *read_val = advk_readl(pcie, PIO_RD_DATA);
  220. /* No error */
  221. strcomp_status = NULL;
  222. break;
  223. case PIO_COMPLETION_STATUS_UR:
  224. if (read) {
  225. /* For reading, UR is not an error status. */
  226. *read_val = CFG_RD_UR_VAL;
  227. strcomp_status = NULL;
  228. } else {
  229. strcomp_status = "UR";
  230. }
  231. break;
  232. case PIO_COMPLETION_STATUS_CRS:
  233. if (read) {
  234. /* For reading, CRS is not an error status. */
  235. *read_val = CFG_RD_CRS_VAL;
  236. strcomp_status = NULL;
  237. } else {
  238. strcomp_status = "CRS";
  239. }
  240. break;
  241. case PIO_COMPLETION_STATUS_CA:
  242. strcomp_status = "CA";
  243. break;
  244. default:
  245. strcomp_status = "Unknown";
  246. break;
  247. }
  248. if (!strcomp_status)
  249. return 0;
  250. if (reg & PIO_NON_POSTED_REQ)
  251. str_posted = "Non-posted";
  252. else
  253. str_posted = "Posted";
  254. dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
  255. str_posted, strcomp_status, reg,
  256. advk_readl(pcie, PIO_ADDR_LS));
  257. return -EFAULT;
  258. }
  259. /**
  260. * pcie_advk_read_config() - Read from configuration space
  261. *
  262. * @bus: Pointer to the PCI bus
  263. * @bdf: Identifies the PCIe device to access
  264. * @offset: The offset into the device's configuration space
  265. * @valuep: A pointer at which to store the read value
  266. * @size: Indicates the size of access to perform
  267. *
  268. * Read a value of size @size from offset @offset within the configuration
  269. * space of the device identified by the bus, device & function numbers in @bdf
  270. * on the PCI bus @bus.
  271. *
  272. * Return: 0 on success
  273. */
  274. static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
  275. uint offset, ulong *valuep,
  276. enum pci_size_t size)
  277. {
  278. struct pcie_advk *pcie = dev_get_priv(bus);
  279. uint reg;
  280. int ret;
  281. dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  282. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  283. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  284. dev_dbg(pcie->dev, "- out of range\n");
  285. *valuep = pci_get_ff(size);
  286. return 0;
  287. }
  288. /* Start PIO */
  289. advk_writel(pcie, 0, PIO_START);
  290. advk_writel(pcie, 1, PIO_ISR);
  291. /* Program the control register */
  292. reg = advk_readl(pcie, PIO_CTRL);
  293. reg &= ~PIO_CTRL_TYPE_MASK;
  294. if (PCI_BUS(bdf) == pcie->first_busno)
  295. reg |= PCIE_CONFIG_RD_TYPE0;
  296. else
  297. reg |= PCIE_CONFIG_RD_TYPE1;
  298. advk_writel(pcie, reg, PIO_CTRL);
  299. /* Program the address registers */
  300. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  301. advk_writel(pcie, reg, PIO_ADDR_LS);
  302. advk_writel(pcie, 0, PIO_ADDR_MS);
  303. /* Start the transfer */
  304. advk_writel(pcie, 1, PIO_START);
  305. if (!pcie_advk_wait_pio(pcie))
  306. return -EINVAL;
  307. /* Check PIO status and get the read result */
  308. ret = pcie_advk_check_pio_status(pcie, true, &reg);
  309. if (ret)
  310. return ret;
  311. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
  312. offset, size, reg);
  313. *valuep = pci_conv_32_to_size(reg, offset, size);
  314. return 0;
  315. }
  316. /**
  317. * pcie_calc_datastrobe() - Calculate data strobe
  318. *
  319. * @offset: The offset into the device's configuration space
  320. * @size: Indicates the size of access to perform
  321. *
  322. * Calculate data strobe according to offset and size
  323. *
  324. */
  325. static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
  326. {
  327. uint bytes, data_strobe;
  328. switch (size) {
  329. case PCI_SIZE_8:
  330. bytes = 1;
  331. break;
  332. case PCI_SIZE_16:
  333. bytes = 2;
  334. break;
  335. default:
  336. bytes = 4;
  337. }
  338. data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
  339. return data_strobe;
  340. }
  341. /**
  342. * pcie_advk_write_config() - Write to configuration space
  343. *
  344. * @bus: Pointer to the PCI bus
  345. * @bdf: Identifies the PCIe device to access
  346. * @offset: The offset into the device's configuration space
  347. * @value: The value to write
  348. * @size: Indicates the size of access to perform
  349. *
  350. * Write the value @value of size @size from offset @offset within the
  351. * configuration space of the device identified by the bus, device & function
  352. * numbers in @bdf on the PCI bus @bus.
  353. *
  354. * Return: 0 on success
  355. */
  356. static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
  357. uint offset, ulong value,
  358. enum pci_size_t size)
  359. {
  360. struct pcie_advk *pcie = dev_get_priv(bus);
  361. uint reg;
  362. dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  363. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  364. dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
  365. offset, size, value);
  366. if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
  367. dev_dbg(pcie->dev, "- out of range\n");
  368. return 0;
  369. }
  370. /* Start PIO */
  371. advk_writel(pcie, 0, PIO_START);
  372. advk_writel(pcie, 1, PIO_ISR);
  373. /* Program the control register */
  374. reg = advk_readl(pcie, PIO_CTRL);
  375. reg &= ~PIO_CTRL_TYPE_MASK;
  376. if (PCI_BUS(bdf) == pcie->first_busno)
  377. reg |= PCIE_CONFIG_WR_TYPE0;
  378. else
  379. reg |= PCIE_CONFIG_WR_TYPE1;
  380. advk_writel(pcie, reg, PIO_CTRL);
  381. /* Program the address registers */
  382. reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
  383. advk_writel(pcie, reg, PIO_ADDR_LS);
  384. advk_writel(pcie, 0, PIO_ADDR_MS);
  385. dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
  386. /* Program the data register */
  387. reg = pci_conv_size_to_32(0, value, offset, size);
  388. advk_writel(pcie, reg, PIO_WR_DATA);
  389. dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg);
  390. /* Program the data strobe */
  391. reg = pcie_calc_datastrobe(offset, size);
  392. advk_writel(pcie, reg, PIO_WR_DATA_STRB);
  393. dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
  394. /* Start the transfer */
  395. advk_writel(pcie, 1, PIO_START);
  396. if (!pcie_advk_wait_pio(pcie)) {
  397. dev_dbg(pcie->dev, "- wait pio timeout\n");
  398. return -EINVAL;
  399. }
  400. /* Check PIO status */
  401. pcie_advk_check_pio_status(pcie, false, &reg);
  402. return 0;
  403. }
  404. /**
  405. * pcie_advk_link_up() - Check if PCIe link is up or not
  406. *
  407. * @pcie: The PCI device to access
  408. *
  409. * Return 1 (true) on link up.
  410. * Return 0 (false) on link down.
  411. */
  412. static int pcie_advk_link_up(struct pcie_advk *pcie)
  413. {
  414. u32 val, ltssm_state;
  415. val = advk_readl(pcie, CFG_REG);
  416. ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
  417. return ltssm_state >= LTSSM_L0;
  418. }
  419. /**
  420. * pcie_advk_wait_for_link() - Wait for link training to be accomplished
  421. *
  422. * @pcie: The PCI device to access
  423. *
  424. * Wait up to 1 second for link training to be accomplished.
  425. *
  426. * Return 1 (true) if link training ends up with link up success.
  427. * Return 0 (false) if link training ends up with link up failure.
  428. */
  429. static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
  430. {
  431. int retries;
  432. /* check if the link is up or not */
  433. for (retries = 0; retries < MAX_RETRIES; retries++) {
  434. if (pcie_advk_link_up(pcie)) {
  435. printf("PCIE-%d: Link up\n", pcie->first_busno);
  436. return 0;
  437. }
  438. udelay(LINK_WAIT_TIMEOUT);
  439. }
  440. printf("PCIE-%d: Link down\n", pcie->first_busno);
  441. return -ETIMEDOUT;
  442. }
  443. /**
  444. * pcie_advk_setup_hw() - PCIe initailzation
  445. *
  446. * @pcie: The PCI device to access
  447. *
  448. * Return: 0 on success
  449. */
  450. static int pcie_advk_setup_hw(struct pcie_advk *pcie)
  451. {
  452. u32 reg;
  453. /* Set to Direct mode */
  454. reg = advk_readl(pcie, CTRL_CONFIG_REG);
  455. reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
  456. reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
  457. advk_writel(pcie, reg, CTRL_CONFIG_REG);
  458. /* Set PCI global control register to RC mode */
  459. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  460. reg |= (IS_RC_MSK << IS_RC_SHIFT);
  461. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  462. /* Set Advanced Error Capabilities and Control PF0 register */
  463. reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
  464. PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
  465. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
  466. PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
  467. advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
  468. /* Set PCIe Device Control and Status 1 PF0 register */
  469. reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
  470. PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
  471. advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
  472. /* Program PCIe Control 2 to disable strict ordering */
  473. reg = PCIE_CORE_CTRL2_RESERVED |
  474. PCIE_CORE_CTRL2_TD_ENABLE;
  475. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  476. /* Set GEN2 */
  477. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  478. reg &= ~PCIE_GEN_SEL_MSK;
  479. reg |= SPEED_GEN_2;
  480. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  481. /* Set lane X1 */
  482. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  483. reg &= ~LANE_CNT_MSK;
  484. reg |= LANE_COUNT_1;
  485. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  486. /* Enable link training */
  487. reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  488. reg |= LINK_TRAINING_EN;
  489. advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  490. /*
  491. * Enable AXI address window location generation:
  492. * When it is enabled, the default outbound window
  493. * configurations (Default User Field: 0xD0074CFC)
  494. * are used to transparent address translation for
  495. * the outbound transactions. Thus, PCIe address
  496. * windows are not required.
  497. */
  498. reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  499. reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
  500. advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
  501. /*
  502. * Bypass the address window mapping for PIO:
  503. * Since PIO access already contains all required
  504. * info over AXI interface by PIO registers, the
  505. * address window is not required.
  506. */
  507. reg = advk_readl(pcie, PIO_CTRL);
  508. reg |= PIO_CTRL_ADDR_WIN_DISABLE;
  509. advk_writel(pcie, reg, PIO_CTRL);
  510. /* Start link training */
  511. reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
  512. reg |= PCIE_CORE_LINK_TRAINING;
  513. advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
  514. /* Wait for PCIe link up */
  515. if (pcie_advk_wait_for_link(pcie))
  516. return -ENXIO;
  517. reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
  518. reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
  519. PCIE_CORE_CMD_IO_ACCESS_EN |
  520. PCIE_CORE_CMD_MEM_IO_REQ_EN;
  521. advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
  522. return 0;
  523. }
  524. /**
  525. * pcie_advk_probe() - Probe the PCIe bus for active link
  526. *
  527. * @dev: A pointer to the device being operated on
  528. *
  529. * Probe for an active link on the PCIe bus and configure the controller
  530. * to enable this port.
  531. *
  532. * Return: 0 on success, else -ENODEV
  533. */
  534. static int pcie_advk_probe(struct udevice *dev)
  535. {
  536. struct pcie_advk *pcie = dev_get_priv(dev);
  537. #if CONFIG_IS_ENABLED(DM_GPIO)
  538. struct gpio_desc reset_gpio;
  539. gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
  540. GPIOD_IS_OUT);
  541. /*
  542. * Issue reset to add-in card through the dedicated GPIO.
  543. * Some boards are connecting the card reset pin to common system
  544. * reset wire and others are using separate GPIO port.
  545. * In the last case we have to release a reset of the addon card
  546. * using this GPIO.
  547. *
  548. * FIX-ME:
  549. * The PCIe RESET signal is not supposed to be released along
  550. * with the SOC RESET signal. It should be lowered as early as
  551. * possible before PCIe PHY initialization. Moreover, the PCIe
  552. * clock should be gated as well.
  553. */
  554. if (dm_gpio_is_valid(&reset_gpio)) {
  555. dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
  556. dm_gpio_set_value(&reset_gpio, 0);
  557. mdelay(200);
  558. dm_gpio_set_value(&reset_gpio, 1);
  559. }
  560. #else
  561. dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
  562. #endif /* DM_GPIO */
  563. pcie->first_busno = dev->seq;
  564. pcie->dev = pci_get_controller(dev);
  565. return pcie_advk_setup_hw(pcie);
  566. }
  567. /**
  568. * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
  569. *
  570. * @dev: A pointer to the device being operated on
  571. *
  572. * Translate relevant data from the device tree pertaining to device @dev into
  573. * state that the driver will later make use of. This state is stored in the
  574. * device's private data structure.
  575. *
  576. * Return: 0 on success, else -EINVAL
  577. */
  578. static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
  579. {
  580. struct pcie_advk *pcie = dev_get_priv(dev);
  581. /* Get the register base address */
  582. pcie->base = (void *)dev_read_addr_index(dev, 0);
  583. if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
  584. return -EINVAL;
  585. return 0;
  586. }
  587. static const struct dm_pci_ops pcie_advk_ops = {
  588. .read_config = pcie_advk_read_config,
  589. .write_config = pcie_advk_write_config,
  590. };
  591. static const struct udevice_id pcie_advk_ids[] = {
  592. { .compatible = "marvell,armada-37xx-pcie" },
  593. { }
  594. };
  595. U_BOOT_DRIVER(pcie_advk) = {
  596. .name = "pcie_advk",
  597. .id = UCLASS_PCI,
  598. .of_match = pcie_advk_ids,
  599. .ops = &pcie_advk_ops,
  600. .ofdata_to_platdata = pcie_advk_ofdata_to_platdata,
  601. .probe = pcie_advk_probe,
  602. .priv_auto_alloc_size = sizeof(struct pcie_advk),
  603. };