sun8i_emac.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Author: Amit Singh Tomar, amittomer25@gmail.com
  5. *
  6. * Ethernet driver for H3/A64/A83T based SoC's
  7. *
  8. * It is derived from the work done by
  9. * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  10. *
  11. */
  12. #include <cpu_func.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/gpio.h>
  16. #include <common.h>
  17. #include <clk.h>
  18. #include <dm.h>
  19. #include <fdt_support.h>
  20. #include <linux/err.h>
  21. #include <malloc.h>
  22. #include <miiphy.h>
  23. #include <net.h>
  24. #include <reset.h>
  25. #include <dt-bindings/pinctrl/sun4i-a10.h>
  26. #if CONFIG_IS_ENABLED(DM_GPIO)
  27. #include <asm-generic/gpio.h>
  28. #endif
  29. #define MDIO_CMD_MII_BUSY BIT(0)
  30. #define MDIO_CMD_MII_WRITE BIT(1)
  31. #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
  32. #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  33. #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
  34. #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
  35. #define CONFIG_TX_DESCR_NUM 32
  36. #define CONFIG_RX_DESCR_NUM 32
  37. #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
  38. /*
  39. * The datasheet says that each descriptor can transfers up to 4096 bytes
  40. * But later, the register documentation reduces that value to 2048,
  41. * using 2048 cause strange behaviours and even BSP driver use 2047
  42. */
  43. #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
  44. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  45. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  46. #define H3_EPHY_DEFAULT_VALUE 0x58000
  47. #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
  48. #define H3_EPHY_ADDR_SHIFT 20
  49. #define REG_PHY_ADDR_MASK GENMASK(4, 0)
  50. #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
  51. #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
  52. #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
  53. #define SC_RMII_EN BIT(13)
  54. #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
  55. #define SC_ETCS_MASK GENMASK(1, 0)
  56. #define SC_ETCS_EXT_GMII 0x1
  57. #define SC_ETCS_INT_GMII 0x2
  58. #define SC_ETXDC_MASK GENMASK(12, 10)
  59. #define SC_ETXDC_OFFSET 10
  60. #define SC_ERXDC_MASK GENMASK(9, 5)
  61. #define SC_ERXDC_OFFSET 5
  62. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  63. #define AHB_GATE_OFFSET_EPHY 0
  64. /* IO mux settings */
  65. #define SUN8I_IOMUX_H3 2
  66. #define SUN8I_IOMUX_R40 5
  67. #define SUN8I_IOMUX 4
  68. /* H3/A64 EMAC Register's offset */
  69. #define EMAC_CTL0 0x00
  70. #define EMAC_CTL1 0x04
  71. #define EMAC_INT_STA 0x08
  72. #define EMAC_INT_EN 0x0c
  73. #define EMAC_TX_CTL0 0x10
  74. #define EMAC_TX_CTL1 0x14
  75. #define EMAC_TX_FLOW_CTL 0x1c
  76. #define EMAC_TX_DMA_DESC 0x20
  77. #define EMAC_RX_CTL0 0x24
  78. #define EMAC_RX_CTL1 0x28
  79. #define EMAC_RX_DMA_DESC 0x34
  80. #define EMAC_MII_CMD 0x48
  81. #define EMAC_MII_DATA 0x4c
  82. #define EMAC_ADDR0_HIGH 0x50
  83. #define EMAC_ADDR0_LOW 0x54
  84. #define EMAC_TX_DMA_STA 0xb0
  85. #define EMAC_TX_CUR_DESC 0xb4
  86. #define EMAC_TX_CUR_BUF 0xb8
  87. #define EMAC_RX_DMA_STA 0xc0
  88. #define EMAC_RX_CUR_DESC 0xc4
  89. DECLARE_GLOBAL_DATA_PTR;
  90. enum emac_variant {
  91. A83T_EMAC = 1,
  92. H3_EMAC,
  93. A64_EMAC,
  94. R40_GMAC,
  95. };
  96. struct emac_dma_desc {
  97. u32 status;
  98. u32 st;
  99. u32 buf_addr;
  100. u32 next;
  101. } __aligned(ARCH_DMA_MINALIGN);
  102. struct emac_eth_dev {
  103. struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
  104. struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
  105. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  106. char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  107. u32 interface;
  108. u32 phyaddr;
  109. u32 link;
  110. u32 speed;
  111. u32 duplex;
  112. u32 phy_configured;
  113. u32 tx_currdescnum;
  114. u32 rx_currdescnum;
  115. u32 addr;
  116. u32 tx_slot;
  117. bool use_internal_phy;
  118. enum emac_variant variant;
  119. void *mac_reg;
  120. phys_addr_t sysctl_reg;
  121. struct phy_device *phydev;
  122. struct mii_dev *bus;
  123. struct clk tx_clk;
  124. struct clk ephy_clk;
  125. struct reset_ctl tx_rst;
  126. struct reset_ctl ephy_rst;
  127. #if CONFIG_IS_ENABLED(DM_GPIO)
  128. struct gpio_desc reset_gpio;
  129. #endif
  130. };
  131. struct sun8i_eth_pdata {
  132. struct eth_pdata eth_pdata;
  133. u32 reset_delays[3];
  134. int tx_delay_ps;
  135. int rx_delay_ps;
  136. };
  137. static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  138. {
  139. struct udevice *dev = bus->priv;
  140. struct emac_eth_dev *priv = dev_get_priv(dev);
  141. ulong start;
  142. u32 miiaddr = 0;
  143. int timeout = CONFIG_MDIO_TIMEOUT;
  144. miiaddr &= ~MDIO_CMD_MII_WRITE;
  145. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  146. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  147. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  148. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  149. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  150. MDIO_CMD_MII_PHY_ADDR_MASK;
  151. miiaddr |= MDIO_CMD_MII_BUSY;
  152. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  153. start = get_timer(0);
  154. while (get_timer(start) < timeout) {
  155. if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
  156. return readl(priv->mac_reg + EMAC_MII_DATA);
  157. udelay(10);
  158. };
  159. return -1;
  160. }
  161. static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  162. u16 val)
  163. {
  164. struct udevice *dev = bus->priv;
  165. struct emac_eth_dev *priv = dev_get_priv(dev);
  166. ulong start;
  167. u32 miiaddr = 0;
  168. int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
  169. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  170. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  171. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  172. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  173. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  174. MDIO_CMD_MII_PHY_ADDR_MASK;
  175. miiaddr |= MDIO_CMD_MII_WRITE;
  176. miiaddr |= MDIO_CMD_MII_BUSY;
  177. writel(val, priv->mac_reg + EMAC_MII_DATA);
  178. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  179. start = get_timer(0);
  180. while (get_timer(start) < timeout) {
  181. if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
  182. MDIO_CMD_MII_BUSY)) {
  183. ret = 0;
  184. break;
  185. }
  186. udelay(10);
  187. };
  188. return ret;
  189. }
  190. static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
  191. {
  192. u32 macid_lo, macid_hi;
  193. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  194. (mac_id[3] << 24);
  195. macid_hi = mac_id[4] + (mac_id[5] << 8);
  196. writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
  197. writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
  198. return 0;
  199. }
  200. static void sun8i_adjust_link(struct emac_eth_dev *priv,
  201. struct phy_device *phydev)
  202. {
  203. u32 v;
  204. v = readl(priv->mac_reg + EMAC_CTL0);
  205. if (phydev->duplex)
  206. v |= BIT(0);
  207. else
  208. v &= ~BIT(0);
  209. v &= ~0x0C;
  210. switch (phydev->speed) {
  211. case 1000:
  212. break;
  213. case 100:
  214. v |= BIT(2);
  215. v |= BIT(3);
  216. break;
  217. case 10:
  218. v |= BIT(3);
  219. break;
  220. }
  221. writel(v, priv->mac_reg + EMAC_CTL0);
  222. }
  223. static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
  224. {
  225. if (priv->use_internal_phy) {
  226. /* H3 based SoC's that has an Internal 100MBit PHY
  227. * needs to be configured and powered up before use
  228. */
  229. *reg &= ~H3_EPHY_DEFAULT_MASK;
  230. *reg |= H3_EPHY_DEFAULT_VALUE;
  231. *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
  232. *reg &= ~H3_EPHY_SHUTDOWN;
  233. *reg |= H3_EPHY_SELECT;
  234. } else
  235. /* This is to select External Gigabit PHY on
  236. * the boards with H3 SoC.
  237. */
  238. *reg &= ~H3_EPHY_SELECT;
  239. return 0;
  240. }
  241. static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
  242. struct emac_eth_dev *priv)
  243. {
  244. int ret;
  245. u32 reg;
  246. if (priv->variant == R40_GMAC) {
  247. /* Select RGMII for R40 */
  248. reg = readl(priv->sysctl_reg + 0x164);
  249. reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
  250. CCM_GMAC_CTRL_GPIT_RGMII |
  251. CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
  252. writel(reg, priv->sysctl_reg + 0x164);
  253. return 0;
  254. }
  255. reg = readl(priv->sysctl_reg + 0x30);
  256. if (priv->variant == H3_EMAC) {
  257. ret = sun8i_emac_set_syscon_ephy(priv, &reg);
  258. if (ret)
  259. return ret;
  260. }
  261. reg &= ~(SC_ETCS_MASK | SC_EPIT);
  262. if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
  263. reg &= ~SC_RMII_EN;
  264. switch (priv->interface) {
  265. case PHY_INTERFACE_MODE_MII:
  266. /* default */
  267. break;
  268. case PHY_INTERFACE_MODE_RGMII:
  269. reg |= SC_EPIT | SC_ETCS_INT_GMII;
  270. break;
  271. case PHY_INTERFACE_MODE_RMII:
  272. if (priv->variant == H3_EMAC ||
  273. priv->variant == A64_EMAC) {
  274. reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
  275. break;
  276. }
  277. /* RMII not supported on A83T */
  278. default:
  279. debug("%s: Invalid PHY interface\n", __func__);
  280. return -EINVAL;
  281. }
  282. if (pdata->tx_delay_ps)
  283. reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
  284. & SC_ETXDC_MASK;
  285. if (pdata->rx_delay_ps)
  286. reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
  287. & SC_ERXDC_MASK;
  288. writel(reg, priv->sysctl_reg + 0x30);
  289. return 0;
  290. }
  291. static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
  292. {
  293. struct phy_device *phydev;
  294. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  295. if (!phydev)
  296. return -ENODEV;
  297. phy_connect_dev(phydev, dev);
  298. priv->phydev = phydev;
  299. phy_config(priv->phydev);
  300. return 0;
  301. }
  302. static void rx_descs_init(struct emac_eth_dev *priv)
  303. {
  304. struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
  305. char *rxbuffs = &priv->rxbuffer[0];
  306. struct emac_dma_desc *desc_p;
  307. u32 idx;
  308. /* flush Rx buffers */
  309. flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
  310. RX_TOTAL_BUFSIZE);
  311. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  312. desc_p = &desc_table_p[idx];
  313. desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
  314. ;
  315. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  316. desc_p->st |= CONFIG_ETH_RXSIZE;
  317. desc_p->status = BIT(31);
  318. }
  319. /* Correcting the last pointer of the chain */
  320. desc_p->next = (uintptr_t)&desc_table_p[0];
  321. flush_dcache_range((uintptr_t)priv->rx_chain,
  322. (uintptr_t)priv->rx_chain +
  323. sizeof(priv->rx_chain));
  324. writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
  325. priv->rx_currdescnum = 0;
  326. }
  327. static void tx_descs_init(struct emac_eth_dev *priv)
  328. {
  329. struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
  330. char *txbuffs = &priv->txbuffer[0];
  331. struct emac_dma_desc *desc_p;
  332. u32 idx;
  333. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  334. desc_p = &desc_table_p[idx];
  335. desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
  336. ;
  337. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  338. desc_p->status = (1 << 31);
  339. desc_p->st = 0;
  340. }
  341. /* Correcting the last pointer of the chain */
  342. desc_p->next = (uintptr_t)&desc_table_p[0];
  343. /* Flush all Tx buffer descriptors */
  344. flush_dcache_range((uintptr_t)priv->tx_chain,
  345. (uintptr_t)priv->tx_chain +
  346. sizeof(priv->tx_chain));
  347. writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
  348. priv->tx_currdescnum = 0;
  349. }
  350. static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
  351. {
  352. u32 reg, v;
  353. int timeout = 100;
  354. reg = readl((priv->mac_reg + EMAC_CTL1));
  355. if (!(reg & 0x1)) {
  356. /* Soft reset MAC */
  357. setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
  358. do {
  359. reg = readl(priv->mac_reg + EMAC_CTL1);
  360. } while ((reg & 0x01) != 0 && (--timeout));
  361. if (!timeout) {
  362. printf("%s: Timeout\n", __func__);
  363. return -1;
  364. }
  365. }
  366. /* Rewrite mac address after reset */
  367. _sun8i_write_hwaddr(priv, enetaddr);
  368. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  369. /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
  370. v |= BIT(1);
  371. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  372. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  373. /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
  374. * complete frame has been written to RX DMA FIFO
  375. */
  376. v |= BIT(1);
  377. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  378. /* DMA */
  379. writel(8 << 24, priv->mac_reg + EMAC_CTL1);
  380. /* Initialize rx/tx descriptors */
  381. rx_descs_init(priv);
  382. tx_descs_init(priv);
  383. /* PHY Start Up */
  384. phy_startup(priv->phydev);
  385. sun8i_adjust_link(priv, priv->phydev);
  386. /* Start RX DMA */
  387. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  388. v |= BIT(30);
  389. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  390. /* Start TX DMA */
  391. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  392. v |= BIT(30);
  393. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  394. /* Enable RX/TX */
  395. setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  396. setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  397. return 0;
  398. }
  399. static int parse_phy_pins(struct udevice *dev)
  400. {
  401. struct emac_eth_dev *priv = dev_get_priv(dev);
  402. int offset;
  403. const char *pin_name;
  404. int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
  405. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  406. "pinctrl-0");
  407. if (offset < 0) {
  408. printf("WARNING: emac: cannot find pinctrl-0 node\n");
  409. return offset;
  410. }
  411. drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
  412. "drive-strength", ~0);
  413. if (drive != ~0) {
  414. if (drive <= 10)
  415. drive = SUN4I_PINCTRL_10_MA;
  416. else if (drive <= 20)
  417. drive = SUN4I_PINCTRL_20_MA;
  418. else if (drive <= 30)
  419. drive = SUN4I_PINCTRL_30_MA;
  420. else
  421. drive = SUN4I_PINCTRL_40_MA;
  422. }
  423. if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
  424. pull = SUN4I_PINCTRL_PULL_UP;
  425. else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
  426. pull = SUN4I_PINCTRL_PULL_DOWN;
  427. for (i = 0; ; i++) {
  428. int pin;
  429. pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
  430. "pins", i, NULL);
  431. if (!pin_name)
  432. break;
  433. pin = sunxi_name_to_gpio(pin_name);
  434. if (pin < 0)
  435. continue;
  436. if (priv->variant == H3_EMAC)
  437. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
  438. else if (priv->variant == R40_GMAC)
  439. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
  440. else
  441. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
  442. if (drive != ~0)
  443. sunxi_gpio_set_drv(pin, drive);
  444. if (pull != ~0)
  445. sunxi_gpio_set_pull(pin, pull);
  446. }
  447. if (!i) {
  448. printf("WARNING: emac: cannot find pins property\n");
  449. return -2;
  450. }
  451. return 0;
  452. }
  453. static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
  454. {
  455. u32 status, desc_num = priv->rx_currdescnum;
  456. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  457. int length = -EAGAIN;
  458. int good_packet = 1;
  459. uintptr_t desc_start = (uintptr_t)desc_p;
  460. uintptr_t desc_end = desc_start +
  461. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  462. ulong data_start = (uintptr_t)desc_p->buf_addr;
  463. ulong data_end;
  464. /* Invalidate entire buffer descriptor */
  465. invalidate_dcache_range(desc_start, desc_end);
  466. status = desc_p->status;
  467. /* Check for DMA own bit */
  468. if (!(status & BIT(31))) {
  469. length = (desc_p->status >> 16) & 0x3FFF;
  470. if (length < 0x40) {
  471. good_packet = 0;
  472. debug("RX: Bad Packet (runt)\n");
  473. }
  474. data_end = data_start + length;
  475. /* Invalidate received data */
  476. invalidate_dcache_range(rounddown(data_start,
  477. ARCH_DMA_MINALIGN),
  478. roundup(data_end,
  479. ARCH_DMA_MINALIGN));
  480. if (good_packet) {
  481. if (length > CONFIG_ETH_RXSIZE) {
  482. printf("Received packet is too big (len=%d)\n",
  483. length);
  484. return -EMSGSIZE;
  485. }
  486. *packetp = (uchar *)(ulong)desc_p->buf_addr;
  487. return length;
  488. }
  489. }
  490. return length;
  491. }
  492. static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
  493. int len)
  494. {
  495. u32 v, desc_num = priv->tx_currdescnum;
  496. struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
  497. uintptr_t desc_start = (uintptr_t)desc_p;
  498. uintptr_t desc_end = desc_start +
  499. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  500. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  501. uintptr_t data_end = data_start +
  502. roundup(len, ARCH_DMA_MINALIGN);
  503. /* Invalidate entire buffer descriptor */
  504. invalidate_dcache_range(desc_start, desc_end);
  505. desc_p->st = len;
  506. /* Mandatory undocumented bit */
  507. desc_p->st |= BIT(24);
  508. memcpy((void *)data_start, packet, len);
  509. /* Flush data to be sent */
  510. flush_dcache_range(data_start, data_end);
  511. /* frame end */
  512. desc_p->st |= BIT(30);
  513. desc_p->st |= BIT(31);
  514. /*frame begin */
  515. desc_p->st |= BIT(29);
  516. desc_p->status = BIT(31);
  517. /*Descriptors st and status field has changed, so FLUSH it */
  518. flush_dcache_range(desc_start, desc_end);
  519. /* Move to next Descriptor and wrap around */
  520. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  521. desc_num = 0;
  522. priv->tx_currdescnum = desc_num;
  523. /* Start the DMA */
  524. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  525. v |= BIT(31);/* mandatory */
  526. v |= BIT(30);/* mandatory */
  527. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  528. return 0;
  529. }
  530. static int sun8i_eth_write_hwaddr(struct udevice *dev)
  531. {
  532. struct eth_pdata *pdata = dev_get_platdata(dev);
  533. struct emac_eth_dev *priv = dev_get_priv(dev);
  534. return _sun8i_write_hwaddr(priv, pdata->enetaddr);
  535. }
  536. static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
  537. {
  538. int ret;
  539. ret = clk_enable(&priv->tx_clk);
  540. if (ret) {
  541. dev_err(dev, "failed to enable TX clock\n");
  542. return ret;
  543. }
  544. if (reset_valid(&priv->tx_rst)) {
  545. ret = reset_deassert(&priv->tx_rst);
  546. if (ret) {
  547. dev_err(dev, "failed to deassert TX reset\n");
  548. goto err_tx_clk;
  549. }
  550. }
  551. /* Only H3/H5 have clock controls for internal EPHY */
  552. if (clk_valid(&priv->ephy_clk)) {
  553. ret = clk_enable(&priv->ephy_clk);
  554. if (ret) {
  555. dev_err(dev, "failed to enable EPHY TX clock\n");
  556. return ret;
  557. }
  558. }
  559. if (reset_valid(&priv->ephy_rst)) {
  560. ret = reset_deassert(&priv->ephy_rst);
  561. if (ret) {
  562. dev_err(dev, "failed to deassert EPHY TX clock\n");
  563. return ret;
  564. }
  565. }
  566. return 0;
  567. err_tx_clk:
  568. clk_disable(&priv->tx_clk);
  569. return ret;
  570. }
  571. #if CONFIG_IS_ENABLED(DM_GPIO)
  572. static int sun8i_mdio_reset(struct mii_dev *bus)
  573. {
  574. struct udevice *dev = bus->priv;
  575. struct emac_eth_dev *priv = dev_get_priv(dev);
  576. struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
  577. int ret;
  578. if (!dm_gpio_is_valid(&priv->reset_gpio))
  579. return 0;
  580. /* reset the phy */
  581. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  582. if (ret)
  583. return ret;
  584. udelay(pdata->reset_delays[0]);
  585. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  586. if (ret)
  587. return ret;
  588. udelay(pdata->reset_delays[1]);
  589. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  590. if (ret)
  591. return ret;
  592. udelay(pdata->reset_delays[2]);
  593. return 0;
  594. }
  595. #endif
  596. static int sun8i_mdio_init(const char *name, struct udevice *priv)
  597. {
  598. struct mii_dev *bus = mdio_alloc();
  599. if (!bus) {
  600. debug("Failed to allocate MDIO bus\n");
  601. return -ENOMEM;
  602. }
  603. bus->read = sun8i_mdio_read;
  604. bus->write = sun8i_mdio_write;
  605. snprintf(bus->name, sizeof(bus->name), name);
  606. bus->priv = (void *)priv;
  607. #if CONFIG_IS_ENABLED(DM_GPIO)
  608. bus->reset = sun8i_mdio_reset;
  609. #endif
  610. return mdio_register(bus);
  611. }
  612. static int sun8i_emac_eth_start(struct udevice *dev)
  613. {
  614. struct eth_pdata *pdata = dev_get_platdata(dev);
  615. return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
  616. }
  617. static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
  618. {
  619. struct emac_eth_dev *priv = dev_get_priv(dev);
  620. return _sun8i_emac_eth_send(priv, packet, length);
  621. }
  622. static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  623. {
  624. struct emac_eth_dev *priv = dev_get_priv(dev);
  625. return _sun8i_eth_recv(priv, packetp);
  626. }
  627. static int _sun8i_free_pkt(struct emac_eth_dev *priv)
  628. {
  629. u32 desc_num = priv->rx_currdescnum;
  630. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  631. uintptr_t desc_start = (uintptr_t)desc_p;
  632. uintptr_t desc_end = desc_start +
  633. roundup(sizeof(u32), ARCH_DMA_MINALIGN);
  634. /* Make the current descriptor valid again */
  635. desc_p->status |= BIT(31);
  636. /* Flush Status field of descriptor */
  637. flush_dcache_range(desc_start, desc_end);
  638. /* Move to next desc and wrap-around condition. */
  639. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  640. desc_num = 0;
  641. priv->rx_currdescnum = desc_num;
  642. return 0;
  643. }
  644. static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
  645. int length)
  646. {
  647. struct emac_eth_dev *priv = dev_get_priv(dev);
  648. return _sun8i_free_pkt(priv);
  649. }
  650. static void sun8i_emac_eth_stop(struct udevice *dev)
  651. {
  652. struct emac_eth_dev *priv = dev_get_priv(dev);
  653. /* Stop Rx/Tx transmitter */
  654. clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  655. clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  656. /* Stop TX DMA */
  657. clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
  658. phy_shutdown(priv->phydev);
  659. }
  660. static int sun8i_emac_eth_probe(struct udevice *dev)
  661. {
  662. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  663. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  664. struct emac_eth_dev *priv = dev_get_priv(dev);
  665. int ret;
  666. priv->mac_reg = (void *)pdata->iobase;
  667. ret = sun8i_emac_board_setup(priv);
  668. if (ret)
  669. return ret;
  670. sun8i_emac_set_syscon(sun8i_pdata, priv);
  671. sun8i_mdio_init(dev->name, dev);
  672. priv->bus = miiphy_get_dev_by_name(dev->name);
  673. return sun8i_phy_init(priv, dev);
  674. }
  675. static const struct eth_ops sun8i_emac_eth_ops = {
  676. .start = sun8i_emac_eth_start,
  677. .write_hwaddr = sun8i_eth_write_hwaddr,
  678. .send = sun8i_emac_eth_send,
  679. .recv = sun8i_emac_eth_recv,
  680. .free_pkt = sun8i_eth_free_pkt,
  681. .stop = sun8i_emac_eth_stop,
  682. };
  683. static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
  684. {
  685. int emac_node, ephy_node, ret, ephy_handle;
  686. emac_node = fdt_path_offset(gd->fdt_blob,
  687. "/soc/ethernet@1c30000");
  688. if (emac_node < 0) {
  689. debug("failed to get emac node\n");
  690. return emac_node;
  691. }
  692. ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
  693. emac_node, "phy-handle");
  694. /* look for mdio-mux node for internal PHY node */
  695. ephy_node = fdt_path_offset(gd->fdt_blob,
  696. "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
  697. if (ephy_node < 0) {
  698. debug("failed to get mdio-mux with internal PHY\n");
  699. return ephy_node;
  700. }
  701. /* This is not the phy we are looking for */
  702. if (ephy_node != ephy_handle)
  703. return 0;
  704. ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
  705. "allwinner,sun8i-h3-mdio-internal");
  706. if (ret < 0) {
  707. debug("failed to find mdio-internal node\n");
  708. return ret;
  709. }
  710. ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
  711. &priv->ephy_clk);
  712. if (ret) {
  713. dev_err(dev, "failed to get EPHY TX clock\n");
  714. return ret;
  715. }
  716. ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
  717. &priv->ephy_rst);
  718. if (ret) {
  719. dev_err(dev, "failed to get EPHY TX reset\n");
  720. return ret;
  721. }
  722. priv->use_internal_phy = true;
  723. return 0;
  724. }
  725. static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
  726. {
  727. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  728. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  729. struct emac_eth_dev *priv = dev_get_priv(dev);
  730. const char *phy_mode;
  731. const fdt32_t *reg;
  732. int node = dev_of_offset(dev);
  733. int offset = 0;
  734. #if CONFIG_IS_ENABLED(DM_GPIO)
  735. int reset_flags = GPIOD_IS_OUT;
  736. #endif
  737. int ret;
  738. pdata->iobase = devfdt_get_addr(dev);
  739. if (pdata->iobase == FDT_ADDR_T_NONE) {
  740. debug("%s: Cannot find MAC base address\n", __func__);
  741. return -EINVAL;
  742. }
  743. priv->variant = dev_get_driver_data(dev);
  744. if (!priv->variant) {
  745. printf("%s: Missing variant\n", __func__);
  746. return -EINVAL;
  747. }
  748. ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
  749. if (ret) {
  750. dev_err(dev, "failed to get TX clock\n");
  751. return ret;
  752. }
  753. ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
  754. if (ret && ret != -ENOENT) {
  755. dev_err(dev, "failed to get TX reset\n");
  756. return ret;
  757. }
  758. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
  759. if (offset < 0) {
  760. debug("%s: cannot find syscon node\n", __func__);
  761. return -EINVAL;
  762. }
  763. reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
  764. if (!reg) {
  765. debug("%s: cannot find reg property in syscon node\n",
  766. __func__);
  767. return -EINVAL;
  768. }
  769. priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
  770. offset, reg);
  771. if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
  772. debug("%s: Cannot find syscon base address\n", __func__);
  773. return -EINVAL;
  774. }
  775. pdata->phy_interface = -1;
  776. priv->phyaddr = -1;
  777. priv->use_internal_phy = false;
  778. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  779. if (offset < 0) {
  780. debug("%s: Cannot find PHY address\n", __func__);
  781. return -EINVAL;
  782. }
  783. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  784. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  785. if (phy_mode)
  786. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  787. printf("phy interface%d\n", pdata->phy_interface);
  788. if (pdata->phy_interface == -1) {
  789. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  790. return -EINVAL;
  791. }
  792. if (priv->variant == H3_EMAC) {
  793. ret = sun8i_get_ephy_nodes(priv);
  794. if (ret)
  795. return ret;
  796. }
  797. priv->interface = pdata->phy_interface;
  798. if (!priv->use_internal_phy)
  799. parse_phy_pins(dev);
  800. sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  801. "allwinner,tx-delay-ps", 0);
  802. if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
  803. printf("%s: Invalid TX delay value %d\n", __func__,
  804. sun8i_pdata->tx_delay_ps);
  805. sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  806. "allwinner,rx-delay-ps", 0);
  807. if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
  808. printf("%s: Invalid RX delay value %d\n", __func__,
  809. sun8i_pdata->rx_delay_ps);
  810. #if CONFIG_IS_ENABLED(DM_GPIO)
  811. if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  812. "snps,reset-active-low"))
  813. reset_flags |= GPIOD_ACTIVE_LOW;
  814. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  815. &priv->reset_gpio, reset_flags);
  816. if (ret == 0) {
  817. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  818. "snps,reset-delays-us",
  819. sun8i_pdata->reset_delays, 3);
  820. } else if (ret == -ENOENT) {
  821. ret = 0;
  822. }
  823. #endif
  824. return 0;
  825. }
  826. static const struct udevice_id sun8i_emac_eth_ids[] = {
  827. {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
  828. {.compatible = "allwinner,sun50i-a64-emac",
  829. .data = (uintptr_t)A64_EMAC },
  830. {.compatible = "allwinner,sun8i-a83t-emac",
  831. .data = (uintptr_t)A83T_EMAC },
  832. {.compatible = "allwinner,sun8i-r40-gmac",
  833. .data = (uintptr_t)R40_GMAC },
  834. { }
  835. };
  836. U_BOOT_DRIVER(eth_sun8i_emac) = {
  837. .name = "eth_sun8i_emac",
  838. .id = UCLASS_ETH,
  839. .of_match = sun8i_emac_eth_ids,
  840. .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
  841. .probe = sun8i_emac_eth_probe,
  842. .ops = &sun8i_emac_eth_ops,
  843. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  844. .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
  845. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  846. };