mvneta.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  4. *
  5. * U-Boot version:
  6. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  7. *
  8. * Based on the Linux version which is:
  9. * Copyright (C) 2012 Marvell
  10. *
  11. * Rami Rosen <rosenr@marvell.com>
  12. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13. */
  14. #include <common.h>
  15. #include <cpu_func.h>
  16. #include <dm.h>
  17. #include <net.h>
  18. #include <netdev.h>
  19. #include <config.h>
  20. #include <malloc.h>
  21. #include <asm/io.h>
  22. #include <linux/errno.h>
  23. #include <phy.h>
  24. #include <miiphy.h>
  25. #include <watchdog.h>
  26. #include <asm/arch/cpu.h>
  27. #include <asm/arch/soc.h>
  28. #include <linux/compat.h>
  29. #include <linux/mbus.h>
  30. #include <asm-generic/gpio.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #if !defined(CONFIG_PHYLIB)
  33. # error Marvell mvneta requires PHYLIB
  34. #endif
  35. #define CONFIG_NR_CPUS 1
  36. #define ETH_HLEN 14 /* Total octets in header */
  37. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  38. #define WRAP (2 + ETH_HLEN + 4 + 32)
  39. #define MTU 1500
  40. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  41. #define MVNETA_SMI_TIMEOUT 10000
  42. /* Registers */
  43. #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
  44. #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
  45. #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
  46. #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
  47. #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
  48. #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
  49. #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
  50. #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
  51. #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
  52. #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
  53. #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
  54. #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
  55. #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
  56. #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
  57. #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
  58. #define MVNETA_PORT_RX_RESET 0x1cc0
  59. #define MVNETA_PORT_RX_DMA_RESET BIT(0)
  60. #define MVNETA_PHY_ADDR 0x2000
  61. #define MVNETA_PHY_ADDR_MASK 0x1f
  62. #define MVNETA_SMI 0x2004
  63. #define MVNETA_PHY_REG_MASK 0x1f
  64. /* SMI register fields */
  65. #define MVNETA_SMI_DATA_OFFS 0 /* Data */
  66. #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
  67. #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  68. #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  69. #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  70. #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
  71. #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
  72. #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
  73. #define MVNETA_MBUS_RETRY 0x2010
  74. #define MVNETA_UNIT_INTR_CAUSE 0x2080
  75. #define MVNETA_UNIT_CONTROL 0x20B0
  76. #define MVNETA_PHY_POLLING_ENABLE BIT(1)
  77. #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
  78. #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
  79. #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
  80. #define MVNETA_WIN_SIZE_MASK (0xffff0000)
  81. #define MVNETA_BASE_ADDR_ENABLE 0x2290
  82. #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
  83. #define MVNETA_PORT_ACCESS_PROTECT 0x2294
  84. #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
  85. #define MVNETA_PORT_CONFIG 0x2400
  86. #define MVNETA_UNI_PROMISC_MODE BIT(0)
  87. #define MVNETA_DEF_RXQ(q) ((q) << 1)
  88. #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
  89. #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
  90. #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
  91. #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
  92. #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
  93. #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
  94. #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
  95. MVNETA_DEF_RXQ_ARP(q) | \
  96. MVNETA_DEF_RXQ_TCP(q) | \
  97. MVNETA_DEF_RXQ_UDP(q) | \
  98. MVNETA_DEF_RXQ_BPDU(q) | \
  99. MVNETA_TX_UNSET_ERR_SUM | \
  100. MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
  101. #define MVNETA_PORT_CONFIG_EXTEND 0x2404
  102. #define MVNETA_MAC_ADDR_LOW 0x2414
  103. #define MVNETA_MAC_ADDR_HIGH 0x2418
  104. #define MVNETA_SDMA_CONFIG 0x241c
  105. #define MVNETA_SDMA_BRST_SIZE_16 4
  106. #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
  107. #define MVNETA_RX_NO_DATA_SWAP BIT(4)
  108. #define MVNETA_TX_NO_DATA_SWAP BIT(5)
  109. #define MVNETA_DESC_SWAP BIT(6)
  110. #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
  111. #define MVNETA_PORT_STATUS 0x2444
  112. #define MVNETA_TX_IN_PRGRS BIT(1)
  113. #define MVNETA_TX_FIFO_EMPTY BIT(8)
  114. #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
  115. #define MVNETA_SERDES_CFG 0x24A0
  116. #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
  117. #define MVNETA_QSGMII_SERDES_PROTO 0x0667
  118. #define MVNETA_TYPE_PRIO 0x24bc
  119. #define MVNETA_FORCE_UNI BIT(21)
  120. #define MVNETA_TXQ_CMD_1 0x24e4
  121. #define MVNETA_TXQ_CMD 0x2448
  122. #define MVNETA_TXQ_DISABLE_SHIFT 8
  123. #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
  124. #define MVNETA_ACC_MODE 0x2500
  125. #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
  126. #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
  127. #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
  128. #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
  129. /* Exception Interrupt Port/Queue Cause register */
  130. #define MVNETA_INTR_NEW_CAUSE 0x25a0
  131. #define MVNETA_INTR_NEW_MASK 0x25a4
  132. /* bits 0..7 = TXQ SENT, one bit per queue.
  133. * bits 8..15 = RXQ OCCUP, one bit per queue.
  134. * bits 16..23 = RXQ FREE, one bit per queue.
  135. * bit 29 = OLD_REG_SUM, see old reg ?
  136. * bit 30 = TX_ERR_SUM, one bit for 4 ports
  137. * bit 31 = MISC_SUM, one bit for 4 ports
  138. */
  139. #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
  140. #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
  141. #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
  142. #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
  143. #define MVNETA_INTR_OLD_CAUSE 0x25a8
  144. #define MVNETA_INTR_OLD_MASK 0x25ac
  145. /* Data Path Port/Queue Cause Register */
  146. #define MVNETA_INTR_MISC_CAUSE 0x25b0
  147. #define MVNETA_INTR_MISC_MASK 0x25b4
  148. #define MVNETA_INTR_ENABLE 0x25b8
  149. #define MVNETA_RXQ_CMD 0x2680
  150. #define MVNETA_RXQ_DISABLE_SHIFT 8
  151. #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
  152. #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
  153. #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
  154. #define MVNETA_GMAC_CTRL_0 0x2c00
  155. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  156. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  157. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  158. #define MVNETA_GMAC_CTRL_2 0x2c08
  159. #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
  160. #define MVNETA_GMAC2_PORT_RGMII BIT(4)
  161. #define MVNETA_GMAC2_PORT_RESET BIT(6)
  162. #define MVNETA_GMAC_STATUS 0x2c10
  163. #define MVNETA_GMAC_LINK_UP BIT(0)
  164. #define MVNETA_GMAC_SPEED_1000 BIT(1)
  165. #define MVNETA_GMAC_SPEED_100 BIT(2)
  166. #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
  167. #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
  168. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  169. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  170. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  171. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  172. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  173. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  174. #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
  175. #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
  176. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  177. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  178. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  179. #define MVNETA_GMAC_SET_FC_EN BIT(8)
  180. #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
  181. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  182. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  183. #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
  184. #define MVNETA_MIB_COUNTERS_BASE 0x3080
  185. #define MVNETA_MIB_LATE_COLLISION 0x7c
  186. #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
  187. #define MVNETA_DA_FILT_OTH_MCAST 0x3500
  188. #define MVNETA_DA_FILT_UCAST_BASE 0x3600
  189. #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
  190. #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
  191. #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
  192. #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
  193. #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
  194. #define MVNETA_TXQ_DEC_SENT_SHIFT 16
  195. #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
  196. #define MVNETA_TXQ_SENT_DESC_SHIFT 16
  197. #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
  198. #define MVNETA_PORT_TX_RESET 0x3cf0
  199. #define MVNETA_PORT_TX_DMA_RESET BIT(0)
  200. #define MVNETA_TX_MTU 0x3e0c
  201. #define MVNETA_TX_TOKEN_SIZE 0x3e14
  202. #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
  203. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  204. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  205. /* Descriptor ring Macros */
  206. #define MVNETA_QUEUE_NEXT_DESC(q, index) \
  207. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  208. /* Various constants */
  209. /* Coalescing */
  210. #define MVNETA_TXDONE_COAL_PKTS 16
  211. #define MVNETA_RX_COAL_PKTS 32
  212. #define MVNETA_RX_COAL_USEC 100
  213. /* The two bytes Marvell header. Either contains a special value used
  214. * by Marvell switches when a specific hardware mode is enabled (not
  215. * supported by this driver) or is filled automatically by zeroes on
  216. * the RX side. Those two bytes being at the front of the Ethernet
  217. * header, they allow to have the IP header aligned on a 4 bytes
  218. * boundary automatically: the hardware skips those two bytes on its
  219. * own.
  220. */
  221. #define MVNETA_MH_SIZE 2
  222. #define MVNETA_VLAN_TAG_LEN 4
  223. #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
  224. #define MVNETA_TX_CSUM_MAX_SIZE 9800
  225. #define MVNETA_ACC_MODE_EXT 1
  226. /* Timeout constants */
  227. #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
  228. #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
  229. #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
  230. #define MVNETA_TX_MTU_MAX 0x3ffff
  231. /* Max number of Rx descriptors */
  232. #define MVNETA_MAX_RXD 16
  233. /* Max number of Tx descriptors */
  234. #define MVNETA_MAX_TXD 16
  235. /* descriptor aligned size */
  236. #define MVNETA_DESC_ALIGNED_SIZE 32
  237. struct mvneta_port {
  238. void __iomem *base;
  239. struct mvneta_rx_queue *rxqs;
  240. struct mvneta_tx_queue *txqs;
  241. u8 mcast_count[256];
  242. u16 tx_ring_size;
  243. u16 rx_ring_size;
  244. phy_interface_t phy_interface;
  245. unsigned int link;
  246. unsigned int duplex;
  247. unsigned int speed;
  248. int init;
  249. int phyaddr;
  250. struct phy_device *phydev;
  251. #if CONFIG_IS_ENABLED(DM_GPIO)
  252. struct gpio_desc phy_reset_gpio;
  253. #endif
  254. struct mii_dev *bus;
  255. };
  256. /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
  257. * layout of the transmit and reception DMA descriptors, and their
  258. * layout is therefore defined by the hardware design
  259. */
  260. #define MVNETA_TX_L3_OFF_SHIFT 0
  261. #define MVNETA_TX_IP_HLEN_SHIFT 8
  262. #define MVNETA_TX_L4_UDP BIT(16)
  263. #define MVNETA_TX_L3_IP6 BIT(17)
  264. #define MVNETA_TXD_IP_CSUM BIT(18)
  265. #define MVNETA_TXD_Z_PAD BIT(19)
  266. #define MVNETA_TXD_L_DESC BIT(20)
  267. #define MVNETA_TXD_F_DESC BIT(21)
  268. #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
  269. MVNETA_TXD_L_DESC | \
  270. MVNETA_TXD_F_DESC)
  271. #define MVNETA_TX_L4_CSUM_FULL BIT(30)
  272. #define MVNETA_TX_L4_CSUM_NOT BIT(31)
  273. #define MVNETA_RXD_ERR_CRC 0x0
  274. #define MVNETA_RXD_ERR_SUMMARY BIT(16)
  275. #define MVNETA_RXD_ERR_OVERRUN BIT(17)
  276. #define MVNETA_RXD_ERR_LEN BIT(18)
  277. #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
  278. #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
  279. #define MVNETA_RXD_L3_IP4 BIT(25)
  280. #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
  281. #define MVNETA_RXD_L4_CSUM_OK BIT(30)
  282. struct mvneta_tx_desc {
  283. u32 command; /* Options used by HW for packet transmitting.*/
  284. u16 reserverd1; /* csum_l4 (for future use) */
  285. u16 data_size; /* Data size of transmitted packet in bytes */
  286. u32 buf_phys_addr; /* Physical addr of transmitted buffer */
  287. u32 reserved2; /* hw_cmd - (for future use, PMT) */
  288. u32 reserved3[4]; /* Reserved - (for future use) */
  289. };
  290. struct mvneta_rx_desc {
  291. u32 status; /* Info about received packet */
  292. u16 reserved1; /* pnc_info - (for future use, PnC) */
  293. u16 data_size; /* Size of received packet in bytes */
  294. u32 buf_phys_addr; /* Physical address of the buffer */
  295. u32 reserved2; /* pnc_flow_id (for future use, PnC) */
  296. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  297. u16 reserved3; /* prefetch_cmd, for future use */
  298. u16 reserved4; /* csum_l4 - (for future use, PnC) */
  299. u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
  300. u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
  301. };
  302. struct mvneta_tx_queue {
  303. /* Number of this TX queue, in the range 0-7 */
  304. u8 id;
  305. /* Number of TX DMA descriptors in the descriptor ring */
  306. int size;
  307. /* Index of last TX DMA descriptor that was inserted */
  308. int txq_put_index;
  309. /* Index of the TX DMA descriptor to be cleaned up */
  310. int txq_get_index;
  311. /* Virtual address of the TX DMA descriptors array */
  312. struct mvneta_tx_desc *descs;
  313. /* DMA address of the TX DMA descriptors array */
  314. dma_addr_t descs_phys;
  315. /* Index of the last TX DMA descriptor */
  316. int last_desc;
  317. /* Index of the next TX DMA descriptor to process */
  318. int next_desc_to_proc;
  319. };
  320. struct mvneta_rx_queue {
  321. /* rx queue number, in the range 0-7 */
  322. u8 id;
  323. /* num of rx descriptors in the rx descriptor ring */
  324. int size;
  325. /* Virtual address of the RX DMA descriptors array */
  326. struct mvneta_rx_desc *descs;
  327. /* DMA address of the RX DMA descriptors array */
  328. dma_addr_t descs_phys;
  329. /* Index of the last RX DMA descriptor */
  330. int last_desc;
  331. /* Index of the next RX DMA descriptor to process */
  332. int next_desc_to_proc;
  333. };
  334. /* U-Boot doesn't use the queues, so set the number to 1 */
  335. static int rxq_number = 1;
  336. static int txq_number = 1;
  337. static int rxq_def;
  338. struct buffer_location {
  339. struct mvneta_tx_desc *tx_descs;
  340. struct mvneta_rx_desc *rx_descs;
  341. u32 rx_buffers;
  342. };
  343. /*
  344. * All 4 interfaces use the same global buffer, since only one interface
  345. * can be enabled at once
  346. */
  347. static struct buffer_location buffer_loc;
  348. /*
  349. * Page table entries are set to 1MB, or multiples of 1MB
  350. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  351. */
  352. #define BD_SPACE (1 << 20)
  353. /*
  354. * Dummy implementation that can be overwritten by a board
  355. * specific function
  356. */
  357. __weak int board_network_enable(struct mii_dev *bus)
  358. {
  359. return 0;
  360. }
  361. /* Utility/helper methods */
  362. /* Write helper method */
  363. static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
  364. {
  365. writel(data, pp->base + offset);
  366. }
  367. /* Read helper method */
  368. static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
  369. {
  370. return readl(pp->base + offset);
  371. }
  372. /* Clear all MIB counters */
  373. static void mvneta_mib_counters_clear(struct mvneta_port *pp)
  374. {
  375. int i;
  376. /* Perform dummy reads from MIB counters */
  377. for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
  378. mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
  379. }
  380. /* Rx descriptors helper methods */
  381. /* Checks whether the RX descriptor having this status is both the first
  382. * and the last descriptor for the RX packet. Each RX packet is currently
  383. * received through a single RX descriptor, so not having each RX
  384. * descriptor with its first and last bits set is an error
  385. */
  386. static int mvneta_rxq_desc_is_first_last(u32 status)
  387. {
  388. return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
  389. MVNETA_RXD_FIRST_LAST_DESC;
  390. }
  391. /* Add number of descriptors ready to receive new packets */
  392. static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
  393. struct mvneta_rx_queue *rxq,
  394. int ndescs)
  395. {
  396. /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
  397. * be added at once
  398. */
  399. while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
  400. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  401. (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
  402. MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  403. ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
  404. }
  405. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  406. (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  407. }
  408. /* Get number of RX descriptors occupied by received packets */
  409. static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
  410. struct mvneta_rx_queue *rxq)
  411. {
  412. u32 val;
  413. val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
  414. return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
  415. }
  416. /* Update num of rx desc called upon return from rx path or
  417. * from mvneta_rxq_drop_pkts().
  418. */
  419. static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
  420. struct mvneta_rx_queue *rxq,
  421. int rx_done, int rx_filled)
  422. {
  423. u32 val;
  424. if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
  425. val = rx_done |
  426. (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
  427. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  428. return;
  429. }
  430. /* Only 255 descriptors can be added at once */
  431. while ((rx_done > 0) || (rx_filled > 0)) {
  432. if (rx_done <= 0xff) {
  433. val = rx_done;
  434. rx_done = 0;
  435. } else {
  436. val = 0xff;
  437. rx_done -= 0xff;
  438. }
  439. if (rx_filled <= 0xff) {
  440. val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  441. rx_filled = 0;
  442. } else {
  443. val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  444. rx_filled -= 0xff;
  445. }
  446. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  447. }
  448. }
  449. /* Get pointer to next RX descriptor to be processed by SW */
  450. static struct mvneta_rx_desc *
  451. mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
  452. {
  453. int rx_desc = rxq->next_desc_to_proc;
  454. rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
  455. return rxq->descs + rx_desc;
  456. }
  457. /* Tx descriptors helper methods */
  458. /* Update HW with number of TX descriptors to be sent */
  459. static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
  460. struct mvneta_tx_queue *txq,
  461. int pend_desc)
  462. {
  463. u32 val;
  464. /* Only 255 descriptors can be added at once ; Assume caller
  465. * process TX descriptors in quanta less than 256
  466. */
  467. val = pend_desc;
  468. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  469. }
  470. /* Get pointer to next TX descriptor to be processed (send) by HW */
  471. static struct mvneta_tx_desc *
  472. mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
  473. {
  474. int tx_desc = txq->next_desc_to_proc;
  475. txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
  476. return txq->descs + tx_desc;
  477. }
  478. /* Set rxq buf size */
  479. static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
  480. struct mvneta_rx_queue *rxq,
  481. int buf_size)
  482. {
  483. u32 val;
  484. val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
  485. val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
  486. val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
  487. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
  488. }
  489. static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
  490. {
  491. /* phy_addr is set to invalid value for fixed link */
  492. return pp->phyaddr > PHY_MAX_ADDR;
  493. }
  494. /* Start the Ethernet port RX and TX activity */
  495. static void mvneta_port_up(struct mvneta_port *pp)
  496. {
  497. int queue;
  498. u32 q_map;
  499. /* Enable all initialized TXs. */
  500. mvneta_mib_counters_clear(pp);
  501. q_map = 0;
  502. for (queue = 0; queue < txq_number; queue++) {
  503. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  504. if (txq->descs != NULL)
  505. q_map |= (1 << queue);
  506. }
  507. mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
  508. /* Enable all initialized RXQs. */
  509. q_map = 0;
  510. for (queue = 0; queue < rxq_number; queue++) {
  511. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  512. if (rxq->descs != NULL)
  513. q_map |= (1 << queue);
  514. }
  515. mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
  516. }
  517. /* Stop the Ethernet port activity */
  518. static void mvneta_port_down(struct mvneta_port *pp)
  519. {
  520. u32 val;
  521. int count;
  522. /* Stop Rx port activity. Check port Rx activity. */
  523. val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
  524. /* Issue stop command for active channels only */
  525. if (val != 0)
  526. mvreg_write(pp, MVNETA_RXQ_CMD,
  527. val << MVNETA_RXQ_DISABLE_SHIFT);
  528. /* Wait for all Rx activity to terminate. */
  529. count = 0;
  530. do {
  531. if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
  532. netdev_warn(pp->dev,
  533. "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
  534. val);
  535. break;
  536. }
  537. mdelay(1);
  538. val = mvreg_read(pp, MVNETA_RXQ_CMD);
  539. } while (val & 0xff);
  540. /* Stop Tx port activity. Check port Tx activity. Issue stop
  541. * command for active channels only
  542. */
  543. val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
  544. if (val != 0)
  545. mvreg_write(pp, MVNETA_TXQ_CMD,
  546. (val << MVNETA_TXQ_DISABLE_SHIFT));
  547. /* Wait for all Tx activity to terminate. */
  548. count = 0;
  549. do {
  550. if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
  551. netdev_warn(pp->dev,
  552. "TIMEOUT for TX stopped status=0x%08x\n",
  553. val);
  554. break;
  555. }
  556. mdelay(1);
  557. /* Check TX Command reg that all Txqs are stopped */
  558. val = mvreg_read(pp, MVNETA_TXQ_CMD);
  559. } while (val & 0xff);
  560. /* Double check to verify that TX FIFO is empty */
  561. count = 0;
  562. do {
  563. if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
  564. netdev_warn(pp->dev,
  565. "TX FIFO empty timeout status=0x08%x\n",
  566. val);
  567. break;
  568. }
  569. mdelay(1);
  570. val = mvreg_read(pp, MVNETA_PORT_STATUS);
  571. } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
  572. (val & MVNETA_TX_IN_PRGRS));
  573. udelay(200);
  574. }
  575. /* Enable the port by setting the port enable bit of the MAC control register */
  576. static void mvneta_port_enable(struct mvneta_port *pp)
  577. {
  578. u32 val;
  579. /* Enable port */
  580. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  581. val |= MVNETA_GMAC0_PORT_ENABLE;
  582. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  583. }
  584. /* Disable the port and wait for about 200 usec before retuning */
  585. static void mvneta_port_disable(struct mvneta_port *pp)
  586. {
  587. u32 val;
  588. /* Reset the Enable bit in the Serial Control Register */
  589. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  590. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  591. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  592. udelay(200);
  593. }
  594. /* Multicast tables methods */
  595. /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
  596. static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
  597. {
  598. int offset;
  599. u32 val;
  600. if (queue == -1) {
  601. val = 0;
  602. } else {
  603. val = 0x1 | (queue << 1);
  604. val |= (val << 24) | (val << 16) | (val << 8);
  605. }
  606. for (offset = 0; offset <= 0xc; offset += 4)
  607. mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
  608. }
  609. /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
  610. static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
  611. {
  612. int offset;
  613. u32 val;
  614. if (queue == -1) {
  615. val = 0;
  616. } else {
  617. val = 0x1 | (queue << 1);
  618. val |= (val << 24) | (val << 16) | (val << 8);
  619. }
  620. for (offset = 0; offset <= 0xfc; offset += 4)
  621. mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
  622. }
  623. /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
  624. static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
  625. {
  626. int offset;
  627. u32 val;
  628. if (queue == -1) {
  629. memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
  630. val = 0;
  631. } else {
  632. memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
  633. val = 0x1 | (queue << 1);
  634. val |= (val << 24) | (val << 16) | (val << 8);
  635. }
  636. for (offset = 0; offset <= 0xfc; offset += 4)
  637. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  638. }
  639. /* This method sets defaults to the NETA port:
  640. * Clears interrupt Cause and Mask registers.
  641. * Clears all MAC tables.
  642. * Sets defaults to all registers.
  643. * Resets RX and TX descriptor rings.
  644. * Resets PHY.
  645. * This method can be called after mvneta_port_down() to return the port
  646. * settings to defaults.
  647. */
  648. static void mvneta_defaults_set(struct mvneta_port *pp)
  649. {
  650. int cpu;
  651. int queue;
  652. u32 val;
  653. /* Clear all Cause registers */
  654. mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
  655. mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
  656. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  657. /* Mask all interrupts */
  658. mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
  659. mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
  660. mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
  661. mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
  662. /* Enable MBUS Retry bit16 */
  663. mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
  664. /* Set CPU queue access map - all CPUs have access to all RX
  665. * queues and to all TX queues
  666. */
  667. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
  668. mvreg_write(pp, MVNETA_CPU_MAP(cpu),
  669. (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
  670. MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
  671. /* Reset RX and TX DMAs */
  672. mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
  673. mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
  674. /* Disable Legacy WRR, Disable EJP, Release from reset */
  675. mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
  676. for (queue = 0; queue < txq_number; queue++) {
  677. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
  678. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
  679. }
  680. mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
  681. mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
  682. /* Set Port Acceleration Mode */
  683. val = MVNETA_ACC_MODE_EXT;
  684. mvreg_write(pp, MVNETA_ACC_MODE, val);
  685. /* Update val of portCfg register accordingly with all RxQueue types */
  686. val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
  687. mvreg_write(pp, MVNETA_PORT_CONFIG, val);
  688. val = 0;
  689. mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
  690. mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
  691. /* Build PORT_SDMA_CONFIG_REG */
  692. val = 0;
  693. /* Default burst size */
  694. val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  695. val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  696. val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
  697. /* Assign port SDMA configuration */
  698. mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
  699. /* Enable PHY polling in hardware if not in fixed-link mode */
  700. if (!mvneta_port_is_fixed_link(pp)) {
  701. val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
  702. val |= MVNETA_PHY_POLLING_ENABLE;
  703. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  704. }
  705. mvneta_set_ucast_table(pp, -1);
  706. mvneta_set_special_mcast_table(pp, -1);
  707. mvneta_set_other_mcast_table(pp, -1);
  708. }
  709. /* Set unicast address */
  710. static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
  711. int queue)
  712. {
  713. unsigned int unicast_reg;
  714. unsigned int tbl_offset;
  715. unsigned int reg_offset;
  716. /* Locate the Unicast table entry */
  717. last_nibble = (0xf & last_nibble);
  718. /* offset from unicast tbl base */
  719. tbl_offset = (last_nibble / 4) * 4;
  720. /* offset within the above reg */
  721. reg_offset = last_nibble % 4;
  722. unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
  723. if (queue == -1) {
  724. /* Clear accepts frame bit at specified unicast DA tbl entry */
  725. unicast_reg &= ~(0xff << (8 * reg_offset));
  726. } else {
  727. unicast_reg &= ~(0xff << (8 * reg_offset));
  728. unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
  729. }
  730. mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
  731. }
  732. /* Set mac address */
  733. static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
  734. int queue)
  735. {
  736. unsigned int mac_h;
  737. unsigned int mac_l;
  738. if (queue != -1) {
  739. mac_l = (addr[4] << 8) | (addr[5]);
  740. mac_h = (addr[0] << 24) | (addr[1] << 16) |
  741. (addr[2] << 8) | (addr[3] << 0);
  742. mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
  743. mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
  744. }
  745. /* Accept frames of this address */
  746. mvneta_set_ucast_addr(pp, addr[5], queue);
  747. }
  748. static int mvneta_write_hwaddr(struct udevice *dev)
  749. {
  750. mvneta_mac_addr_set(dev_get_priv(dev),
  751. ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
  752. rxq_def);
  753. return 0;
  754. }
  755. /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
  756. static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
  757. u32 phys_addr, u32 cookie)
  758. {
  759. rx_desc->buf_cookie = cookie;
  760. rx_desc->buf_phys_addr = phys_addr;
  761. }
  762. /* Decrement sent descriptors counter */
  763. static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
  764. struct mvneta_tx_queue *txq,
  765. int sent_desc)
  766. {
  767. u32 val;
  768. /* Only 255 TX descriptors can be updated at once */
  769. while (sent_desc > 0xff) {
  770. val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
  771. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  772. sent_desc = sent_desc - 0xff;
  773. }
  774. val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
  775. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  776. }
  777. /* Get number of TX descriptors already sent by HW */
  778. static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
  779. struct mvneta_tx_queue *txq)
  780. {
  781. u32 val;
  782. int sent_desc;
  783. val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
  784. sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
  785. MVNETA_TXQ_SENT_DESC_SHIFT;
  786. return sent_desc;
  787. }
  788. /* Display more error info */
  789. static void mvneta_rx_error(struct mvneta_port *pp,
  790. struct mvneta_rx_desc *rx_desc)
  791. {
  792. u32 status = rx_desc->status;
  793. if (!mvneta_rxq_desc_is_first_last(status)) {
  794. netdev_err(pp->dev,
  795. "bad rx status %08x (buffer oversize), size=%d\n",
  796. status, rx_desc->data_size);
  797. return;
  798. }
  799. switch (status & MVNETA_RXD_ERR_CODE_MASK) {
  800. case MVNETA_RXD_ERR_CRC:
  801. netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
  802. status, rx_desc->data_size);
  803. break;
  804. case MVNETA_RXD_ERR_OVERRUN:
  805. netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
  806. status, rx_desc->data_size);
  807. break;
  808. case MVNETA_RXD_ERR_LEN:
  809. netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
  810. status, rx_desc->data_size);
  811. break;
  812. case MVNETA_RXD_ERR_RESOURCE:
  813. netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
  814. status, rx_desc->data_size);
  815. break;
  816. }
  817. }
  818. static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
  819. int rxq)
  820. {
  821. return &pp->rxqs[rxq];
  822. }
  823. /* Drop packets received by the RXQ and free buffers */
  824. static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
  825. struct mvneta_rx_queue *rxq)
  826. {
  827. int rx_done;
  828. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  829. if (rx_done)
  830. mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
  831. }
  832. /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
  833. static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
  834. int num)
  835. {
  836. int i;
  837. for (i = 0; i < num; i++) {
  838. u32 addr;
  839. /* U-Boot special: Fill in the rx buffer addresses */
  840. addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
  841. mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
  842. }
  843. /* Add this number of RX descriptors as non occupied (ready to
  844. * get packets)
  845. */
  846. mvneta_rxq_non_occup_desc_add(pp, rxq, i);
  847. return 0;
  848. }
  849. /* Rx/Tx queue initialization/cleanup methods */
  850. /* Create a specified RX queue */
  851. static int mvneta_rxq_init(struct mvneta_port *pp,
  852. struct mvneta_rx_queue *rxq)
  853. {
  854. rxq->size = pp->rx_ring_size;
  855. /* Allocate memory for RX descriptors */
  856. rxq->descs_phys = (dma_addr_t)rxq->descs;
  857. if (rxq->descs == NULL)
  858. return -ENOMEM;
  859. WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
  860. rxq->last_desc = rxq->size - 1;
  861. /* Set Rx descriptors queue starting address */
  862. mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
  863. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
  864. /* Fill RXQ with buffers from RX pool */
  865. mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
  866. mvneta_rxq_fill(pp, rxq, rxq->size);
  867. return 0;
  868. }
  869. /* Cleanup Rx queue */
  870. static void mvneta_rxq_deinit(struct mvneta_port *pp,
  871. struct mvneta_rx_queue *rxq)
  872. {
  873. mvneta_rxq_drop_pkts(pp, rxq);
  874. rxq->descs = NULL;
  875. rxq->last_desc = 0;
  876. rxq->next_desc_to_proc = 0;
  877. rxq->descs_phys = 0;
  878. }
  879. /* Create and initialize a tx queue */
  880. static int mvneta_txq_init(struct mvneta_port *pp,
  881. struct mvneta_tx_queue *txq)
  882. {
  883. txq->size = pp->tx_ring_size;
  884. /* Allocate memory for TX descriptors */
  885. txq->descs_phys = (dma_addr_t)txq->descs;
  886. if (txq->descs == NULL)
  887. return -ENOMEM;
  888. WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
  889. txq->last_desc = txq->size - 1;
  890. /* Set maximum bandwidth for enabled TXQs */
  891. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
  892. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
  893. /* Set Tx descriptors queue starting address */
  894. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
  895. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
  896. return 0;
  897. }
  898. /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
  899. static void mvneta_txq_deinit(struct mvneta_port *pp,
  900. struct mvneta_tx_queue *txq)
  901. {
  902. txq->descs = NULL;
  903. txq->last_desc = 0;
  904. txq->next_desc_to_proc = 0;
  905. txq->descs_phys = 0;
  906. /* Set minimum bandwidth for disabled TXQs */
  907. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
  908. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
  909. /* Set Tx descriptors queue starting address and size */
  910. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
  911. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
  912. }
  913. /* Cleanup all Tx queues */
  914. static void mvneta_cleanup_txqs(struct mvneta_port *pp)
  915. {
  916. int queue;
  917. for (queue = 0; queue < txq_number; queue++)
  918. mvneta_txq_deinit(pp, &pp->txqs[queue]);
  919. }
  920. /* Cleanup all Rx queues */
  921. static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
  922. {
  923. int queue;
  924. for (queue = 0; queue < rxq_number; queue++)
  925. mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
  926. }
  927. /* Init all Rx queues */
  928. static int mvneta_setup_rxqs(struct mvneta_port *pp)
  929. {
  930. int queue;
  931. for (queue = 0; queue < rxq_number; queue++) {
  932. int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
  933. if (err) {
  934. netdev_err(pp->dev, "%s: can't create rxq=%d\n",
  935. __func__, queue);
  936. mvneta_cleanup_rxqs(pp);
  937. return err;
  938. }
  939. }
  940. return 0;
  941. }
  942. /* Init all tx queues */
  943. static int mvneta_setup_txqs(struct mvneta_port *pp)
  944. {
  945. int queue;
  946. for (queue = 0; queue < txq_number; queue++) {
  947. int err = mvneta_txq_init(pp, &pp->txqs[queue]);
  948. if (err) {
  949. netdev_err(pp->dev, "%s: can't create txq=%d\n",
  950. __func__, queue);
  951. mvneta_cleanup_txqs(pp);
  952. return err;
  953. }
  954. }
  955. return 0;
  956. }
  957. static void mvneta_start_dev(struct mvneta_port *pp)
  958. {
  959. /* start the Rx/Tx activity */
  960. mvneta_port_enable(pp);
  961. }
  962. static void mvneta_adjust_link(struct udevice *dev)
  963. {
  964. struct mvneta_port *pp = dev_get_priv(dev);
  965. struct phy_device *phydev = pp->phydev;
  966. int status_change = 0;
  967. if (mvneta_port_is_fixed_link(pp)) {
  968. debug("Using fixed link, skip link adjust\n");
  969. return;
  970. }
  971. if (phydev->link) {
  972. if ((pp->speed != phydev->speed) ||
  973. (pp->duplex != phydev->duplex)) {
  974. u32 val;
  975. val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  976. val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  977. MVNETA_GMAC_CONFIG_GMII_SPEED |
  978. MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  979. MVNETA_GMAC_AN_SPEED_EN |
  980. MVNETA_GMAC_AN_DUPLEX_EN);
  981. if (phydev->duplex)
  982. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  983. if (phydev->speed == SPEED_1000)
  984. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  985. else
  986. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  987. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  988. pp->duplex = phydev->duplex;
  989. pp->speed = phydev->speed;
  990. }
  991. }
  992. if (phydev->link != pp->link) {
  993. if (!phydev->link) {
  994. pp->duplex = -1;
  995. pp->speed = 0;
  996. }
  997. pp->link = phydev->link;
  998. status_change = 1;
  999. }
  1000. if (status_change) {
  1001. if (phydev->link) {
  1002. u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  1003. val |= (MVNETA_GMAC_FORCE_LINK_PASS |
  1004. MVNETA_GMAC_FORCE_LINK_DOWN);
  1005. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1006. mvneta_port_up(pp);
  1007. } else {
  1008. mvneta_port_down(pp);
  1009. }
  1010. }
  1011. }
  1012. static int mvneta_open(struct udevice *dev)
  1013. {
  1014. struct mvneta_port *pp = dev_get_priv(dev);
  1015. int ret;
  1016. ret = mvneta_setup_rxqs(pp);
  1017. if (ret)
  1018. return ret;
  1019. ret = mvneta_setup_txqs(pp);
  1020. if (ret)
  1021. return ret;
  1022. mvneta_adjust_link(dev);
  1023. mvneta_start_dev(pp);
  1024. return 0;
  1025. }
  1026. /* Initialize hw */
  1027. static int mvneta_init2(struct mvneta_port *pp)
  1028. {
  1029. int queue;
  1030. /* Disable port */
  1031. mvneta_port_disable(pp);
  1032. /* Set port default values */
  1033. mvneta_defaults_set(pp);
  1034. pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
  1035. GFP_KERNEL);
  1036. if (!pp->txqs)
  1037. return -ENOMEM;
  1038. /* U-Boot special: use preallocated area */
  1039. pp->txqs[0].descs = buffer_loc.tx_descs;
  1040. /* Initialize TX descriptor rings */
  1041. for (queue = 0; queue < txq_number; queue++) {
  1042. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  1043. txq->id = queue;
  1044. txq->size = pp->tx_ring_size;
  1045. }
  1046. pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
  1047. GFP_KERNEL);
  1048. if (!pp->rxqs) {
  1049. kfree(pp->txqs);
  1050. return -ENOMEM;
  1051. }
  1052. /* U-Boot special: use preallocated area */
  1053. pp->rxqs[0].descs = buffer_loc.rx_descs;
  1054. /* Create Rx descriptor rings */
  1055. for (queue = 0; queue < rxq_number; queue++) {
  1056. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  1057. rxq->id = queue;
  1058. rxq->size = pp->rx_ring_size;
  1059. }
  1060. return 0;
  1061. }
  1062. /* platform glue : initialize decoding windows */
  1063. /*
  1064. * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
  1065. * First layer is: GbE Address window that resides inside the GBE unit,
  1066. * Second layer is: Fabric address window which is located in the NIC400
  1067. * (South Fabric).
  1068. * To simplify the address decode configuration for Armada3700, we bypass the
  1069. * first layer of GBE decode window by setting the first window to 4GB.
  1070. */
  1071. static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
  1072. {
  1073. /*
  1074. * Set window size to 4GB, to bypass GBE address decode, leave the
  1075. * work to MBUS decode window
  1076. */
  1077. mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
  1078. /* Enable GBE address decode window 0 by set bit 0 to 0 */
  1079. clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
  1080. MVNETA_BASE_ADDR_ENABLE_BIT);
  1081. /* Set GBE address decode window 0 to full Access (read or write) */
  1082. setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
  1083. MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
  1084. }
  1085. static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
  1086. {
  1087. const struct mbus_dram_target_info *dram;
  1088. u32 win_enable;
  1089. u32 win_protect;
  1090. int i;
  1091. dram = mvebu_mbus_dram_info();
  1092. for (i = 0; i < 6; i++) {
  1093. mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
  1094. mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
  1095. if (i < 4)
  1096. mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
  1097. }
  1098. win_enable = 0x3f;
  1099. win_protect = 0;
  1100. for (i = 0; i < dram->num_cs; i++) {
  1101. const struct mbus_dram_window *cs = dram->cs + i;
  1102. mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
  1103. (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
  1104. mvreg_write(pp, MVNETA_WIN_SIZE(i),
  1105. (cs->size - 1) & 0xffff0000);
  1106. win_enable &= ~(1 << i);
  1107. win_protect |= 3 << (2 * i);
  1108. }
  1109. mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
  1110. }
  1111. /* Power up the port */
  1112. static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
  1113. {
  1114. u32 ctrl;
  1115. /* MAC Cause register should be cleared */
  1116. mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
  1117. ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  1118. /* Even though it might look weird, when we're configured in
  1119. * SGMII or QSGMII mode, the RGMII bit needs to be set.
  1120. */
  1121. switch (phy_mode) {
  1122. case PHY_INTERFACE_MODE_QSGMII:
  1123. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
  1124. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1125. break;
  1126. case PHY_INTERFACE_MODE_SGMII:
  1127. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
  1128. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1129. break;
  1130. case PHY_INTERFACE_MODE_RGMII:
  1131. case PHY_INTERFACE_MODE_RGMII_ID:
  1132. ctrl |= MVNETA_GMAC2_PORT_RGMII;
  1133. break;
  1134. default:
  1135. return -EINVAL;
  1136. }
  1137. /* Cancel Port Reset */
  1138. ctrl &= ~MVNETA_GMAC2_PORT_RESET;
  1139. mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
  1140. while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
  1141. MVNETA_GMAC2_PORT_RESET) != 0)
  1142. continue;
  1143. return 0;
  1144. }
  1145. /* Device initialization routine */
  1146. static int mvneta_init(struct udevice *dev)
  1147. {
  1148. struct eth_pdata *pdata = dev_get_platdata(dev);
  1149. struct mvneta_port *pp = dev_get_priv(dev);
  1150. int err;
  1151. pp->tx_ring_size = MVNETA_MAX_TXD;
  1152. pp->rx_ring_size = MVNETA_MAX_RXD;
  1153. err = mvneta_init2(pp);
  1154. if (err < 0) {
  1155. dev_err(&pdev->dev, "can't init eth hal\n");
  1156. return err;
  1157. }
  1158. mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
  1159. err = mvneta_port_power_up(pp, pp->phy_interface);
  1160. if (err < 0) {
  1161. dev_err(&pdev->dev, "can't power up port\n");
  1162. return err;
  1163. }
  1164. /* Call open() now as it needs to be done before runing send() */
  1165. mvneta_open(dev);
  1166. return 0;
  1167. }
  1168. /* U-Boot only functions follow here */
  1169. /* SMI / MDIO functions */
  1170. static int smi_wait_ready(struct mvneta_port *pp)
  1171. {
  1172. u32 timeout = MVNETA_SMI_TIMEOUT;
  1173. u32 smi_reg;
  1174. /* wait till the SMI is not busy */
  1175. do {
  1176. /* read smi register */
  1177. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1178. if (timeout-- == 0) {
  1179. printf("Error: SMI busy timeout\n");
  1180. return -EFAULT;
  1181. }
  1182. } while (smi_reg & MVNETA_SMI_BUSY);
  1183. return 0;
  1184. }
  1185. /*
  1186. * mvneta_mdio_read - miiphy_read callback function.
  1187. *
  1188. * Returns 16bit phy register value, or 0xffff on error
  1189. */
  1190. static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  1191. {
  1192. struct mvneta_port *pp = bus->priv;
  1193. u32 smi_reg;
  1194. u32 timeout;
  1195. /* check parameters */
  1196. if (addr > MVNETA_PHY_ADDR_MASK) {
  1197. printf("Error: Invalid PHY address %d\n", addr);
  1198. return -EFAULT;
  1199. }
  1200. if (reg > MVNETA_PHY_REG_MASK) {
  1201. printf("Err: Invalid register offset %d\n", reg);
  1202. return -EFAULT;
  1203. }
  1204. /* wait till the SMI is not busy */
  1205. if (smi_wait_ready(pp) < 0)
  1206. return -EFAULT;
  1207. /* fill the phy address and regiser offset and read opcode */
  1208. smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1209. | (reg << MVNETA_SMI_REG_ADDR_OFFS)
  1210. | MVNETA_SMI_OPCODE_READ;
  1211. /* write the smi register */
  1212. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1213. /* wait till read value is ready */
  1214. timeout = MVNETA_SMI_TIMEOUT;
  1215. do {
  1216. /* read smi register */
  1217. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1218. if (timeout-- == 0) {
  1219. printf("Err: SMI read ready timeout\n");
  1220. return -EFAULT;
  1221. }
  1222. } while (!(smi_reg & MVNETA_SMI_READ_VALID));
  1223. /* Wait for the data to update in the SMI register */
  1224. for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
  1225. ;
  1226. return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
  1227. }
  1228. /*
  1229. * mvneta_mdio_write - miiphy_write callback function.
  1230. *
  1231. * Returns 0 if write succeed, -EINVAL on bad parameters
  1232. * -ETIME on timeout
  1233. */
  1234. static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  1235. u16 value)
  1236. {
  1237. struct mvneta_port *pp = bus->priv;
  1238. u32 smi_reg;
  1239. /* check parameters */
  1240. if (addr > MVNETA_PHY_ADDR_MASK) {
  1241. printf("Error: Invalid PHY address %d\n", addr);
  1242. return -EFAULT;
  1243. }
  1244. if (reg > MVNETA_PHY_REG_MASK) {
  1245. printf("Err: Invalid register offset %d\n", reg);
  1246. return -EFAULT;
  1247. }
  1248. /* wait till the SMI is not busy */
  1249. if (smi_wait_ready(pp) < 0)
  1250. return -EFAULT;
  1251. /* fill the phy addr and reg offset and write opcode and data */
  1252. smi_reg = value << MVNETA_SMI_DATA_OFFS;
  1253. smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1254. | (reg << MVNETA_SMI_REG_ADDR_OFFS);
  1255. smi_reg &= ~MVNETA_SMI_OPCODE_READ;
  1256. /* write the smi register */
  1257. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1258. return 0;
  1259. }
  1260. static int mvneta_start(struct udevice *dev)
  1261. {
  1262. struct mvneta_port *pp = dev_get_priv(dev);
  1263. struct phy_device *phydev;
  1264. mvneta_port_power_up(pp, pp->phy_interface);
  1265. if (!pp->init || pp->link == 0) {
  1266. if (mvneta_port_is_fixed_link(pp)) {
  1267. u32 val;
  1268. pp->init = 1;
  1269. pp->link = 1;
  1270. mvneta_init(dev);
  1271. val = MVNETA_GMAC_FORCE_LINK_UP |
  1272. MVNETA_GMAC_IB_BYPASS_AN_EN |
  1273. MVNETA_GMAC_SET_FC_EN |
  1274. MVNETA_GMAC_ADVERT_FC_EN |
  1275. MVNETA_GMAC_SAMPLE_TX_CFG_EN;
  1276. if (pp->duplex)
  1277. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  1278. if (pp->speed == SPEED_1000)
  1279. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  1280. else if (pp->speed == SPEED_100)
  1281. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  1282. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1283. } else {
  1284. /* Set phy address of the port */
  1285. mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
  1286. phydev = phy_connect(pp->bus, pp->phyaddr, dev,
  1287. pp->phy_interface);
  1288. if (!phydev) {
  1289. printf("phy_connect failed\n");
  1290. return -ENODEV;
  1291. }
  1292. pp->phydev = phydev;
  1293. phy_config(phydev);
  1294. phy_startup(phydev);
  1295. if (!phydev->link) {
  1296. printf("%s: No link.\n", phydev->dev->name);
  1297. return -1;
  1298. }
  1299. /* Full init on first call */
  1300. mvneta_init(dev);
  1301. pp->init = 1;
  1302. return 0;
  1303. }
  1304. }
  1305. /* Upon all following calls, this is enough */
  1306. mvneta_port_up(pp);
  1307. mvneta_port_enable(pp);
  1308. return 0;
  1309. }
  1310. static int mvneta_send(struct udevice *dev, void *packet, int length)
  1311. {
  1312. struct mvneta_port *pp = dev_get_priv(dev);
  1313. struct mvneta_tx_queue *txq = &pp->txqs[0];
  1314. struct mvneta_tx_desc *tx_desc;
  1315. int sent_desc;
  1316. u32 timeout = 0;
  1317. /* Get a descriptor for the first part of the packet */
  1318. tx_desc = mvneta_txq_next_desc_get(txq);
  1319. tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
  1320. tx_desc->data_size = length;
  1321. flush_dcache_range((ulong)packet,
  1322. (ulong)packet + ALIGN(length, PKTALIGN));
  1323. /* First and Last descriptor */
  1324. tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
  1325. mvneta_txq_pend_desc_add(pp, txq, 1);
  1326. /* Wait for packet to be sent (queue might help with speed here) */
  1327. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1328. while (!sent_desc) {
  1329. if (timeout++ > 10000) {
  1330. printf("timeout: packet not sent\n");
  1331. return -1;
  1332. }
  1333. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1334. }
  1335. /* txDone has increased - hw sent packet */
  1336. mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
  1337. return 0;
  1338. }
  1339. static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
  1340. {
  1341. struct mvneta_port *pp = dev_get_priv(dev);
  1342. int rx_done;
  1343. struct mvneta_rx_queue *rxq;
  1344. int rx_bytes = 0;
  1345. /* get rx queue */
  1346. rxq = mvneta_rxq_handle_get(pp, rxq_def);
  1347. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  1348. if (rx_done) {
  1349. struct mvneta_rx_desc *rx_desc;
  1350. unsigned char *data;
  1351. u32 rx_status;
  1352. /*
  1353. * No cache invalidation needed here, since the desc's are
  1354. * located in a uncached memory region
  1355. */
  1356. rx_desc = mvneta_rxq_next_desc_get(rxq);
  1357. rx_status = rx_desc->status;
  1358. if (!mvneta_rxq_desc_is_first_last(rx_status) ||
  1359. (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
  1360. mvneta_rx_error(pp, rx_desc);
  1361. /* leave the descriptor untouched */
  1362. return -EIO;
  1363. }
  1364. /* 2 bytes for marvell header. 4 bytes for crc */
  1365. rx_bytes = rx_desc->data_size - 6;
  1366. /* give packet to stack - skip on first 2 bytes */
  1367. data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
  1368. /*
  1369. * No cache invalidation needed here, since the rx_buffer's are
  1370. * located in a uncached memory region
  1371. */
  1372. *packetp = data;
  1373. /*
  1374. * Only mark one descriptor as free
  1375. * since only one was processed
  1376. */
  1377. mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
  1378. }
  1379. return rx_bytes;
  1380. }
  1381. static int mvneta_probe(struct udevice *dev)
  1382. {
  1383. struct eth_pdata *pdata = dev_get_platdata(dev);
  1384. struct mvneta_port *pp = dev_get_priv(dev);
  1385. void *blob = (void *)gd->fdt_blob;
  1386. int node = dev_of_offset(dev);
  1387. struct mii_dev *bus;
  1388. unsigned long addr;
  1389. void *bd_space;
  1390. int ret;
  1391. int fl_node;
  1392. /*
  1393. * Allocate buffer area for descs and rx_buffers. This is only
  1394. * done once for all interfaces. As only one interface can
  1395. * be active. Make this area DMA safe by disabling the D-cache
  1396. */
  1397. if (!buffer_loc.tx_descs) {
  1398. u32 size;
  1399. /* Align buffer area for descs and rx_buffers to 1MiB */
  1400. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  1401. flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
  1402. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
  1403. DCACHE_OFF);
  1404. buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
  1405. size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
  1406. ARCH_DMA_MINALIGN);
  1407. memset(buffer_loc.tx_descs, 0, size);
  1408. buffer_loc.rx_descs = (struct mvneta_rx_desc *)
  1409. ((phys_addr_t)bd_space + size);
  1410. size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
  1411. ARCH_DMA_MINALIGN);
  1412. buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
  1413. }
  1414. pp->base = (void __iomem *)pdata->iobase;
  1415. /* Configure MBUS address windows */
  1416. if (device_is_compatible(dev, "marvell,armada-3700-neta"))
  1417. mvneta_bypass_mbus_windows(pp);
  1418. else
  1419. mvneta_conf_mbus_windows(pp);
  1420. /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
  1421. pp->phy_interface = pdata->phy_interface;
  1422. /* fetch 'fixed-link' property from 'neta' node */
  1423. fl_node = fdt_subnode_offset(blob, node, "fixed-link");
  1424. if (fl_node != -FDT_ERR_NOTFOUND) {
  1425. /* set phy_addr to invalid value for fixed link */
  1426. pp->phyaddr = PHY_MAX_ADDR + 1;
  1427. pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  1428. pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  1429. } else {
  1430. /* Now read phyaddr from DT */
  1431. addr = fdtdec_get_int(blob, node, "phy", 0);
  1432. addr = fdt_node_offset_by_phandle(blob, addr);
  1433. pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  1434. }
  1435. bus = mdio_alloc();
  1436. if (!bus) {
  1437. printf("Failed to allocate MDIO bus\n");
  1438. return -ENOMEM;
  1439. }
  1440. bus->read = mvneta_mdio_read;
  1441. bus->write = mvneta_mdio_write;
  1442. snprintf(bus->name, sizeof(bus->name), dev->name);
  1443. bus->priv = (void *)pp;
  1444. pp->bus = bus;
  1445. ret = mdio_register(bus);
  1446. if (ret)
  1447. return ret;
  1448. #if CONFIG_IS_ENABLED(DM_GPIO)
  1449. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1450. &pp->phy_reset_gpio, GPIOD_IS_OUT);
  1451. if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
  1452. dm_gpio_set_value(&pp->phy_reset_gpio, 1);
  1453. mdelay(10);
  1454. dm_gpio_set_value(&pp->phy_reset_gpio, 0);
  1455. }
  1456. #endif
  1457. return board_network_enable(bus);
  1458. }
  1459. static void mvneta_stop(struct udevice *dev)
  1460. {
  1461. struct mvneta_port *pp = dev_get_priv(dev);
  1462. mvneta_port_down(pp);
  1463. mvneta_port_disable(pp);
  1464. }
  1465. static const struct eth_ops mvneta_ops = {
  1466. .start = mvneta_start,
  1467. .send = mvneta_send,
  1468. .recv = mvneta_recv,
  1469. .stop = mvneta_stop,
  1470. .write_hwaddr = mvneta_write_hwaddr,
  1471. };
  1472. static int mvneta_ofdata_to_platdata(struct udevice *dev)
  1473. {
  1474. struct eth_pdata *pdata = dev_get_platdata(dev);
  1475. const char *phy_mode;
  1476. pdata->iobase = devfdt_get_addr(dev);
  1477. /* Get phy-mode / phy_interface from DT */
  1478. pdata->phy_interface = -1;
  1479. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1480. NULL);
  1481. if (phy_mode)
  1482. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1483. if (pdata->phy_interface == -1) {
  1484. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1485. return -EINVAL;
  1486. }
  1487. return 0;
  1488. }
  1489. static const struct udevice_id mvneta_ids[] = {
  1490. { .compatible = "marvell,armada-370-neta" },
  1491. { .compatible = "marvell,armada-xp-neta" },
  1492. { .compatible = "marvell,armada-3700-neta" },
  1493. { }
  1494. };
  1495. U_BOOT_DRIVER(mvneta) = {
  1496. .name = "mvneta",
  1497. .id = UCLASS_ETH,
  1498. .of_match = mvneta_ids,
  1499. .ofdata_to_platdata = mvneta_ofdata_to_platdata,
  1500. .probe = mvneta_probe,
  1501. .ops = &mvneta_ops,
  1502. .priv_auto_alloc_size = sizeof(struct mvneta_port),
  1503. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1504. };