designware.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. /*
  7. * Designware ethernet IP driver for U-Boot
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <cpu_func.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <miiphy.h>
  15. #include <malloc.h>
  16. #include <pci.h>
  17. #include <reset.h>
  18. #include <linux/compiler.h>
  19. #include <linux/err.h>
  20. #include <linux/kernel.h>
  21. #include <asm/io.h>
  22. #include <power/regulator.h>
  23. #include "designware.h"
  24. static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  25. {
  26. #ifdef CONFIG_DM_ETH
  27. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  28. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  29. #else
  30. struct eth_mac_regs *mac_p = bus->priv;
  31. #endif
  32. ulong start;
  33. u16 miiaddr;
  34. int timeout = CONFIG_MDIO_TIMEOUT;
  35. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  36. ((reg << MIIREGSHIFT) & MII_REGMSK);
  37. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  38. start = get_timer(0);
  39. while (get_timer(start) < timeout) {
  40. if (!(readl(&mac_p->miiaddr) & MII_BUSY))
  41. return readl(&mac_p->miidata);
  42. udelay(10);
  43. };
  44. return -ETIMEDOUT;
  45. }
  46. static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  47. u16 val)
  48. {
  49. #ifdef CONFIG_DM_ETH
  50. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  51. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  52. #else
  53. struct eth_mac_regs *mac_p = bus->priv;
  54. #endif
  55. ulong start;
  56. u16 miiaddr;
  57. int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
  58. writel(val, &mac_p->miidata);
  59. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  60. ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
  61. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  62. start = get_timer(0);
  63. while (get_timer(start) < timeout) {
  64. if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
  65. ret = 0;
  66. break;
  67. }
  68. udelay(10);
  69. };
  70. return ret;
  71. }
  72. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  73. static int dw_mdio_reset(struct mii_dev *bus)
  74. {
  75. struct udevice *dev = bus->priv;
  76. struct dw_eth_dev *priv = dev_get_priv(dev);
  77. struct dw_eth_pdata *pdata = dev_get_platdata(dev);
  78. int ret;
  79. if (!dm_gpio_is_valid(&priv->reset_gpio))
  80. return 0;
  81. /* reset the phy */
  82. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  83. if (ret)
  84. return ret;
  85. udelay(pdata->reset_delays[0]);
  86. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  87. if (ret)
  88. return ret;
  89. udelay(pdata->reset_delays[1]);
  90. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  91. if (ret)
  92. return ret;
  93. udelay(pdata->reset_delays[2]);
  94. return 0;
  95. }
  96. #endif
  97. static int dw_mdio_init(const char *name, void *priv)
  98. {
  99. struct mii_dev *bus = mdio_alloc();
  100. if (!bus) {
  101. printf("Failed to allocate MDIO bus\n");
  102. return -ENOMEM;
  103. }
  104. bus->read = dw_mdio_read;
  105. bus->write = dw_mdio_write;
  106. snprintf(bus->name, sizeof(bus->name), "%s", name);
  107. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  108. bus->reset = dw_mdio_reset;
  109. #endif
  110. bus->priv = priv;
  111. return mdio_register(bus);
  112. }
  113. static void tx_descs_init(struct dw_eth_dev *priv)
  114. {
  115. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  116. struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  117. char *txbuffs = &priv->txbuffs[0];
  118. struct dmamacdescr *desc_p;
  119. u32 idx;
  120. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  121. desc_p = &desc_table_p[idx];
  122. desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
  123. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  124. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  125. desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  126. DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
  127. DESC_TXSTS_TXCHECKINSCTRL |
  128. DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  129. desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  130. desc_p->dmamac_cntl = 0;
  131. desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  132. #else
  133. desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  134. desc_p->txrx_status = 0;
  135. #endif
  136. }
  137. /* Correcting the last pointer of the chain */
  138. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  139. /* Flush all Tx buffer descriptors at once */
  140. flush_dcache_range((ulong)priv->tx_mac_descrtable,
  141. (ulong)priv->tx_mac_descrtable +
  142. sizeof(priv->tx_mac_descrtable));
  143. writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  144. priv->tx_currdescnum = 0;
  145. }
  146. static void rx_descs_init(struct dw_eth_dev *priv)
  147. {
  148. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  149. struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  150. char *rxbuffs = &priv->rxbuffs[0];
  151. struct dmamacdescr *desc_p;
  152. u32 idx;
  153. /* Before passing buffers to GMAC we need to make sure zeros
  154. * written there right after "priv" structure allocation were
  155. * flushed into RAM.
  156. * Otherwise there's a chance to get some of them flushed in RAM when
  157. * GMAC is already pushing data to RAM via DMA. This way incoming from
  158. * GMAC data will be corrupted. */
  159. flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
  160. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  161. desc_p = &desc_table_p[idx];
  162. desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  163. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  164. desc_p->dmamac_cntl =
  165. (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
  166. DESC_RXCTRL_RXCHAIN;
  167. desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  168. }
  169. /* Correcting the last pointer of the chain */
  170. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  171. /* Flush all Rx buffer descriptors at once */
  172. flush_dcache_range((ulong)priv->rx_mac_descrtable,
  173. (ulong)priv->rx_mac_descrtable +
  174. sizeof(priv->rx_mac_descrtable));
  175. writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  176. priv->rx_currdescnum = 0;
  177. }
  178. static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
  179. {
  180. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  181. u32 macid_lo, macid_hi;
  182. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  183. (mac_id[3] << 24);
  184. macid_hi = mac_id[4] + (mac_id[5] << 8);
  185. writel(macid_hi, &mac_p->macaddr0hi);
  186. writel(macid_lo, &mac_p->macaddr0lo);
  187. return 0;
  188. }
  189. static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
  190. struct phy_device *phydev)
  191. {
  192. u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
  193. if (!phydev->link) {
  194. printf("%s: No link.\n", phydev->dev->name);
  195. return 0;
  196. }
  197. if (phydev->speed != 1000)
  198. conf |= MII_PORTSELECT;
  199. else
  200. conf &= ~MII_PORTSELECT;
  201. if (phydev->speed == 100)
  202. conf |= FES_100;
  203. if (phydev->duplex)
  204. conf |= FULLDPLXMODE;
  205. writel(conf, &mac_p->conf);
  206. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  207. (phydev->duplex) ? "full" : "half",
  208. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  209. return 0;
  210. }
  211. static void _dw_eth_halt(struct dw_eth_dev *priv)
  212. {
  213. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  214. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  215. writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
  216. writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
  217. phy_shutdown(priv->phydev);
  218. }
  219. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
  220. {
  221. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  222. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  223. unsigned int start;
  224. int ret;
  225. writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
  226. /*
  227. * When a MII PHY is used, we must set the PS bit for the DMA
  228. * reset to succeed.
  229. */
  230. if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
  231. writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
  232. else
  233. writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
  234. start = get_timer(0);
  235. while (readl(&dma_p->busmode) & DMAMAC_SRST) {
  236. if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
  237. printf("DMA reset timeout\n");
  238. return -ETIMEDOUT;
  239. }
  240. mdelay(100);
  241. };
  242. /*
  243. * Soft reset above clears HW address registers.
  244. * So we have to set it here once again.
  245. */
  246. _dw_write_hwaddr(priv, enetaddr);
  247. rx_descs_init(priv);
  248. tx_descs_init(priv);
  249. writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
  250. #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
  251. writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
  252. &dma_p->opmode);
  253. #else
  254. writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
  255. &dma_p->opmode);
  256. #endif
  257. writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
  258. #ifdef CONFIG_DW_AXI_BURST_LEN
  259. writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
  260. #endif
  261. /* Start up the PHY */
  262. ret = phy_startup(priv->phydev);
  263. if (ret) {
  264. printf("Could not initialize PHY %s\n",
  265. priv->phydev->dev->name);
  266. return ret;
  267. }
  268. ret = dw_adjust_link(priv, mac_p, priv->phydev);
  269. if (ret)
  270. return ret;
  271. return 0;
  272. }
  273. int designware_eth_enable(struct dw_eth_dev *priv)
  274. {
  275. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  276. if (!priv->phydev->link)
  277. return -EIO;
  278. writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
  279. return 0;
  280. }
  281. #define ETH_ZLEN 60
  282. static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
  283. {
  284. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  285. u32 desc_num = priv->tx_currdescnum;
  286. struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
  287. ulong desc_start = (ulong)desc_p;
  288. ulong desc_end = desc_start +
  289. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  290. ulong data_start = desc_p->dmamac_addr;
  291. ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  292. /*
  293. * Strictly we only need to invalidate the "txrx_status" field
  294. * for the following check, but on some platforms we cannot
  295. * invalidate only 4 bytes, so we flush the entire descriptor,
  296. * which is 16 bytes in total. This is safe because the
  297. * individual descriptors in the array are each aligned to
  298. * ARCH_DMA_MINALIGN and padded appropriately.
  299. */
  300. invalidate_dcache_range(desc_start, desc_end);
  301. /* Check if the descriptor is owned by CPU */
  302. if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  303. printf("CPU not owner of tx frame\n");
  304. return -EPERM;
  305. }
  306. memcpy((void *)data_start, packet, length);
  307. if (length < ETH_ZLEN) {
  308. memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
  309. length = ETH_ZLEN;
  310. }
  311. /* Flush data to be sent */
  312. flush_dcache_range(data_start, data_end);
  313. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  314. desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
  315. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  316. ((length << DESC_TXCTRL_SIZE1SHFT) &
  317. DESC_TXCTRL_SIZE1MASK);
  318. desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
  319. desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
  320. #else
  321. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  322. ((length << DESC_TXCTRL_SIZE1SHFT) &
  323. DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
  324. DESC_TXCTRL_TXFIRST;
  325. desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
  326. #endif
  327. /* Flush modified buffer descriptor */
  328. flush_dcache_range(desc_start, desc_end);
  329. /* Test the wrap-around condition. */
  330. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  331. desc_num = 0;
  332. priv->tx_currdescnum = desc_num;
  333. /* Start the transmission */
  334. writel(POLL_DATA, &dma_p->txpolldemand);
  335. return 0;
  336. }
  337. static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
  338. {
  339. u32 status, desc_num = priv->rx_currdescnum;
  340. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  341. int length = -EAGAIN;
  342. ulong desc_start = (ulong)desc_p;
  343. ulong desc_end = desc_start +
  344. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  345. ulong data_start = desc_p->dmamac_addr;
  346. ulong data_end;
  347. /* Invalidate entire buffer descriptor */
  348. invalidate_dcache_range(desc_start, desc_end);
  349. status = desc_p->txrx_status;
  350. /* Check if the owner is the CPU */
  351. if (!(status & DESC_RXSTS_OWNBYDMA)) {
  352. length = (status & DESC_RXSTS_FRMLENMSK) >>
  353. DESC_RXSTS_FRMLENSHFT;
  354. /* Invalidate received data */
  355. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  356. invalidate_dcache_range(data_start, data_end);
  357. *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
  358. }
  359. return length;
  360. }
  361. static int _dw_free_pkt(struct dw_eth_dev *priv)
  362. {
  363. u32 desc_num = priv->rx_currdescnum;
  364. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  365. ulong desc_start = (ulong)desc_p;
  366. ulong desc_end = desc_start +
  367. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  368. /*
  369. * Make the current descriptor valid again and go to
  370. * the next one
  371. */
  372. desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  373. /* Flush only status field - others weren't changed */
  374. flush_dcache_range(desc_start, desc_end);
  375. /* Test the wrap-around condition. */
  376. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  377. desc_num = 0;
  378. priv->rx_currdescnum = desc_num;
  379. return 0;
  380. }
  381. static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
  382. {
  383. struct phy_device *phydev;
  384. int phy_addr = -1, ret;
  385. #ifdef CONFIG_PHY_ADDR
  386. phy_addr = CONFIG_PHY_ADDR;
  387. #endif
  388. phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
  389. if (!phydev)
  390. return -ENODEV;
  391. phydev->supported &= PHY_GBIT_FEATURES;
  392. if (priv->max_speed) {
  393. ret = phy_set_supported(phydev, priv->max_speed);
  394. if (ret)
  395. return ret;
  396. }
  397. phydev->advertising = phydev->supported;
  398. priv->phydev = phydev;
  399. phy_config(phydev);
  400. return 0;
  401. }
  402. #ifndef CONFIG_DM_ETH
  403. static int dw_eth_init(struct eth_device *dev, bd_t *bis)
  404. {
  405. int ret;
  406. ret = designware_eth_init(dev->priv, dev->enetaddr);
  407. if (!ret)
  408. ret = designware_eth_enable(dev->priv);
  409. return ret;
  410. }
  411. static int dw_eth_send(struct eth_device *dev, void *packet, int length)
  412. {
  413. return _dw_eth_send(dev->priv, packet, length);
  414. }
  415. static int dw_eth_recv(struct eth_device *dev)
  416. {
  417. uchar *packet;
  418. int length;
  419. length = _dw_eth_recv(dev->priv, &packet);
  420. if (length == -EAGAIN)
  421. return 0;
  422. net_process_received_packet(packet, length);
  423. _dw_free_pkt(dev->priv);
  424. return 0;
  425. }
  426. static void dw_eth_halt(struct eth_device *dev)
  427. {
  428. return _dw_eth_halt(dev->priv);
  429. }
  430. static int dw_write_hwaddr(struct eth_device *dev)
  431. {
  432. return _dw_write_hwaddr(dev->priv, dev->enetaddr);
  433. }
  434. int designware_initialize(ulong base_addr, u32 interface)
  435. {
  436. struct eth_device *dev;
  437. struct dw_eth_dev *priv;
  438. dev = (struct eth_device *) malloc(sizeof(struct eth_device));
  439. if (!dev)
  440. return -ENOMEM;
  441. /*
  442. * Since the priv structure contains the descriptors which need a strict
  443. * buswidth alignment, memalign is used to allocate memory
  444. */
  445. priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
  446. sizeof(struct dw_eth_dev));
  447. if (!priv) {
  448. free(dev);
  449. return -ENOMEM;
  450. }
  451. if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
  452. printf("designware: buffers are outside DMA memory\n");
  453. return -EINVAL;
  454. }
  455. memset(dev, 0, sizeof(struct eth_device));
  456. memset(priv, 0, sizeof(struct dw_eth_dev));
  457. sprintf(dev->name, "dwmac.%lx", base_addr);
  458. dev->iobase = (int)base_addr;
  459. dev->priv = priv;
  460. priv->dev = dev;
  461. priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
  462. priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
  463. DW_DMA_BASE_OFFSET);
  464. dev->init = dw_eth_init;
  465. dev->send = dw_eth_send;
  466. dev->recv = dw_eth_recv;
  467. dev->halt = dw_eth_halt;
  468. dev->write_hwaddr = dw_write_hwaddr;
  469. eth_register(dev);
  470. priv->interface = interface;
  471. dw_mdio_init(dev->name, priv->mac_regs_p);
  472. priv->bus = miiphy_get_dev_by_name(dev->name);
  473. return dw_phy_init(priv, dev);
  474. }
  475. #endif
  476. #ifdef CONFIG_DM_ETH
  477. static int designware_eth_start(struct udevice *dev)
  478. {
  479. struct eth_pdata *pdata = dev_get_platdata(dev);
  480. struct dw_eth_dev *priv = dev_get_priv(dev);
  481. int ret;
  482. ret = designware_eth_init(priv, pdata->enetaddr);
  483. if (ret)
  484. return ret;
  485. ret = designware_eth_enable(priv);
  486. if (ret)
  487. return ret;
  488. return 0;
  489. }
  490. int designware_eth_send(struct udevice *dev, void *packet, int length)
  491. {
  492. struct dw_eth_dev *priv = dev_get_priv(dev);
  493. return _dw_eth_send(priv, packet, length);
  494. }
  495. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  496. {
  497. struct dw_eth_dev *priv = dev_get_priv(dev);
  498. return _dw_eth_recv(priv, packetp);
  499. }
  500. int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  501. {
  502. struct dw_eth_dev *priv = dev_get_priv(dev);
  503. return _dw_free_pkt(priv);
  504. }
  505. void designware_eth_stop(struct udevice *dev)
  506. {
  507. struct dw_eth_dev *priv = dev_get_priv(dev);
  508. return _dw_eth_halt(priv);
  509. }
  510. int designware_eth_write_hwaddr(struct udevice *dev)
  511. {
  512. struct eth_pdata *pdata = dev_get_platdata(dev);
  513. struct dw_eth_dev *priv = dev_get_priv(dev);
  514. return _dw_write_hwaddr(priv, pdata->enetaddr);
  515. }
  516. static int designware_eth_bind(struct udevice *dev)
  517. {
  518. #ifdef CONFIG_DM_PCI
  519. static int num_cards;
  520. char name[20];
  521. /* Create a unique device name for PCI type devices */
  522. if (device_is_on_pci_bus(dev)) {
  523. sprintf(name, "eth_designware#%u", num_cards++);
  524. device_set_name(dev, name);
  525. }
  526. #endif
  527. return 0;
  528. }
  529. int designware_eth_probe(struct udevice *dev)
  530. {
  531. struct eth_pdata *pdata = dev_get_platdata(dev);
  532. struct dw_eth_dev *priv = dev_get_priv(dev);
  533. u32 iobase = pdata->iobase;
  534. ulong ioaddr;
  535. int ret, err;
  536. struct reset_ctl_bulk reset_bulk;
  537. #ifdef CONFIG_CLK
  538. int i, clock_nb;
  539. priv->clock_count = 0;
  540. clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  541. if (clock_nb > 0) {
  542. priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
  543. GFP_KERNEL);
  544. if (!priv->clocks)
  545. return -ENOMEM;
  546. for (i = 0; i < clock_nb; i++) {
  547. err = clk_get_by_index(dev, i, &priv->clocks[i]);
  548. if (err < 0)
  549. break;
  550. err = clk_enable(&priv->clocks[i]);
  551. if (err && err != -ENOSYS && err != -ENOTSUPP) {
  552. pr_err("failed to enable clock %d\n", i);
  553. clk_free(&priv->clocks[i]);
  554. goto clk_err;
  555. }
  556. priv->clock_count++;
  557. }
  558. } else if (clock_nb != -ENOENT) {
  559. pr_err("failed to get clock phandle(%d)\n", clock_nb);
  560. return clock_nb;
  561. }
  562. #endif
  563. #if defined(CONFIG_DM_REGULATOR)
  564. struct udevice *phy_supply;
  565. ret = device_get_supply_regulator(dev, "phy-supply",
  566. &phy_supply);
  567. if (ret) {
  568. debug("%s: No phy supply\n", dev->name);
  569. } else {
  570. ret = regulator_set_enable(phy_supply, true);
  571. if (ret) {
  572. puts("Error enabling phy supply\n");
  573. return ret;
  574. }
  575. }
  576. #endif
  577. ret = reset_get_bulk(dev, &reset_bulk);
  578. if (ret)
  579. dev_warn(dev, "Can't get reset: %d\n", ret);
  580. else
  581. reset_deassert_bulk(&reset_bulk);
  582. #ifdef CONFIG_DM_PCI
  583. /*
  584. * If we are on PCI bus, either directly attached to a PCI root port,
  585. * or via a PCI bridge, fill in platdata before we probe the hardware.
  586. */
  587. if (device_is_on_pci_bus(dev)) {
  588. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  589. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  590. iobase = dm_pci_mem_to_phys(dev, iobase);
  591. pdata->iobase = iobase;
  592. pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
  593. }
  594. #endif
  595. debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
  596. ioaddr = iobase;
  597. priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
  598. priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
  599. priv->interface = pdata->phy_interface;
  600. priv->max_speed = pdata->max_speed;
  601. ret = dw_mdio_init(dev->name, dev);
  602. if (ret) {
  603. err = ret;
  604. goto mdio_err;
  605. }
  606. priv->bus = miiphy_get_dev_by_name(dev->name);
  607. ret = dw_phy_init(priv, dev);
  608. debug("%s, ret=%d\n", __func__, ret);
  609. if (!ret)
  610. return 0;
  611. /* continue here for cleanup if no PHY found */
  612. err = ret;
  613. mdio_unregister(priv->bus);
  614. mdio_free(priv->bus);
  615. mdio_err:
  616. #ifdef CONFIG_CLK
  617. clk_err:
  618. ret = clk_release_all(priv->clocks, priv->clock_count);
  619. if (ret)
  620. pr_err("failed to disable all clocks\n");
  621. #endif
  622. return err;
  623. }
  624. static int designware_eth_remove(struct udevice *dev)
  625. {
  626. struct dw_eth_dev *priv = dev_get_priv(dev);
  627. free(priv->phydev);
  628. mdio_unregister(priv->bus);
  629. mdio_free(priv->bus);
  630. #ifdef CONFIG_CLK
  631. return clk_release_all(priv->clocks, priv->clock_count);
  632. #else
  633. return 0;
  634. #endif
  635. }
  636. const struct eth_ops designware_eth_ops = {
  637. .start = designware_eth_start,
  638. .send = designware_eth_send,
  639. .recv = designware_eth_recv,
  640. .free_pkt = designware_eth_free_pkt,
  641. .stop = designware_eth_stop,
  642. .write_hwaddr = designware_eth_write_hwaddr,
  643. };
  644. int designware_eth_ofdata_to_platdata(struct udevice *dev)
  645. {
  646. struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
  647. #if CONFIG_IS_ENABLED(DM_GPIO)
  648. struct dw_eth_dev *priv = dev_get_priv(dev);
  649. #endif
  650. struct eth_pdata *pdata = &dw_pdata->eth_pdata;
  651. const char *phy_mode;
  652. #if CONFIG_IS_ENABLED(DM_GPIO)
  653. int reset_flags = GPIOD_IS_OUT;
  654. #endif
  655. int ret = 0;
  656. pdata->iobase = dev_read_addr(dev);
  657. pdata->phy_interface = -1;
  658. phy_mode = dev_read_string(dev, "phy-mode");
  659. if (phy_mode)
  660. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  661. if (pdata->phy_interface == -1) {
  662. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  663. return -EINVAL;
  664. }
  665. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  666. #if CONFIG_IS_ENABLED(DM_GPIO)
  667. if (dev_read_bool(dev, "snps,reset-active-low"))
  668. reset_flags |= GPIOD_ACTIVE_LOW;
  669. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  670. &priv->reset_gpio, reset_flags);
  671. if (ret == 0) {
  672. ret = dev_read_u32_array(dev, "snps,reset-delays-us",
  673. dw_pdata->reset_delays, 3);
  674. } else if (ret == -ENOENT) {
  675. ret = 0;
  676. }
  677. #endif
  678. return ret;
  679. }
  680. static const struct udevice_id designware_eth_ids[] = {
  681. { .compatible = "allwinner,sun7i-a20-gmac" },
  682. { .compatible = "amlogic,meson6-dwmac" },
  683. { .compatible = "amlogic,meson-gx-dwmac" },
  684. { .compatible = "amlogic,meson-gxbb-dwmac" },
  685. { .compatible = "amlogic,meson-axg-dwmac" },
  686. { .compatible = "st,stm32-dwmac" },
  687. { .compatible = "snps,arc-dwmac-3.70a" },
  688. { }
  689. };
  690. U_BOOT_DRIVER(eth_designware) = {
  691. .name = "eth_designware",
  692. .id = UCLASS_ETH,
  693. .of_match = designware_eth_ids,
  694. .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
  695. .bind = designware_eth_bind,
  696. .probe = designware_eth_probe,
  697. .remove = designware_eth_remove,
  698. .ops = &designware_eth_ops,
  699. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  700. .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
  701. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  702. };
  703. static struct pci_device_id supported[] = {
  704. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
  705. { }
  706. };
  707. U_BOOT_PCI_DEVICE(eth_designware, supported);
  708. #endif