sh_mmcif.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MMCIF driver.
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <watchdog.h>
  10. #include <command.h>
  11. #include <mmc.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <malloc.h>
  15. #include <linux/errno.h>
  16. #include <linux/compat.h>
  17. #include <linux/io.h>
  18. #include <linux/sizes.h>
  19. #include "sh_mmcif.h"
  20. #define DRIVER_NAME "sh_mmcif"
  21. static int sh_mmcif_intr(void *dev_id)
  22. {
  23. struct sh_mmcif_host *host = dev_id;
  24. u32 state = 0;
  25. state = sh_mmcif_read(&host->regs->ce_int);
  26. state &= sh_mmcif_read(&host->regs->ce_int_mask);
  27. if (state & INT_RBSYE) {
  28. sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
  29. sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
  30. goto end;
  31. } else if (state & INT_CRSPE) {
  32. sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
  33. sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
  34. /* one more interrupt (INT_RBSYE) */
  35. if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
  36. return -EAGAIN;
  37. goto end;
  38. } else if (state & INT_BUFREN) {
  39. sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
  40. sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
  41. goto end;
  42. } else if (state & INT_BUFWEN) {
  43. sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
  44. sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
  45. goto end;
  46. } else if (state & INT_CMD12DRE) {
  47. sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
  48. INT_BUFRE), &host->regs->ce_int);
  49. sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
  50. goto end;
  51. } else if (state & INT_BUFRE) {
  52. sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
  53. sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
  54. goto end;
  55. } else if (state & INT_DTRANE) {
  56. sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
  57. sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
  58. goto end;
  59. } else if (state & INT_CMD12RBE) {
  60. sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
  61. &host->regs->ce_int);
  62. sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
  63. goto end;
  64. } else if (state & INT_ERR_STS) {
  65. /* err interrupts */
  66. sh_mmcif_write(~state, &host->regs->ce_int);
  67. sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
  68. goto err;
  69. } else
  70. return -EAGAIN;
  71. err:
  72. host->sd_error = 1;
  73. debug("%s: int err state = %08x\n", DRIVER_NAME, state);
  74. end:
  75. host->wait_int = 1;
  76. return 0;
  77. }
  78. static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
  79. {
  80. int timeout = 10000000;
  81. while (1) {
  82. timeout--;
  83. if (timeout < 0) {
  84. printf("timeout\n");
  85. return 0;
  86. }
  87. if (!sh_mmcif_intr(host))
  88. break;
  89. udelay(1); /* 1 usec */
  90. }
  91. return 1; /* Return value: NOT 0 = complete waiting */
  92. }
  93. static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
  94. {
  95. sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  96. sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
  97. if (!clk)
  98. return;
  99. if (clk == CLKDEV_EMMC_DATA)
  100. sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
  101. else
  102. sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
  103. clk) - 1) - 1) << 16,
  104. &host->regs->ce_clk_ctrl);
  105. sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  106. }
  107. static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
  108. {
  109. u32 tmp;
  110. tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
  111. CLK_CLEAR);
  112. sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
  113. sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
  114. sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
  115. &host->regs->ce_clk_ctrl);
  116. /* byte swap on */
  117. sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
  118. }
  119. static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
  120. {
  121. u32 state1, state2;
  122. int ret, timeout = 10000000;
  123. host->sd_error = 0;
  124. host->wait_int = 0;
  125. state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
  126. state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
  127. debug("%s: ERR HOST_STS1 = %08x\n", \
  128. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
  129. debug("%s: ERR HOST_STS2 = %08x\n", \
  130. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
  131. if (state1 & STS1_CMDSEQ) {
  132. debug("%s: Forced end of command sequence\n", DRIVER_NAME);
  133. sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  134. sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  135. while (1) {
  136. timeout--;
  137. if (timeout < 0) {
  138. printf(DRIVER_NAME": Forceed end of " \
  139. "command sequence timeout err\n");
  140. return -EILSEQ;
  141. }
  142. if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
  143. & STS1_CMDSEQ))
  144. break;
  145. }
  146. sh_mmcif_sync_reset(host);
  147. return -EILSEQ;
  148. }
  149. if (state2 & STS2_CRC_ERR)
  150. ret = -EILSEQ;
  151. else if (state2 & STS2_TIMEOUT_ERR)
  152. ret = -ETIMEDOUT;
  153. else
  154. ret = -EILSEQ;
  155. return ret;
  156. }
  157. static int sh_mmcif_single_read(struct sh_mmcif_host *host,
  158. struct mmc_data *data)
  159. {
  160. long time;
  161. u32 blocksize, i;
  162. unsigned long *p = (unsigned long *)data->dest;
  163. if ((unsigned long)p & 0x00000001) {
  164. printf("%s: The data pointer is unaligned.", __func__);
  165. return -EIO;
  166. }
  167. host->wait_int = 0;
  168. /* buf read enable */
  169. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  170. time = mmcif_wait_interrupt_flag(host);
  171. if (time == 0 || host->sd_error != 0)
  172. return sh_mmcif_error_manage(host);
  173. host->wait_int = 0;
  174. blocksize = (BLOCK_SIZE_MASK &
  175. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  176. for (i = 0; i < blocksize / 4; i++)
  177. *p++ = sh_mmcif_read(&host->regs->ce_data);
  178. /* buffer read end */
  179. sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
  180. time = mmcif_wait_interrupt_flag(host);
  181. if (time == 0 || host->sd_error != 0)
  182. return sh_mmcif_error_manage(host);
  183. host->wait_int = 0;
  184. return 0;
  185. }
  186. static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
  187. struct mmc_data *data)
  188. {
  189. long time;
  190. u32 blocksize, i, j;
  191. unsigned long *p = (unsigned long *)data->dest;
  192. if ((unsigned long)p & 0x00000001) {
  193. printf("%s: The data pointer is unaligned.", __func__);
  194. return -EIO;
  195. }
  196. host->wait_int = 0;
  197. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  198. for (j = 0; j < data->blocks; j++) {
  199. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  200. time = mmcif_wait_interrupt_flag(host);
  201. if (time == 0 || host->sd_error != 0)
  202. return sh_mmcif_error_manage(host);
  203. host->wait_int = 0;
  204. for (i = 0; i < blocksize / 4; i++)
  205. *p++ = sh_mmcif_read(&host->regs->ce_data);
  206. WATCHDOG_RESET();
  207. }
  208. return 0;
  209. }
  210. static int sh_mmcif_single_write(struct sh_mmcif_host *host,
  211. struct mmc_data *data)
  212. {
  213. long time;
  214. u32 blocksize, i;
  215. const unsigned long *p = (unsigned long *)data->dest;
  216. if ((unsigned long)p & 0x00000001) {
  217. printf("%s: The data pointer is unaligned.", __func__);
  218. return -EIO;
  219. }
  220. host->wait_int = 0;
  221. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  222. time = mmcif_wait_interrupt_flag(host);
  223. if (time == 0 || host->sd_error != 0)
  224. return sh_mmcif_error_manage(host);
  225. host->wait_int = 0;
  226. blocksize = (BLOCK_SIZE_MASK &
  227. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  228. for (i = 0; i < blocksize / 4; i++)
  229. sh_mmcif_write(*p++, &host->regs->ce_data);
  230. /* buffer write end */
  231. sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
  232. time = mmcif_wait_interrupt_flag(host);
  233. if (time == 0 || host->sd_error != 0)
  234. return sh_mmcif_error_manage(host);
  235. host->wait_int = 0;
  236. return 0;
  237. }
  238. static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
  239. struct mmc_data *data)
  240. {
  241. long time;
  242. u32 i, j, blocksize;
  243. const unsigned long *p = (unsigned long *)data->dest;
  244. if ((unsigned long)p & 0x00000001) {
  245. printf("%s: The data pointer is unaligned.", __func__);
  246. return -EIO;
  247. }
  248. host->wait_int = 0;
  249. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  250. for (j = 0; j < data->blocks; j++) {
  251. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  252. time = mmcif_wait_interrupt_flag(host);
  253. if (time == 0 || host->sd_error != 0)
  254. return sh_mmcif_error_manage(host);
  255. host->wait_int = 0;
  256. for (i = 0; i < blocksize / 4; i++)
  257. sh_mmcif_write(*p++, &host->regs->ce_data);
  258. WATCHDOG_RESET();
  259. }
  260. return 0;
  261. }
  262. static void sh_mmcif_get_response(struct sh_mmcif_host *host,
  263. struct mmc_cmd *cmd)
  264. {
  265. if (cmd->resp_type & MMC_RSP_136) {
  266. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
  267. cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
  268. cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
  269. cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
  270. debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
  271. cmd->response[1], cmd->response[2], cmd->response[3]);
  272. } else {
  273. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
  274. }
  275. }
  276. static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
  277. struct mmc_cmd *cmd)
  278. {
  279. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
  280. }
  281. static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
  282. struct mmc_data *data, struct mmc_cmd *cmd)
  283. {
  284. u32 tmp = 0;
  285. u32 opc = cmd->cmdidx;
  286. /* Response Type check */
  287. switch (cmd->resp_type) {
  288. case MMC_RSP_NONE:
  289. tmp |= CMD_SET_RTYP_NO;
  290. break;
  291. case MMC_RSP_R1:
  292. case MMC_RSP_R1b:
  293. case MMC_RSP_R3:
  294. tmp |= CMD_SET_RTYP_6B;
  295. break;
  296. case MMC_RSP_R2:
  297. tmp |= CMD_SET_RTYP_17B;
  298. break;
  299. default:
  300. printf(DRIVER_NAME": Not support type response.\n");
  301. break;
  302. }
  303. /* RBSY */
  304. if (opc == MMC_CMD_SWITCH)
  305. tmp |= CMD_SET_RBSY;
  306. /* WDAT / DATW */
  307. if (host->data) {
  308. tmp |= CMD_SET_WDAT;
  309. switch (host->bus_width) {
  310. case MMC_BUS_WIDTH_1:
  311. tmp |= CMD_SET_DATW_1;
  312. break;
  313. case MMC_BUS_WIDTH_4:
  314. tmp |= CMD_SET_DATW_4;
  315. break;
  316. case MMC_BUS_WIDTH_8:
  317. tmp |= CMD_SET_DATW_8;
  318. break;
  319. default:
  320. printf(DRIVER_NAME": Not support bus width.\n");
  321. break;
  322. }
  323. }
  324. /* DWEN */
  325. if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
  326. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
  327. tmp |= CMD_SET_DWEN;
  328. /* CMLTE/CMD12EN */
  329. if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
  330. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
  331. tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
  332. sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
  333. }
  334. /* RIDXC[1:0] check bits */
  335. if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
  336. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  337. tmp |= CMD_SET_RIDXC_BITS;
  338. /* RCRC7C[1:0] check bits */
  339. if (opc == MMC_CMD_SEND_OP_COND)
  340. tmp |= CMD_SET_CRC7C_BITS;
  341. /* RCRC7C[1:0] internal CRC7 */
  342. if (opc == MMC_CMD_ALL_SEND_CID ||
  343. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  344. tmp |= CMD_SET_CRC7C_INTERNAL;
  345. return opc = ((opc << 24) | tmp);
  346. }
  347. static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
  348. struct mmc_data *data, u16 opc)
  349. {
  350. u32 ret;
  351. switch (opc) {
  352. case MMC_CMD_READ_MULTIPLE_BLOCK:
  353. ret = sh_mmcif_multi_read(host, data);
  354. break;
  355. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  356. ret = sh_mmcif_multi_write(host, data);
  357. break;
  358. case MMC_CMD_WRITE_SINGLE_BLOCK:
  359. ret = sh_mmcif_single_write(host, data);
  360. break;
  361. case MMC_CMD_READ_SINGLE_BLOCK:
  362. case MMC_CMD_SEND_EXT_CSD:
  363. ret = sh_mmcif_single_read(host, data);
  364. break;
  365. default:
  366. printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
  367. ret = -EINVAL;
  368. break;
  369. }
  370. return ret;
  371. }
  372. static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
  373. struct mmc_data *data, struct mmc_cmd *cmd)
  374. {
  375. long time;
  376. int ret = 0, mask = 0;
  377. u32 opc = cmd->cmdidx;
  378. if (opc == MMC_CMD_STOP_TRANSMISSION) {
  379. /* MMCIF sends the STOP command automatically */
  380. if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
  381. sh_mmcif_bitset(MASK_MCMD12DRE,
  382. &host->regs->ce_int_mask);
  383. else
  384. sh_mmcif_bitset(MASK_MCMD12RBE,
  385. &host->regs->ce_int_mask);
  386. time = mmcif_wait_interrupt_flag(host);
  387. if (time == 0 || host->sd_error != 0)
  388. return sh_mmcif_error_manage(host);
  389. sh_mmcif_get_cmd12response(host, cmd);
  390. return 0;
  391. }
  392. if (opc == MMC_CMD_SWITCH)
  393. mask = MASK_MRBSYE;
  394. else
  395. mask = MASK_MCRSPE;
  396. mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
  397. MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
  398. MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
  399. MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
  400. if (host->data) {
  401. sh_mmcif_write(0, &host->regs->ce_block_set);
  402. sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
  403. }
  404. opc = sh_mmcif_set_cmd(host, data, cmd);
  405. sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
  406. sh_mmcif_write(mask, &host->regs->ce_int_mask);
  407. debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
  408. /* set arg */
  409. sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
  410. host->wait_int = 0;
  411. /* set cmd */
  412. sh_mmcif_write(opc, &host->regs->ce_cmd_set);
  413. time = mmcif_wait_interrupt_flag(host);
  414. if (time == 0)
  415. return sh_mmcif_error_manage(host);
  416. if (host->sd_error) {
  417. switch (cmd->cmdidx) {
  418. case MMC_CMD_ALL_SEND_CID:
  419. case MMC_CMD_SELECT_CARD:
  420. case MMC_CMD_APP_CMD:
  421. ret = -ETIMEDOUT;
  422. break;
  423. default:
  424. printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
  425. ret = sh_mmcif_error_manage(host);
  426. break;
  427. }
  428. host->sd_error = 0;
  429. host->wait_int = 0;
  430. return ret;
  431. }
  432. /* if no response */
  433. if (!(opc & 0x00C00000))
  434. return 0;
  435. if (host->wait_int == 1) {
  436. sh_mmcif_get_response(host, cmd);
  437. host->wait_int = 0;
  438. }
  439. if (host->data)
  440. ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
  441. host->last_cmd = cmd->cmdidx;
  442. return ret;
  443. }
  444. static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
  445. struct mmc_cmd *cmd, struct mmc_data *data)
  446. {
  447. int ret;
  448. WATCHDOG_RESET();
  449. switch (cmd->cmdidx) {
  450. case MMC_CMD_APP_CMD:
  451. return -ETIMEDOUT;
  452. case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
  453. if (data)
  454. /* ext_csd */
  455. break;
  456. else
  457. /* send_if_cond cmd (not support) */
  458. return -ETIMEDOUT;
  459. default:
  460. break;
  461. }
  462. host->sd_error = 0;
  463. host->data = data;
  464. ret = sh_mmcif_start_cmd(host, data, cmd);
  465. host->data = NULL;
  466. return ret;
  467. }
  468. static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
  469. {
  470. if (mmc->clock)
  471. sh_mmcif_clock_control(host, mmc->clock);
  472. if (mmc->bus_width == 8)
  473. host->bus_width = MMC_BUS_WIDTH_8;
  474. else if (mmc->bus_width == 4)
  475. host->bus_width = MMC_BUS_WIDTH_4;
  476. else
  477. host->bus_width = MMC_BUS_WIDTH_1;
  478. debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
  479. return 0;
  480. }
  481. static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
  482. {
  483. sh_mmcif_sync_reset(host);
  484. sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
  485. return 0;
  486. }
  487. #ifndef CONFIG_DM_MMC
  488. static void *mmc_priv(struct mmc *mmc)
  489. {
  490. return (void *)mmc->priv;
  491. }
  492. static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  493. struct mmc_data *data)
  494. {
  495. struct sh_mmcif_host *host = mmc_priv(mmc);
  496. return sh_mmcif_send_cmd_common(host, cmd, data);
  497. }
  498. static int sh_mmcif_set_ios(struct mmc *mmc)
  499. {
  500. struct sh_mmcif_host *host = mmc_priv(mmc);
  501. return sh_mmcif_set_ios_common(host, mmc);
  502. }
  503. static int sh_mmcif_initialize(struct mmc *mmc)
  504. {
  505. struct sh_mmcif_host *host = mmc_priv(mmc);
  506. return sh_mmcif_initialize_common(host);
  507. }
  508. static const struct mmc_ops sh_mmcif_ops = {
  509. .send_cmd = sh_mmcif_send_cmd,
  510. .set_ios = sh_mmcif_set_ios,
  511. .init = sh_mmcif_initialize,
  512. };
  513. static struct mmc_config sh_mmcif_cfg = {
  514. .name = DRIVER_NAME,
  515. .ops = &sh_mmcif_ops,
  516. .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
  517. MMC_MODE_8BIT,
  518. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  519. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  520. };
  521. int mmcif_mmc_init(void)
  522. {
  523. struct mmc *mmc;
  524. struct sh_mmcif_host *host = NULL;
  525. host = malloc(sizeof(struct sh_mmcif_host));
  526. if (!host)
  527. return -ENOMEM;
  528. memset(host, 0, sizeof(*host));
  529. host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
  530. host->clk = CONFIG_SH_MMCIF_CLK;
  531. sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  532. sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  533. mmc = mmc_create(&sh_mmcif_cfg, host);
  534. if (mmc == NULL) {
  535. free(host);
  536. return -ENOMEM;
  537. }
  538. return 0;
  539. }
  540. #else
  541. struct sh_mmcif_plat {
  542. struct mmc_config cfg;
  543. struct mmc mmc;
  544. };
  545. int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  546. struct mmc_data *data)
  547. {
  548. struct sh_mmcif_host *host = dev_get_priv(dev);
  549. return sh_mmcif_send_cmd_common(host, cmd, data);
  550. }
  551. int sh_mmcif_dm_set_ios(struct udevice *dev)
  552. {
  553. struct sh_mmcif_host *host = dev_get_priv(dev);
  554. struct mmc *mmc = mmc_get_mmc_dev(dev);
  555. return sh_mmcif_set_ios_common(host, mmc);
  556. }
  557. static const struct dm_mmc_ops sh_mmcif_dm_ops = {
  558. .send_cmd = sh_mmcif_dm_send_cmd,
  559. .set_ios = sh_mmcif_dm_set_ios,
  560. };
  561. static int sh_mmcif_dm_bind(struct udevice *dev)
  562. {
  563. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  564. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  565. }
  566. static int sh_mmcif_dm_probe(struct udevice *dev)
  567. {
  568. struct sh_mmcif_plat *plat = dev_get_platdata(dev);
  569. struct sh_mmcif_host *host = dev_get_priv(dev);
  570. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  571. struct clk sh_mmcif_clk;
  572. fdt_addr_t base;
  573. int ret;
  574. base = devfdt_get_addr(dev);
  575. if (base == FDT_ADDR_T_NONE)
  576. return -EINVAL;
  577. host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
  578. if (!host->regs)
  579. return -ENOMEM;
  580. ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
  581. if (ret) {
  582. debug("failed to get clock, ret=%d\n", ret);
  583. return ret;
  584. }
  585. ret = clk_enable(&sh_mmcif_clk);
  586. if (ret) {
  587. debug("failed to enable clock, ret=%d\n", ret);
  588. return ret;
  589. }
  590. host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
  591. plat->cfg.name = dev->name;
  592. plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  593. switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
  594. 1)) {
  595. case 8:
  596. plat->cfg.host_caps |= MMC_MODE_8BIT;
  597. break;
  598. case 4:
  599. plat->cfg.host_caps |= MMC_MODE_4BIT;
  600. break;
  601. case 1:
  602. break;
  603. default:
  604. dev_err(dev, "Invalid \"bus-width\" value\n");
  605. return -EINVAL;
  606. }
  607. sh_mmcif_initialize_common(host);
  608. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  609. plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  610. plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  611. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  612. upriv->mmc = &plat->mmc;
  613. return 0;
  614. }
  615. static const struct udevice_id sh_mmcif_sd_match[] = {
  616. { .compatible = "renesas,sh-mmcif" },
  617. { /* sentinel */ }
  618. };
  619. U_BOOT_DRIVER(sh_mmcif_mmc) = {
  620. .name = "sh-mmcif",
  621. .id = UCLASS_MMC,
  622. .of_match = sh_mmcif_sd_match,
  623. .bind = sh_mmcif_dm_bind,
  624. .probe = sh_mmcif_dm_probe,
  625. .priv_auto_alloc_size = sizeof(struct sh_mmcif_host),
  626. .platdata_auto_alloc_size = sizeof(struct sh_mmcif_plat),
  627. .ops = &sh_mmcif_dm_ops,
  628. };
  629. #endif