mxs_gpio.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 GPIO control code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/imx-regs.h>
  13. #if defined(CONFIG_MX23)
  14. #define PINCTRL_BANKS 3
  15. #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
  16. #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
  17. #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
  18. #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
  19. #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
  20. #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
  21. #elif defined(CONFIG_MX28)
  22. #define PINCTRL_BANKS 5
  23. #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
  24. #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
  25. #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
  26. #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
  27. #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
  28. #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
  29. #else
  30. #error "Please select CONFIG_MX23 or CONFIG_MX28"
  31. #endif
  32. #define GPIO_INT_FALL_EDGE 0x0
  33. #define GPIO_INT_LOW_LEV 0x1
  34. #define GPIO_INT_RISE_EDGE 0x2
  35. #define GPIO_INT_HIGH_LEV 0x3
  36. #define GPIO_INT_LEV_MASK (1 << 0)
  37. #define GPIO_INT_POL_MASK (1 << 1)
  38. void mxs_gpio_init(void)
  39. {
  40. int i;
  41. for (i = 0; i < PINCTRL_BANKS; i++) {
  42. writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
  43. writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
  44. /* Use SCT address here to clear the IRQSTAT bits */
  45. writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
  46. }
  47. }
  48. #if !CONFIG_IS_ENABLED(DM_GPIO)
  49. int gpio_get_value(unsigned gpio)
  50. {
  51. uint32_t bank = PAD_BANK(gpio);
  52. uint32_t offset = PINCTRL_DIN(bank);
  53. struct mxs_register_32 *reg =
  54. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  55. return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
  56. }
  57. void gpio_set_value(unsigned gpio, int value)
  58. {
  59. uint32_t bank = PAD_BANK(gpio);
  60. uint32_t offset = PINCTRL_DOUT(bank);
  61. struct mxs_register_32 *reg =
  62. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  63. if (value)
  64. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  65. else
  66. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  67. }
  68. int gpio_direction_input(unsigned gpio)
  69. {
  70. uint32_t bank = PAD_BANK(gpio);
  71. uint32_t offset = PINCTRL_DOE(bank);
  72. struct mxs_register_32 *reg =
  73. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  74. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  75. return 0;
  76. }
  77. int gpio_direction_output(unsigned gpio, int value)
  78. {
  79. uint32_t bank = PAD_BANK(gpio);
  80. uint32_t offset = PINCTRL_DOE(bank);
  81. struct mxs_register_32 *reg =
  82. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  83. gpio_set_value(gpio, value);
  84. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  85. return 0;
  86. }
  87. int gpio_request(unsigned gpio, const char *label)
  88. {
  89. if (PAD_BANK(gpio) >= PINCTRL_BANKS)
  90. return -1;
  91. return 0;
  92. }
  93. int gpio_free(unsigned gpio)
  94. {
  95. return 0;
  96. }
  97. int name_to_gpio(const char *name)
  98. {
  99. unsigned bank, pin;
  100. char *end;
  101. bank = simple_strtoul(name, &end, 10);
  102. if (!*end || *end != ':')
  103. return bank;
  104. pin = simple_strtoul(end + 1, NULL, 10);
  105. return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
  106. }
  107. #else /* DM_GPIO */
  108. #include <dm.h>
  109. #include <asm/gpio.h>
  110. #include <dt-structs.h>
  111. #include <asm/arch/gpio.h>
  112. #define MXS_MAX_GPIO_PER_BANK 32
  113. #ifdef CONFIG_MX28
  114. #define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio
  115. #else /* CONFIG_MX23 */
  116. #define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio
  117. #endif
  118. DECLARE_GLOBAL_DATA_PTR;
  119. /*
  120. * According to i.MX28 Reference Manual:
  121. * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
  122. * The i.MX28 has following number of GPIOs available:
  123. * Bank 0: 0-28 -> 29 PINS
  124. * Bank 1: 0-31 -> 32 PINS
  125. * Bank 2: 0-27 -> 28 PINS
  126. * Bank 3: 0-30 -> 31 PINS
  127. * Bank 4: 0-20 -> 21 PINS
  128. */
  129. struct mxs_gpio_platdata {
  130. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  131. struct dtd_fsl_imx_gpio dtplat;
  132. #endif
  133. unsigned int bank;
  134. int gpio_ranges;
  135. };
  136. struct mxs_gpio_priv {
  137. unsigned int bank;
  138. };
  139. static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
  140. {
  141. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  142. struct mxs_register_32 *reg =
  143. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  144. PINCTRL_DIN(priv->bank));
  145. return (readl(&reg->reg) >> offset) & 1;
  146. }
  147. static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
  148. int value)
  149. {
  150. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  151. struct mxs_register_32 *reg =
  152. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  153. PINCTRL_DOUT(priv->bank));
  154. if (value)
  155. writel(BIT(offset), &reg->reg_set);
  156. else
  157. writel(BIT(offset), &reg->reg_clr);
  158. return 0;
  159. }
  160. static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
  161. {
  162. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  163. struct mxs_register_32 *reg =
  164. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  165. PINCTRL_DOE(priv->bank));
  166. writel(BIT(offset), &reg->reg_clr);
  167. return 0;
  168. }
  169. static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
  170. int value)
  171. {
  172. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  173. struct mxs_register_32 *reg =
  174. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  175. PINCTRL_DOE(priv->bank));
  176. mxs_gpio_set_value(dev, offset, value);
  177. writel(BIT(offset), &reg->reg_set);
  178. return 0;
  179. }
  180. static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
  181. {
  182. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  183. struct mxs_register_32 *reg =
  184. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  185. PINCTRL_DOE(priv->bank));
  186. bool is_output = !!(readl(&reg->reg) >> offset);
  187. return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
  188. }
  189. static const struct dm_gpio_ops gpio_mxs_ops = {
  190. .direction_input = mxs_gpio_direction_input,
  191. .direction_output = mxs_gpio_direction_output,
  192. .get_value = mxs_gpio_get_value,
  193. .set_value = mxs_gpio_set_value,
  194. .get_function = mxs_gpio_get_function,
  195. };
  196. static int mxs_gpio_probe(struct udevice *dev)
  197. {
  198. struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
  199. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  200. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  201. char name[16], *str;
  202. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  203. struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat;
  204. priv->bank = (unsigned int)dtplat->reg[0];
  205. uc_priv->gpio_count = dtplat->gpio_ranges[3];
  206. #else
  207. priv->bank = (unsigned int)plat->bank;
  208. uc_priv->gpio_count = plat->gpio_ranges;
  209. #endif
  210. snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
  211. str = strdup(name);
  212. if (!str)
  213. return -ENOMEM;
  214. uc_priv->bank_name = str;
  215. debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
  216. uc_priv->gpio_count, priv->bank);
  217. return 0;
  218. }
  219. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  220. static int mxs_ofdata_to_platdata(struct udevice *dev)
  221. {
  222. struct mxs_gpio_platdata *plat = dev->platdata;
  223. struct fdtdec_phandle_args args;
  224. int node = dev_of_offset(dev);
  225. int ret;
  226. plat->bank = devfdt_get_addr(dev);
  227. if (plat->bank == FDT_ADDR_T_NONE) {
  228. printf("%s: No 'reg' property defined!\n", __func__);
  229. return -EINVAL;
  230. }
  231. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
  232. NULL, 3, 0, &args);
  233. if (ret)
  234. printf("%s: 'gpio-ranges' not defined - using default!\n",
  235. __func__);
  236. plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
  237. return 0;
  238. }
  239. static const struct udevice_id mxs_gpio_ids[] = {
  240. { .compatible = "fsl,imx23-gpio" },
  241. { .compatible = "fsl,imx28-gpio" },
  242. { }
  243. };
  244. #endif
  245. U_BOOT_DRIVER(gpio_mxs) = {
  246. #ifdef CONFIG_MX28
  247. .name = "fsl_imx28_gpio",
  248. #else /* CONFIG_MX23 */
  249. .name = "fsl_imx23_gpio",
  250. #endif
  251. .id = UCLASS_GPIO,
  252. .ops = &gpio_mxs_ops,
  253. .probe = mxs_gpio_probe,
  254. .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
  255. .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
  256. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  257. .of_match = mxs_gpio_ids,
  258. .ofdata_to_platdata = mxs_ofdata_to_platdata,
  259. #endif
  260. };
  261. #endif /* DM_GPIO */