mxc_gpio.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. *
  6. * Copyright (C) 2011
  7. * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. enum mxc_gpio_direction {
  17. MXC_GPIO_DIRECTION_IN,
  18. MXC_GPIO_DIRECTION_OUT,
  19. };
  20. #define GPIO_PER_BANK 32
  21. struct mxc_gpio_plat {
  22. int bank_index;
  23. struct gpio_regs *regs;
  24. };
  25. struct mxc_bank_info {
  26. struct gpio_regs *regs;
  27. };
  28. #if !CONFIG_IS_ENABLED(DM_GPIO)
  29. #define GPIO_TO_PORT(n) ((n) / 32)
  30. /* GPIO port description */
  31. static unsigned long gpio_ports[] = {
  32. [0] = GPIO1_BASE_ADDR,
  33. [1] = GPIO2_BASE_ADDR,
  34. [2] = GPIO3_BASE_ADDR,
  35. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  36. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  37. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  38. defined(CONFIG_ARCH_IMX8)
  39. [3] = GPIO4_BASE_ADDR,
  40. #endif
  41. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  42. defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
  43. defined(CONFIG_ARCH_IMX8)
  44. [4] = GPIO5_BASE_ADDR,
  45. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
  46. [5] = GPIO6_BASE_ADDR,
  47. #endif
  48. #endif
  49. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
  50. defined(CONFIG_ARCH_IMX8)
  51. #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
  52. [6] = GPIO7_BASE_ADDR,
  53. #endif
  54. #endif
  55. #if defined(CONFIG_ARCH_IMX8)
  56. [7] = GPIO8_BASE_ADDR,
  57. #endif
  58. };
  59. static int mxc_gpio_direction(unsigned int gpio,
  60. enum mxc_gpio_direction direction)
  61. {
  62. unsigned int port = GPIO_TO_PORT(gpio);
  63. struct gpio_regs *regs;
  64. u32 l;
  65. if (port >= ARRAY_SIZE(gpio_ports))
  66. return -1;
  67. gpio &= 0x1f;
  68. regs = (struct gpio_regs *)gpio_ports[port];
  69. l = readl(&regs->gpio_dir);
  70. switch (direction) {
  71. case MXC_GPIO_DIRECTION_OUT:
  72. l |= 1 << gpio;
  73. break;
  74. case MXC_GPIO_DIRECTION_IN:
  75. l &= ~(1 << gpio);
  76. }
  77. writel(l, &regs->gpio_dir);
  78. return 0;
  79. }
  80. int gpio_set_value(unsigned gpio, int value)
  81. {
  82. unsigned int port = GPIO_TO_PORT(gpio);
  83. struct gpio_regs *regs;
  84. u32 l;
  85. if (port >= ARRAY_SIZE(gpio_ports))
  86. return -1;
  87. gpio &= 0x1f;
  88. regs = (struct gpio_regs *)gpio_ports[port];
  89. l = readl(&regs->gpio_dr);
  90. if (value)
  91. l |= 1 << gpio;
  92. else
  93. l &= ~(1 << gpio);
  94. writel(l, &regs->gpio_dr);
  95. return 0;
  96. }
  97. int gpio_get_value(unsigned gpio)
  98. {
  99. unsigned int port = GPIO_TO_PORT(gpio);
  100. struct gpio_regs *regs;
  101. u32 val;
  102. if (port >= ARRAY_SIZE(gpio_ports))
  103. return -1;
  104. gpio &= 0x1f;
  105. regs = (struct gpio_regs *)gpio_ports[port];
  106. val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
  107. return val;
  108. }
  109. int gpio_request(unsigned gpio, const char *label)
  110. {
  111. unsigned int port = GPIO_TO_PORT(gpio);
  112. if (port >= ARRAY_SIZE(gpio_ports))
  113. return -1;
  114. return 0;
  115. }
  116. int gpio_free(unsigned gpio)
  117. {
  118. return 0;
  119. }
  120. int gpio_direction_input(unsigned gpio)
  121. {
  122. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_IN);
  123. }
  124. int gpio_direction_output(unsigned gpio, int value)
  125. {
  126. int ret = gpio_set_value(gpio, value);
  127. if (ret < 0)
  128. return ret;
  129. return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
  130. }
  131. #endif
  132. #if CONFIG_IS_ENABLED(DM_GPIO)
  133. #include <fdtdec.h>
  134. static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  135. {
  136. u32 val;
  137. val = readl(&regs->gpio_dir);
  138. return val & (1 << offset) ? 1 : 0;
  139. }
  140. static void mxc_gpio_bank_direction(struct gpio_regs *regs, int offset,
  141. enum mxc_gpio_direction direction)
  142. {
  143. u32 l;
  144. l = readl(&regs->gpio_dir);
  145. switch (direction) {
  146. case MXC_GPIO_DIRECTION_OUT:
  147. l |= 1 << offset;
  148. break;
  149. case MXC_GPIO_DIRECTION_IN:
  150. l &= ~(1 << offset);
  151. }
  152. writel(l, &regs->gpio_dir);
  153. }
  154. static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
  155. int value)
  156. {
  157. u32 l;
  158. l = readl(&regs->gpio_dr);
  159. if (value)
  160. l |= 1 << offset;
  161. else
  162. l &= ~(1 << offset);
  163. writel(l, &regs->gpio_dr);
  164. }
  165. static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
  166. {
  167. return (readl(&regs->gpio_psr) >> offset) & 0x01;
  168. }
  169. /* set GPIO pin 'gpio' as an input */
  170. static int mxc_gpio_direction_input(struct udevice *dev, unsigned offset)
  171. {
  172. struct mxc_bank_info *bank = dev_get_priv(dev);
  173. /* Configure GPIO direction as input. */
  174. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_IN);
  175. return 0;
  176. }
  177. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  178. static int mxc_gpio_direction_output(struct udevice *dev, unsigned offset,
  179. int value)
  180. {
  181. struct mxc_bank_info *bank = dev_get_priv(dev);
  182. /* Configure GPIO output value. */
  183. mxc_gpio_bank_set_value(bank->regs, offset, value);
  184. /* Configure GPIO direction as output. */
  185. mxc_gpio_bank_direction(bank->regs, offset, MXC_GPIO_DIRECTION_OUT);
  186. return 0;
  187. }
  188. /* read GPIO IN value of pin 'gpio' */
  189. static int mxc_gpio_get_value(struct udevice *dev, unsigned offset)
  190. {
  191. struct mxc_bank_info *bank = dev_get_priv(dev);
  192. return mxc_gpio_bank_get_value(bank->regs, offset);
  193. }
  194. /* write GPIO OUT value to pin 'gpio' */
  195. static int mxc_gpio_set_value(struct udevice *dev, unsigned offset,
  196. int value)
  197. {
  198. struct mxc_bank_info *bank = dev_get_priv(dev);
  199. mxc_gpio_bank_set_value(bank->regs, offset, value);
  200. return 0;
  201. }
  202. static int mxc_gpio_get_function(struct udevice *dev, unsigned offset)
  203. {
  204. struct mxc_bank_info *bank = dev_get_priv(dev);
  205. /* GPIOF_FUNC is not implemented yet */
  206. if (mxc_gpio_is_output(bank->regs, offset))
  207. return GPIOF_OUTPUT;
  208. else
  209. return GPIOF_INPUT;
  210. }
  211. static const struct dm_gpio_ops gpio_mxc_ops = {
  212. .direction_input = mxc_gpio_direction_input,
  213. .direction_output = mxc_gpio_direction_output,
  214. .get_value = mxc_gpio_get_value,
  215. .set_value = mxc_gpio_set_value,
  216. .get_function = mxc_gpio_get_function,
  217. };
  218. static int mxc_gpio_probe(struct udevice *dev)
  219. {
  220. struct mxc_bank_info *bank = dev_get_priv(dev);
  221. struct mxc_gpio_plat *plat = dev_get_platdata(dev);
  222. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  223. int banknum;
  224. char name[18], *str;
  225. banknum = plat->bank_index;
  226. sprintf(name, "GPIO%d_", banknum + 1);
  227. str = strdup(name);
  228. if (!str)
  229. return -ENOMEM;
  230. uc_priv->bank_name = str;
  231. uc_priv->gpio_count = GPIO_PER_BANK;
  232. bank->regs = plat->regs;
  233. return 0;
  234. }
  235. static int mxc_gpio_bind(struct udevice *dev)
  236. {
  237. struct mxc_gpio_plat *plat = dev->platdata;
  238. fdt_addr_t addr;
  239. /*
  240. * If platdata already exsits, directly return.
  241. * Actually only when DT is not supported, platdata
  242. * is statically initialized in U_BOOT_DEVICES.Here
  243. * will return.
  244. */
  245. if (plat)
  246. return 0;
  247. addr = devfdt_get_addr(dev);
  248. if (addr == FDT_ADDR_T_NONE)
  249. return -EINVAL;
  250. /*
  251. * TODO:
  252. * When every board is converted to driver model and DT is supported,
  253. * this can be done by auto-alloc feature, but not using calloc
  254. * to alloc memory for platdata.
  255. *
  256. * For example mxc_plat below uses platform data rather than device
  257. * tree.
  258. *
  259. * NOTE: DO NOT COPY this code if you are using device tree.
  260. */
  261. plat = calloc(1, sizeof(*plat));
  262. if (!plat)
  263. return -ENOMEM;
  264. plat->regs = (struct gpio_regs *)addr;
  265. plat->bank_index = dev->req_seq;
  266. dev->platdata = plat;
  267. return 0;
  268. }
  269. static const struct udevice_id mxc_gpio_ids[] = {
  270. { .compatible = "fsl,imx35-gpio" },
  271. { }
  272. };
  273. U_BOOT_DRIVER(gpio_mxc) = {
  274. .name = "gpio_mxc",
  275. .id = UCLASS_GPIO,
  276. .ops = &gpio_mxc_ops,
  277. .probe = mxc_gpio_probe,
  278. .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
  279. .of_match = mxc_gpio_ids,
  280. .bind = mxc_gpio_bind,
  281. };
  282. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  283. static const struct mxc_gpio_plat mxc_plat[] = {
  284. { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
  285. { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
  286. { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
  287. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  288. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  289. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  290. { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
  291. #endif
  292. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  293. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  294. { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
  295. #ifndef CONFIG_IMX8M
  296. { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
  297. #endif
  298. #endif
  299. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  300. { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
  301. #endif
  302. #if defined(CONFIG_ARCH_IMX8)
  303. { 7, (struct gpio_regs *)GPIO8_BASE_ADDR },
  304. #endif
  305. };
  306. U_BOOT_DEVICES(mxc_gpios) = {
  307. { "gpio_mxc", &mxc_plat[0] },
  308. { "gpio_mxc", &mxc_plat[1] },
  309. { "gpio_mxc", &mxc_plat[2] },
  310. #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
  311. defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  312. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  313. { "gpio_mxc", &mxc_plat[3] },
  314. #endif
  315. #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
  316. defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
  317. { "gpio_mxc", &mxc_plat[4] },
  318. #ifndef CONFIG_IMX8M
  319. { "gpio_mxc", &mxc_plat[5] },
  320. #endif
  321. #endif
  322. #if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8)
  323. { "gpio_mxc", &mxc_plat[6] },
  324. #endif
  325. #if defined(CONFIG_ARCH_IMX8)
  326. { "gpio_mxc", &mxc_plat[7] },
  327. #endif
  328. };
  329. #endif
  330. #endif