at91_gpio.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
  4. *
  5. * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
  6. *
  7. * Copyright (C) 2005 HP Labs
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <asm/io.h>
  14. #include <linux/sizes.h>
  15. #include <asm/gpio.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/at91_pio.h>
  18. #define GPIO_PER_BANK 32
  19. static struct at91_port *at91_pio_get_port(unsigned port)
  20. {
  21. switch (port) {
  22. case AT91_PIO_PORTA:
  23. return (struct at91_port *)ATMEL_BASE_PIOA;
  24. case AT91_PIO_PORTB:
  25. return (struct at91_port *)ATMEL_BASE_PIOB;
  26. case AT91_PIO_PORTC:
  27. return (struct at91_port *)ATMEL_BASE_PIOC;
  28. #if (ATMEL_PIO_PORTS > 3)
  29. case AT91_PIO_PORTD:
  30. return (struct at91_port *)ATMEL_BASE_PIOD;
  31. #if (ATMEL_PIO_PORTS > 4)
  32. case AT91_PIO_PORTE:
  33. return (struct at91_port *)ATMEL_BASE_PIOE;
  34. #endif
  35. #endif
  36. default:
  37. printf("Error: at91_gpio: Fail to get PIO base!\n");
  38. return NULL;
  39. }
  40. }
  41. static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
  42. int use_pullup)
  43. {
  44. u32 mask;
  45. mask = 1 << offset;
  46. if (use_pullup)
  47. writel(mask, &at91_port->puer);
  48. else
  49. writel(mask, &at91_port->pudr);
  50. writel(mask, &at91_port->per);
  51. }
  52. int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  53. {
  54. struct at91_port *at91_port = at91_pio_get_port(port);
  55. if (at91_port && (pin < GPIO_PER_BANK))
  56. at91_set_port_pullup(at91_port, pin, use_pullup);
  57. return 0;
  58. }
  59. /*
  60. * mux the pin to the "GPIO" peripheral role.
  61. */
  62. int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
  63. {
  64. struct at91_port *at91_port = at91_pio_get_port(port);
  65. u32 mask;
  66. if (at91_port && (pin < GPIO_PER_BANK)) {
  67. mask = 1 << pin;
  68. writel(mask, &at91_port->idr);
  69. at91_set_pio_pullup(port, pin, use_pullup);
  70. writel(mask, &at91_port->per);
  71. }
  72. return 0;
  73. }
  74. /*
  75. * mux the pin to the "A" internal peripheral role.
  76. */
  77. int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  78. {
  79. struct at91_port *at91_port = at91_pio_get_port(port);
  80. u32 mask;
  81. if (at91_port && (pin < GPIO_PER_BANK)) {
  82. mask = 1 << pin;
  83. writel(mask, &at91_port->idr);
  84. at91_set_pio_pullup(port, pin, use_pullup);
  85. writel(mask, &at91_port->mux.pio2.asr);
  86. writel(mask, &at91_port->pdr);
  87. }
  88. return 0;
  89. }
  90. /*
  91. * mux the pin to the "B" internal peripheral role.
  92. */
  93. int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  94. {
  95. struct at91_port *at91_port = at91_pio_get_port(port);
  96. u32 mask;
  97. if (at91_port && (pin < GPIO_PER_BANK)) {
  98. mask = 1 << pin;
  99. writel(mask, &at91_port->idr);
  100. at91_set_pio_pullup(port, pin, use_pullup);
  101. writel(mask, &at91_port->mux.pio2.bsr);
  102. writel(mask, &at91_port->pdr);
  103. }
  104. return 0;
  105. }
  106. /*
  107. * mux the pin to the "A" internal peripheral role.
  108. */
  109. int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
  110. {
  111. struct at91_port *at91_port = at91_pio_get_port(port);
  112. u32 mask;
  113. if (at91_port && (pin < GPIO_PER_BANK)) {
  114. mask = 1 << pin;
  115. writel(mask, &at91_port->idr);
  116. at91_set_pio_pullup(port, pin, use_pullup);
  117. writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
  118. &at91_port->mux.pio3.abcdsr1);
  119. writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
  120. &at91_port->mux.pio3.abcdsr2);
  121. writel(mask, &at91_port->pdr);
  122. }
  123. return 0;
  124. }
  125. /*
  126. * mux the pin to the "B" internal peripheral role.
  127. */
  128. int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
  129. {
  130. struct at91_port *at91_port = at91_pio_get_port(port);
  131. u32 mask;
  132. if (at91_port && (pin < GPIO_PER_BANK)) {
  133. mask = 1 << pin;
  134. writel(mask, &at91_port->idr);
  135. at91_set_pio_pullup(port, pin, use_pullup);
  136. writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
  137. &at91_port->mux.pio3.abcdsr1);
  138. writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
  139. &at91_port->mux.pio3.abcdsr2);
  140. writel(mask, &at91_port->pdr);
  141. }
  142. return 0;
  143. }
  144. /*
  145. * mux the pin to the "C" internal peripheral role.
  146. */
  147. int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
  148. {
  149. struct at91_port *at91_port = at91_pio_get_port(port);
  150. u32 mask;
  151. if (at91_port && (pin < GPIO_PER_BANK)) {
  152. mask = 1 << pin;
  153. writel(mask, &at91_port->idr);
  154. at91_set_pio_pullup(port, pin, use_pullup);
  155. writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
  156. &at91_port->mux.pio3.abcdsr1);
  157. writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
  158. &at91_port->mux.pio3.abcdsr2);
  159. writel(mask, &at91_port->pdr);
  160. }
  161. return 0;
  162. }
  163. /*
  164. * mux the pin to the "D" internal peripheral role.
  165. */
  166. int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
  167. {
  168. struct at91_port *at91_port = at91_pio_get_port(port);
  169. u32 mask;
  170. if (at91_port && (pin < GPIO_PER_BANK)) {
  171. mask = 1 << pin;
  172. writel(mask, &at91_port->idr);
  173. at91_set_pio_pullup(port, pin, use_pullup);
  174. writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
  175. &at91_port->mux.pio3.abcdsr1);
  176. writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
  177. &at91_port->mux.pio3.abcdsr2);
  178. writel(mask, &at91_port->pdr);
  179. }
  180. return 0;
  181. }
  182. #if CONFIG_IS_ENABLED(DM_GPIO)
  183. static bool at91_get_port_output(struct at91_port *at91_port, int offset)
  184. {
  185. u32 mask, val;
  186. mask = 1 << offset;
  187. val = readl(&at91_port->osr);
  188. return val & mask;
  189. }
  190. #endif
  191. static void at91_set_port_input(struct at91_port *at91_port, int offset,
  192. int use_pullup)
  193. {
  194. u32 mask;
  195. mask = 1 << offset;
  196. writel(mask, &at91_port->idr);
  197. at91_set_port_pullup(at91_port, offset, use_pullup);
  198. writel(mask, &at91_port->odr);
  199. writel(mask, &at91_port->per);
  200. }
  201. /*
  202. * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
  203. * configure it for an input.
  204. */
  205. int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
  206. {
  207. struct at91_port *at91_port = at91_pio_get_port(port);
  208. if (at91_port && (pin < GPIO_PER_BANK))
  209. at91_set_port_input(at91_port, pin, use_pullup);
  210. return 0;
  211. }
  212. static void at91_set_port_output(struct at91_port *at91_port, int offset,
  213. int value)
  214. {
  215. u32 mask;
  216. mask = 1 << offset;
  217. writel(mask, &at91_port->idr);
  218. writel(mask, &at91_port->pudr);
  219. if (value)
  220. writel(mask, &at91_port->sodr);
  221. else
  222. writel(mask, &at91_port->codr);
  223. writel(mask, &at91_port->oer);
  224. writel(mask, &at91_port->per);
  225. }
  226. /*
  227. * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
  228. * and configure it for an output.
  229. */
  230. int at91_set_pio_output(unsigned port, u32 pin, int value)
  231. {
  232. struct at91_port *at91_port = at91_pio_get_port(port);
  233. if (at91_port && (pin < GPIO_PER_BANK))
  234. at91_set_port_output(at91_port, pin, value);
  235. return 0;
  236. }
  237. /*
  238. * enable/disable the glitch filter. mostly used with IRQ handling.
  239. */
  240. int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  241. {
  242. struct at91_port *at91_port = at91_pio_get_port(port);
  243. u32 mask;
  244. if (at91_port && (pin < GPIO_PER_BANK)) {
  245. mask = 1 << pin;
  246. if (is_on)
  247. writel(mask, &at91_port->ifer);
  248. else
  249. writel(mask, &at91_port->ifdr);
  250. }
  251. return 0;
  252. }
  253. /*
  254. * enable/disable the glitch filter. mostly used with IRQ handling.
  255. */
  256. int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
  257. {
  258. struct at91_port *at91_port = at91_pio_get_port(port);
  259. u32 mask;
  260. if (at91_port && (pin < GPIO_PER_BANK)) {
  261. mask = 1 << pin;
  262. if (is_on) {
  263. writel(mask, &at91_port->mux.pio3.ifscdr);
  264. writel(mask, &at91_port->ifer);
  265. } else {
  266. writel(mask, &at91_port->ifdr);
  267. }
  268. }
  269. return 0;
  270. }
  271. /*
  272. * enable/disable the debounce filter.
  273. */
  274. int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
  275. {
  276. struct at91_port *at91_port = at91_pio_get_port(port);
  277. u32 mask;
  278. if (at91_port && (pin < GPIO_PER_BANK)) {
  279. mask = 1 << pin;
  280. if (is_on) {
  281. writel(mask, &at91_port->mux.pio3.ifscer);
  282. writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
  283. writel(mask, &at91_port->ifer);
  284. } else {
  285. writel(mask, &at91_port->ifdr);
  286. }
  287. }
  288. return 0;
  289. }
  290. /*
  291. * enable/disable the pull-down.
  292. * If pull-up already enabled while calling the function, we disable it.
  293. */
  294. int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
  295. {
  296. struct at91_port *at91_port = at91_pio_get_port(port);
  297. u32 mask;
  298. if (at91_port && (pin < GPIO_PER_BANK)) {
  299. mask = 1 << pin;
  300. if (is_on) {
  301. at91_set_pio_pullup(port, pin, 0);
  302. writel(mask, &at91_port->mux.pio3.ppder);
  303. } else
  304. writel(mask, &at91_port->mux.pio3.ppddr);
  305. }
  306. return 0;
  307. }
  308. int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
  309. {
  310. struct at91_port *at91_port = at91_pio_get_port(port);
  311. if (use_pullup)
  312. at91_pio3_set_pio_pulldown(port, pin, 0);
  313. if (at91_port && (pin < GPIO_PER_BANK))
  314. at91_set_port_pullup(at91_port, pin, use_pullup);
  315. return 0;
  316. }
  317. /*
  318. * disable Schmitt trigger
  319. */
  320. int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
  321. {
  322. struct at91_port *at91_port = at91_pio_get_port(port);
  323. u32 mask;
  324. if (at91_port && (pin < GPIO_PER_BANK)) {
  325. mask = 1 << pin;
  326. writel(readl(&at91_port->schmitt) | mask,
  327. &at91_port->schmitt);
  328. }
  329. return 0;
  330. }
  331. /*
  332. * enable/disable the multi-driver. This is only valid for output and
  333. * allows the output pin to run as an open collector output.
  334. */
  335. int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
  336. {
  337. struct at91_port *at91_port = at91_pio_get_port(port);
  338. u32 mask;
  339. if (at91_port && (pin < GPIO_PER_BANK)) {
  340. mask = 1 << pin;
  341. if (is_on)
  342. writel(mask, &at91_port->mder);
  343. else
  344. writel(mask, &at91_port->mddr);
  345. }
  346. return 0;
  347. }
  348. static void at91_set_port_value(struct at91_port *at91_port, int offset,
  349. int value)
  350. {
  351. u32 mask;
  352. mask = 1 << offset;
  353. if (value)
  354. writel(mask, &at91_port->sodr);
  355. else
  356. writel(mask, &at91_port->codr);
  357. }
  358. /*
  359. * assuming the pin is muxed as a gpio output, set its value.
  360. */
  361. int at91_set_pio_value(unsigned port, unsigned pin, int value)
  362. {
  363. struct at91_port *at91_port = at91_pio_get_port(port);
  364. if (at91_port && (pin < GPIO_PER_BANK))
  365. at91_set_port_value(at91_port, pin, value);
  366. return 0;
  367. }
  368. static int at91_get_port_value(struct at91_port *at91_port, int offset)
  369. {
  370. u32 pdsr = 0, mask;
  371. mask = 1 << offset;
  372. pdsr = readl(&at91_port->pdsr) & mask;
  373. return pdsr != 0;
  374. }
  375. /*
  376. * read the pin's value (works even if it's not muxed as a gpio).
  377. */
  378. int at91_get_pio_value(unsigned port, unsigned pin)
  379. {
  380. struct at91_port *at91_port = at91_pio_get_port(port);
  381. if (at91_port && (pin < GPIO_PER_BANK))
  382. return at91_get_port_value(at91_port, pin);
  383. return 0;
  384. }
  385. #if !CONFIG_IS_ENABLED(DM_GPIO)
  386. /* Common GPIO API */
  387. int gpio_request(unsigned gpio, const char *label)
  388. {
  389. return 0;
  390. }
  391. int gpio_free(unsigned gpio)
  392. {
  393. return 0;
  394. }
  395. int gpio_direction_input(unsigned gpio)
  396. {
  397. at91_set_pio_input(at91_gpio_to_port(gpio),
  398. at91_gpio_to_pin(gpio), 0);
  399. return 0;
  400. }
  401. int gpio_direction_output(unsigned gpio, int value)
  402. {
  403. at91_set_pio_output(at91_gpio_to_port(gpio),
  404. at91_gpio_to_pin(gpio), value);
  405. return 0;
  406. }
  407. int gpio_get_value(unsigned gpio)
  408. {
  409. return at91_get_pio_value(at91_gpio_to_port(gpio),
  410. at91_gpio_to_pin(gpio));
  411. }
  412. int gpio_set_value(unsigned gpio, int value)
  413. {
  414. at91_set_pio_value(at91_gpio_to_port(gpio),
  415. at91_gpio_to_pin(gpio), value);
  416. return 0;
  417. }
  418. #endif
  419. #if CONFIG_IS_ENABLED(DM_GPIO)
  420. struct at91_port_priv {
  421. struct at91_port *regs;
  422. };
  423. /* set GPIO pin 'gpio' as an input */
  424. static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
  425. {
  426. struct at91_port_priv *port = dev_get_priv(dev);
  427. at91_set_port_input(port->regs, offset, 0);
  428. return 0;
  429. }
  430. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  431. static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
  432. int value)
  433. {
  434. struct at91_port_priv *port = dev_get_priv(dev);
  435. at91_set_port_output(port->regs, offset, value);
  436. return 0;
  437. }
  438. /* read GPIO IN value of pin 'gpio' */
  439. static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
  440. {
  441. struct at91_port_priv *port = dev_get_priv(dev);
  442. return at91_get_port_value(port->regs, offset);
  443. }
  444. /* write GPIO OUT value to pin 'gpio' */
  445. static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
  446. int value)
  447. {
  448. struct at91_port_priv *port = dev_get_priv(dev);
  449. at91_set_port_value(port->regs, offset, value);
  450. return 0;
  451. }
  452. static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
  453. {
  454. struct at91_port_priv *port = dev_get_priv(dev);
  455. /* GPIOF_FUNC is not implemented yet */
  456. if (at91_get_port_output(port->regs, offset))
  457. return GPIOF_OUTPUT;
  458. else
  459. return GPIOF_INPUT;
  460. }
  461. static const char *at91_get_bank_name(uint32_t base_addr)
  462. {
  463. switch (base_addr) {
  464. case ATMEL_BASE_PIOA:
  465. return "PIOA";
  466. case ATMEL_BASE_PIOB:
  467. return "PIOB";
  468. case ATMEL_BASE_PIOC:
  469. return "PIOC";
  470. #if (ATMEL_PIO_PORTS > 3)
  471. case ATMEL_BASE_PIOD:
  472. return "PIOD";
  473. #if (ATMEL_PIO_PORTS > 4)
  474. case ATMEL_BASE_PIOE:
  475. return "PIOE";
  476. #endif
  477. #endif
  478. }
  479. return "undefined";
  480. }
  481. static const struct dm_gpio_ops gpio_at91_ops = {
  482. .direction_input = at91_gpio_direction_input,
  483. .direction_output = at91_gpio_direction_output,
  484. .get_value = at91_gpio_get_value,
  485. .set_value = at91_gpio_set_value,
  486. .get_function = at91_gpio_get_function,
  487. };
  488. static int at91_gpio_probe(struct udevice *dev)
  489. {
  490. struct at91_port_priv *port = dev_get_priv(dev);
  491. struct at91_port_platdata *plat = dev_get_platdata(dev);
  492. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  493. struct clk clk;
  494. int ret;
  495. ret = clk_get_by_index(dev, 0, &clk);
  496. if (ret)
  497. return ret;
  498. ret = clk_enable(&clk);
  499. if (ret)
  500. return ret;
  501. clk_free(&clk);
  502. #if CONFIG_IS_ENABLED(OF_CONTROL)
  503. plat->base_addr = (uint32_t)devfdt_get_addr_ptr(dev);
  504. #endif
  505. plat->bank_name = at91_get_bank_name(plat->base_addr);
  506. port->regs = (struct at91_port *)plat->base_addr;
  507. uc_priv->bank_name = plat->bank_name;
  508. uc_priv->gpio_count = GPIO_PER_BANK;
  509. return 0;
  510. }
  511. #if CONFIG_IS_ENABLED(OF_CONTROL)
  512. static const struct udevice_id at91_gpio_ids[] = {
  513. { .compatible = "atmel,at91rm9200-gpio" },
  514. { }
  515. };
  516. #endif
  517. U_BOOT_DRIVER(gpio_at91) = {
  518. .name = "gpio_at91",
  519. .id = UCLASS_GPIO,
  520. #if CONFIG_IS_ENABLED(OF_CONTROL)
  521. .of_match = at91_gpio_ids,
  522. .platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
  523. #endif
  524. .ops = &gpio_at91_ops,
  525. .probe = at91_gpio_probe,
  526. .priv_auto_alloc_size = sizeof(struct at91_port_priv),
  527. };
  528. #endif