hwinit.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * Functions for omap5 based boards.
  5. *
  6. * (C) Copyright 2011
  7. * Texas Instruments, <www.ti.com>
  8. *
  9. * Author :
  10. * Aneesh V <aneesh@ti.com>
  11. * Steve Sakoman <steve@sakoman.com>
  12. * Sricharan <r.sricharan@ti.com>
  13. */
  14. #include <common.h>
  15. #include <palmas.h>
  16. #include <asm/armv7.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/clock.h>
  20. #include <linux/sizes.h>
  21. #include <asm/utils.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/emif.h>
  24. #include <asm/omap_common.h>
  25. u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  26. #if !CONFIG_IS_ENABLED(DM_GPIO)
  27. static struct gpio_bank gpio_bank_54xx[8] = {
  28. { (void *)OMAP54XX_GPIO1_BASE },
  29. { (void *)OMAP54XX_GPIO2_BASE },
  30. { (void *)OMAP54XX_GPIO3_BASE },
  31. { (void *)OMAP54XX_GPIO4_BASE },
  32. { (void *)OMAP54XX_GPIO5_BASE },
  33. { (void *)OMAP54XX_GPIO6_BASE },
  34. { (void *)OMAP54XX_GPIO7_BASE },
  35. { (void *)OMAP54XX_GPIO8_BASE },
  36. };
  37. const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  38. #endif
  39. void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
  40. {
  41. int i;
  42. struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
  43. for (i = 0; i < size; i++, pad++)
  44. writel(pad->val, base + pad->offset);
  45. }
  46. #ifdef CONFIG_SPL_BUILD
  47. /* LPDDR2 specific IO settings */
  48. static void io_settings_lpddr2(void)
  49. {
  50. const struct ctrl_ioregs *ioregs;
  51. get_ioregs(&ioregs);
  52. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  53. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  54. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  55. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  56. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  57. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  58. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  59. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  60. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  61. }
  62. /* DDR3 specific IO settings */
  63. static void io_settings_ddr3(void)
  64. {
  65. u32 io_settings = 0;
  66. const struct ctrl_ioregs *ioregs;
  67. get_ioregs(&ioregs);
  68. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  69. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  70. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  71. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  72. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  73. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  74. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  75. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  76. if (!is_dra7xx()) {
  77. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  78. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  79. }
  80. /* omap5432 does not use lpddr2 */
  81. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  82. writel(ioregs->ctrl_emif_sdram_config_ext,
  83. (*ctrl)->control_emif1_sdram_config_ext);
  84. if (!is_dra72x())
  85. writel(ioregs->ctrl_emif_sdram_config_ext,
  86. (*ctrl)->control_emif2_sdram_config_ext);
  87. if (is_omap54xx()) {
  88. /* Disable DLL select */
  89. io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
  90. & 0xFFEFFFFF);
  91. writel(io_settings,
  92. (*ctrl)->control_port_emif1_sdram_config);
  93. io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
  94. & 0xFFEFFFFF);
  95. writel(io_settings,
  96. (*ctrl)->control_port_emif2_sdram_config);
  97. } else {
  98. writel(ioregs->ctrl_ddr_ctrl_ext_0,
  99. (*ctrl)->control_ddr_control_ext_0);
  100. }
  101. }
  102. /*
  103. * Some tuning of IOs for optimal power and performance
  104. */
  105. void do_io_settings(void)
  106. {
  107. u32 io_settings = 0, mask = 0;
  108. struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
  109. /* Impedance settings EMMC, C2C 1,2, hsi2 */
  110. mask = (ds_mask << 2) | (ds_mask << 8) |
  111. (ds_mask << 16) | (ds_mask << 18);
  112. io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
  113. (~mask);
  114. io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
  115. (ds_45_ohm << 18) | (ds_60_ohm << 2);
  116. writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
  117. /* Impedance settings Mcspi2 */
  118. mask = (ds_mask << 30);
  119. io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
  120. (~mask);
  121. io_settings |= (ds_60_ohm << 30);
  122. writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
  123. /* Impedance settings C2C 3,4 */
  124. mask = (ds_mask << 14) | (ds_mask << 16);
  125. io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
  126. (~mask);
  127. io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
  128. writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
  129. /* Slew rate settings EMMC, C2C 1,2 */
  130. mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
  131. io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
  132. (~mask);
  133. io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
  134. writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
  135. /* Slew rate settings hsi2, Mcspi2 */
  136. mask = (sc_mask << 24) | (sc_mask << 28);
  137. io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
  138. (~mask);
  139. io_settings |= (sc_fast << 28) | (sc_fast << 24);
  140. writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
  141. /* Slew rate settings C2C 3,4 */
  142. mask = (sc_mask << 16) | (sc_mask << 18);
  143. io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
  144. (~mask);
  145. io_settings |= (sc_na << 16) | (sc_na << 18);
  146. writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
  147. /* impedance and slew rate settings for usb */
  148. mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
  149. (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
  150. io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
  151. (~mask);
  152. io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
  153. (ds_60_ohm << 23) | (sc_fast << 20) |
  154. (sc_fast << 17) | (sc_fast << 14);
  155. writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
  156. if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
  157. io_settings_lpddr2();
  158. else
  159. io_settings_ddr3();
  160. }
  161. static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
  162. {0x45, 0x1}, /* 12 MHz */
  163. {-1, -1}, /* 13 MHz */
  164. {0x63, 0x2}, /* 16.8 MHz */
  165. {0x57, 0x2}, /* 19.2 MHz */
  166. {0x20, 0x1}, /* 26 MHz */
  167. {-1, -1}, /* 27 MHz */
  168. {0x41, 0x3} /* 38.4 MHz */
  169. };
  170. void srcomp_enable(void)
  171. {
  172. u32 srcomp_value, mul_factor, div_factor, clk_val, i;
  173. u32 sysclk_ind = get_sys_clk_index();
  174. u32 omap_rev = omap_revision();
  175. if (!is_omap54xx())
  176. return;
  177. mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
  178. div_factor = srcomp_parameters[sysclk_ind].divide_factor;
  179. for (i = 0; i < 4; i++) {
  180. srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
  181. srcomp_value &=
  182. ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
  183. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  184. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  185. writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
  186. }
  187. if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
  188. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  189. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  190. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  191. for (i = 0; i < 4; i++) {
  192. srcomp_value =
  193. readl((*ctrl)->control_srcomp_north_side + i*4);
  194. srcomp_value &= ~PWRDWN_XS_MASK;
  195. writel(srcomp_value,
  196. (*ctrl)->control_srcomp_north_side + i*4);
  197. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  198. & SRCODE_READ_XS_MASK) >>
  199. SRCODE_READ_XS_SHIFT) == 0)
  200. ;
  201. srcomp_value =
  202. readl((*ctrl)->control_srcomp_north_side + i*4);
  203. srcomp_value &= ~OVERRIDE_XS_MASK;
  204. writel(srcomp_value,
  205. (*ctrl)->control_srcomp_north_side + i*4);
  206. }
  207. } else {
  208. srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
  209. srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
  210. DIVIDE_FACTOR_XS_MASK);
  211. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  212. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  213. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  214. for (i = 0; i < 4; i++) {
  215. srcomp_value =
  216. readl((*ctrl)->control_srcomp_north_side + i*4);
  217. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  218. writel(srcomp_value,
  219. (*ctrl)->control_srcomp_north_side + i*4);
  220. srcomp_value =
  221. readl((*ctrl)->control_srcomp_north_side + i*4);
  222. srcomp_value &= ~OVERRIDE_XS_MASK;
  223. writel(srcomp_value,
  224. (*ctrl)->control_srcomp_north_side + i*4);
  225. }
  226. srcomp_value =
  227. readl((*ctrl)->control_srcomp_east_side_wkup);
  228. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  229. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  230. srcomp_value =
  231. readl((*ctrl)->control_srcomp_east_side_wkup);
  232. srcomp_value &= ~OVERRIDE_XS_MASK;
  233. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  234. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  235. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  236. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  237. clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  238. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  239. writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  240. for (i = 0; i < 4; i++) {
  241. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  242. & SRCODE_READ_XS_MASK) >>
  243. SRCODE_READ_XS_SHIFT) == 0)
  244. ;
  245. srcomp_value =
  246. readl((*ctrl)->control_srcomp_north_side + i*4);
  247. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  248. writel(srcomp_value,
  249. (*ctrl)->control_srcomp_north_side + i*4);
  250. }
  251. while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
  252. SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
  253. ;
  254. srcomp_value =
  255. readl((*ctrl)->control_srcomp_east_side_wkup);
  256. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  257. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  258. }
  259. }
  260. #endif
  261. void config_data_eye_leveling_samples(u32 emif_base)
  262. {
  263. const struct ctrl_ioregs *ioregs;
  264. get_ioregs(&ioregs);
  265. /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
  266. if (emif_base == EMIF1_BASE)
  267. writel(ioregs->ctrl_emif_sdram_config_ext_final,
  268. (*ctrl)->control_emif1_sdram_config_ext);
  269. else if (emif_base == EMIF2_BASE)
  270. writel(ioregs->ctrl_emif_sdram_config_ext_final,
  271. (*ctrl)->control_emif2_sdram_config_ext);
  272. }
  273. void init_cpu_configuration(void)
  274. {
  275. u32 l2actlr;
  276. asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
  277. /*
  278. * L2ACTLR: Ensure to enable the following:
  279. * 3: Disable clean/evict push to external
  280. * 4: Disable WriteUnique and WriteLineUnique transactions from master
  281. * 8: Disable DVM/CMO message broadcast
  282. */
  283. l2actlr |= 0x118;
  284. omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
  285. }
  286. void init_omap_revision(void)
  287. {
  288. /*
  289. * For some of the ES2/ES1 boards ID_CODE is not reliable:
  290. * Also, ES1 and ES2 have different ARM revisions
  291. * So use ARM revision for identification
  292. */
  293. unsigned int rev = cortex_rev();
  294. switch (readl(CONTROL_ID_CODE)) {
  295. case OMAP5430_CONTROL_ID_CODE_ES1_0:
  296. *omap_si_rev = OMAP5430_ES1_0;
  297. if (rev == MIDR_CORTEX_A15_R2P2)
  298. *omap_si_rev = OMAP5430_ES2_0;
  299. break;
  300. case OMAP5432_CONTROL_ID_CODE_ES1_0:
  301. *omap_si_rev = OMAP5432_ES1_0;
  302. if (rev == MIDR_CORTEX_A15_R2P2)
  303. *omap_si_rev = OMAP5432_ES2_0;
  304. break;
  305. case OMAP5430_CONTROL_ID_CODE_ES2_0:
  306. *omap_si_rev = OMAP5430_ES2_0;
  307. break;
  308. case OMAP5432_CONTROL_ID_CODE_ES2_0:
  309. *omap_si_rev = OMAP5432_ES2_0;
  310. break;
  311. case DRA762_CONTROL_ID_CODE_ES1_0:
  312. *omap_si_rev = DRA762_ES1_0;
  313. break;
  314. case DRA752_CONTROL_ID_CODE_ES1_0:
  315. *omap_si_rev = DRA752_ES1_0;
  316. break;
  317. case DRA752_CONTROL_ID_CODE_ES1_1:
  318. *omap_si_rev = DRA752_ES1_1;
  319. break;
  320. case DRA752_CONTROL_ID_CODE_ES2_0:
  321. *omap_si_rev = DRA752_ES2_0;
  322. break;
  323. case DRA722_CONTROL_ID_CODE_ES1_0:
  324. *omap_si_rev = DRA722_ES1_0;
  325. break;
  326. case DRA722_CONTROL_ID_CODE_ES2_0:
  327. *omap_si_rev = DRA722_ES2_0;
  328. break;
  329. case DRA722_CONTROL_ID_CODE_ES2_1:
  330. *omap_si_rev = DRA722_ES2_1;
  331. break;
  332. default:
  333. *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
  334. }
  335. init_cpu_configuration();
  336. }
  337. void init_package_revision(void)
  338. {
  339. unsigned int die_id[4] = { 0 };
  340. u8 package;
  341. omap_die_id(die_id);
  342. package = (die_id[2] >> 16) & 0x3;
  343. if (is_dra76x()) {
  344. switch (package) {
  345. case DRA762_ABZ_PACKAGE:
  346. *omap_si_rev = DRA762_ABZ_ES1_0;
  347. break;
  348. case DRA762_ACD_PACKAGE:
  349. default:
  350. *omap_si_rev = DRA762_ACD_ES1_0;
  351. break;
  352. }
  353. }
  354. }
  355. void omap_die_id(unsigned int *die_id)
  356. {
  357. die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
  358. die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
  359. die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
  360. die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
  361. }
  362. void reset_cpu(ulong ignored)
  363. {
  364. u32 omap_rev = omap_revision();
  365. /*
  366. * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
  367. * So use cold reset in case instead.
  368. */
  369. if (omap_rev == OMAP5430_ES1_0)
  370. writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
  371. else
  372. writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
  373. }
  374. u32 warm_reset(void)
  375. {
  376. return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
  377. }
  378. void setup_warmreset_time(void)
  379. {
  380. u32 rst_time, rst_val;
  381. /*
  382. * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
  383. * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
  384. * into microsec and passing the value.
  385. */
  386. rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC)
  387. << RSTTIME1_SHIFT;
  388. if (rst_time > RSTTIME1_MASK)
  389. rst_time = RSTTIME1_MASK;
  390. rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
  391. rst_val |= rst_time;
  392. writel(rst_val, (*prcm)->prm_rsttime);
  393. }
  394. void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
  395. u32 cpu_rev_comb, u32 cpu_variant,
  396. u32 cpu_rev)
  397. {
  398. omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
  399. }
  400. void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  401. u32 cpu_variant, u32 cpu_rev)
  402. {
  403. #ifdef CONFIG_ARM_ERRATA_801819
  404. /*
  405. * DRA72x processors are uniprocessors and DONOT have
  406. * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
  407. * Extensions) Hence the erratum workaround is not applicable for
  408. * DRA72x processors.
  409. */
  410. if (is_dra72x())
  411. acr &= ~((0x3 << 23) | (0x3 << 25));
  412. #endif
  413. omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
  414. }
  415. #if defined(CONFIG_PALMAS_POWER)
  416. __weak void board_mmc_poweron_ldo(uint voltage)
  417. {
  418. palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
  419. }
  420. void vmmc_pbias_config(uint voltage)
  421. {
  422. u32 value = 0;
  423. value = readl((*ctrl)->control_pbias);
  424. value &= ~SDCARD_PWRDNZ;
  425. writel(value, (*ctrl)->control_pbias);
  426. udelay(10); /* wait 10 us */
  427. value &= ~SDCARD_BIAS_PWRDNZ;
  428. writel(value, (*ctrl)->control_pbias);
  429. board_mmc_poweron_ldo(voltage);
  430. value = readl((*ctrl)->control_pbias);
  431. value |= SDCARD_BIAS_PWRDNZ;
  432. writel(value, (*ctrl)->control_pbias);
  433. udelay(150); /* wait 150 us */
  434. value |= SDCARD_PWRDNZ;
  435. writel(value, (*ctrl)->control_pbias);
  436. udelay(150); /* wait 150 us */
  437. }
  438. #endif