board.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Common board functions for AM33XX based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <debug_uart.h>
  12. #include <errno.h>
  13. #include <ns16550.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/i2c.h>
  22. #include <asm/arch/mem.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/io.h>
  26. #include <asm/emif.h>
  27. #include <asm/gpio.h>
  28. #include <asm/omap_common.h>
  29. #include <i2c.h>
  30. #include <miiphy.h>
  31. #include <cpsw.h>
  32. #include <linux/errno.h>
  33. #include <linux/compiler.h>
  34. #include <linux/usb/ch9.h>
  35. #include <linux/usb/gadget.h>
  36. #include <linux/usb/musb.h>
  37. #include <asm/omap_musb.h>
  38. #include <asm/davinci_rtc.h>
  39. #define AM43XX_EMIF_BASE 0x4C000000
  40. #define AM43XX_SDRAM_CONFIG_OFFSET 0x8
  41. #define AM43XX_SDRAM_TYPE_MASK 0xE0000000
  42. #define AM43XX_SDRAM_TYPE_SHIFT 29
  43. #define AM43XX_SDRAM_TYPE_DDR3 3
  44. #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
  45. #define AM43XX_RDWRLVLFULL_START 0x80000000
  46. DECLARE_GLOBAL_DATA_PTR;
  47. int dram_init(void)
  48. {
  49. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  50. sdram_init();
  51. #endif
  52. /* dram_init must store complete ramsize in gd->ram_size */
  53. gd->ram_size = get_ram_size(
  54. (void *)CONFIG_SYS_SDRAM_BASE,
  55. CONFIG_MAX_RAM_BANK_SIZE);
  56. return 0;
  57. }
  58. int dram_init_banksize(void)
  59. {
  60. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  61. gd->bd->bi_dram[0].size = gd->ram_size;
  62. return 0;
  63. }
  64. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  65. static const struct ns16550_platdata am33xx_serial[] = {
  66. { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  67. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  68. # ifdef CONFIG_SYS_NS16550_COM2
  69. { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  70. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  71. # ifdef CONFIG_SYS_NS16550_COM3
  72. { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  73. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  74. { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  75. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  76. { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  77. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  78. { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  79. .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  80. # endif
  81. # endif
  82. };
  83. U_BOOT_DEVICES(am33xx_uarts) = {
  84. { "ns16550_serial", &am33xx_serial[0] },
  85. # ifdef CONFIG_SYS_NS16550_COM2
  86. { "ns16550_serial", &am33xx_serial[1] },
  87. # ifdef CONFIG_SYS_NS16550_COM3
  88. { "ns16550_serial", &am33xx_serial[2] },
  89. { "ns16550_serial", &am33xx_serial[3] },
  90. { "ns16550_serial", &am33xx_serial[4] },
  91. { "ns16550_serial", &am33xx_serial[5] },
  92. # endif
  93. # endif
  94. };
  95. #ifdef CONFIG_DM_I2C
  96. static const struct omap_i2c_platdata am33xx_i2c[] = {
  97. { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
  98. { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
  99. { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
  100. };
  101. U_BOOT_DEVICES(am33xx_i2c) = {
  102. { "i2c_omap", &am33xx_i2c[0] },
  103. { "i2c_omap", &am33xx_i2c[1] },
  104. { "i2c_omap", &am33xx_i2c[2] },
  105. };
  106. #endif
  107. #if CONFIG_IS_ENABLED(DM_GPIO)
  108. static const struct omap_gpio_platdata am33xx_gpio[] = {
  109. { 0, AM33XX_GPIO0_BASE },
  110. { 1, AM33XX_GPIO1_BASE },
  111. { 2, AM33XX_GPIO2_BASE },
  112. { 3, AM33XX_GPIO3_BASE },
  113. #ifdef CONFIG_AM43XX
  114. { 4, AM33XX_GPIO4_BASE },
  115. { 5, AM33XX_GPIO5_BASE },
  116. #endif
  117. };
  118. U_BOOT_DEVICES(am33xx_gpios) = {
  119. { "gpio_omap", &am33xx_gpio[0] },
  120. { "gpio_omap", &am33xx_gpio[1] },
  121. { "gpio_omap", &am33xx_gpio[2] },
  122. { "gpio_omap", &am33xx_gpio[3] },
  123. #ifdef CONFIG_AM43XX
  124. { "gpio_omap", &am33xx_gpio[4] },
  125. { "gpio_omap", &am33xx_gpio[5] },
  126. #endif
  127. };
  128. #endif
  129. #endif
  130. #if !CONFIG_IS_ENABLED(DM_GPIO)
  131. static const struct gpio_bank gpio_bank_am33xx[] = {
  132. { (void *)AM33XX_GPIO0_BASE },
  133. { (void *)AM33XX_GPIO1_BASE },
  134. { (void *)AM33XX_GPIO2_BASE },
  135. { (void *)AM33XX_GPIO3_BASE },
  136. #ifdef CONFIG_AM43XX
  137. { (void *)AM33XX_GPIO4_BASE },
  138. { (void *)AM33XX_GPIO5_BASE },
  139. #endif
  140. };
  141. const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
  142. #endif
  143. #if defined(CONFIG_MMC_OMAP_HS)
  144. int cpu_mmc_init(bd_t *bis)
  145. {
  146. int ret;
  147. ret = omap_mmc_init(0, 0, 0, -1, -1);
  148. if (ret)
  149. return ret;
  150. return omap_mmc_init(1, 0, 0, -1, -1);
  151. }
  152. #endif
  153. /*
  154. * RTC only with DDR in self-refresh mode magic value, checked against during
  155. * boot to see if we have a valid config. This should be in sync with the value
  156. * that will be in drivers/soc/ti/pm33xx.c.
  157. */
  158. #define RTC_MAGIC_VAL 0x8cd0
  159. /* Board type field bit shift for RTC only with DDR in self-refresh mode */
  160. #define RTC_BOARD_TYPE_SHIFT 16
  161. /* AM33XX has two MUSB controllers which can be host or gadget */
  162. #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
  163. (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
  164. (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
  165. (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
  166. static struct musb_hdrc_config musb_config = {
  167. .multipoint = 1,
  168. .dyn_fifo = 1,
  169. .num_eps = 16,
  170. .ram_bits = 12,
  171. };
  172. #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
  173. static struct ti_musb_platdata usb0 = {
  174. .base = (void *)USB0_OTG_BASE,
  175. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
  176. .plat = {
  177. .config = &musb_config,
  178. .power = 50,
  179. .platform_ops = &musb_dsps_ops,
  180. },
  181. };
  182. static struct ti_musb_platdata usb1 = {
  183. .base = (void *)USB1_OTG_BASE,
  184. .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
  185. .plat = {
  186. .config = &musb_config,
  187. .power = 50,
  188. .platform_ops = &musb_dsps_ops,
  189. },
  190. };
  191. U_BOOT_DEVICES(am33xx_usbs) = {
  192. #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
  193. { "ti-musb-peripheral", &usb0 },
  194. #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
  195. { "ti-musb-host", &usb0 },
  196. #endif
  197. #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
  198. { "ti-musb-peripheral", &usb1 },
  199. #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
  200. { "ti-musb-host", &usb1 },
  201. #endif
  202. };
  203. int arch_misc_init(void)
  204. {
  205. return 0;
  206. }
  207. #else
  208. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  209. /* USB 2.0 PHY Control */
  210. #define CM_PHY_PWRDN (1 << 0)
  211. #define CM_PHY_OTG_PWRDN (1 << 1)
  212. #define OTGVDET_EN (1 << 19)
  213. #define OTGSESSENDEN (1 << 20)
  214. static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
  215. {
  216. if (on) {
  217. clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
  218. OTGVDET_EN | OTGSESSENDEN);
  219. } else {
  220. clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
  221. }
  222. }
  223. #ifdef CONFIG_AM335X_USB0
  224. static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
  225. {
  226. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
  227. }
  228. struct omap_musb_board_data otg0_board_data = {
  229. .set_phy_power = am33xx_otg0_set_phy_power,
  230. };
  231. static struct musb_hdrc_platform_data otg0_plat = {
  232. .mode = CONFIG_AM335X_USB0_MODE,
  233. .config = &musb_config,
  234. .power = 50,
  235. .platform_ops = &musb_dsps_ops,
  236. .board_data = &otg0_board_data,
  237. };
  238. #endif
  239. #ifdef CONFIG_AM335X_USB1
  240. static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
  241. {
  242. am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
  243. }
  244. struct omap_musb_board_data otg1_board_data = {
  245. .set_phy_power = am33xx_otg1_set_phy_power,
  246. };
  247. static struct musb_hdrc_platform_data otg1_plat = {
  248. .mode = CONFIG_AM335X_USB1_MODE,
  249. .config = &musb_config,
  250. .power = 50,
  251. .platform_ops = &musb_dsps_ops,
  252. .board_data = &otg1_board_data,
  253. };
  254. #endif
  255. int arch_misc_init(void)
  256. {
  257. #ifdef CONFIG_AM335X_USB0
  258. musb_register(&otg0_plat, &otg0_board_data,
  259. (void *)USB0_OTG_BASE);
  260. #endif
  261. #ifdef CONFIG_AM335X_USB1
  262. musb_register(&otg1_plat, &otg1_board_data,
  263. (void *)USB1_OTG_BASE);
  264. #endif
  265. return 0;
  266. }
  267. #endif
  268. #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  269. int arch_misc_init(void)
  270. {
  271. struct udevice *dev;
  272. int ret;
  273. ret = uclass_first_device(UCLASS_MISC, &dev);
  274. if (ret || !dev)
  275. return ret;
  276. #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
  277. ret = usb_ether_init();
  278. if (ret) {
  279. pr_err("USB ether init failed\n");
  280. return ret;
  281. }
  282. #endif
  283. return 0;
  284. }
  285. #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
  286. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  287. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
  288. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
  289. static void rtc32k_unlock(struct davinci_rtc *rtc)
  290. {
  291. /*
  292. * Unlock the RTC's registers. For more details please see the
  293. * RTC_SS section of the TRM. In order to unlock we need to
  294. * write these specific values (keys) in this order.
  295. */
  296. writel(RTC_KICK0R_WE, &rtc->kick0r);
  297. writel(RTC_KICK1R_WE, &rtc->kick1r);
  298. }
  299. #endif
  300. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  301. /*
  302. * Write contents of the RTC_SCRATCH1 register based on board type
  303. * Two things are passed
  304. * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
  305. * control gets to kernel, kernel reads the scratchpad register and gets to
  306. * know that bootloader has rtc_only support.
  307. *
  308. * Second important thing is the board type (16:31). This is needed in the
  309. * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
  310. * identify the board type and we go ahead and copy the board strings to
  311. * am43xx_board_name.
  312. */
  313. void update_rtc_magic(void)
  314. {
  315. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  316. u32 magic = RTC_MAGIC_VAL;
  317. magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
  318. rtc32k_unlock(rtc);
  319. /* write magic */
  320. writel(magic, &rtc->scratch1);
  321. }
  322. #endif
  323. /*
  324. * In the case of non-SPL based booting we'll want to call these
  325. * functions a tiny bit later as it will require gd to be set and cleared
  326. * and that's not true in s_init in this case so we cannot do it there.
  327. */
  328. int board_early_init_f(void)
  329. {
  330. set_mux_conf_regs();
  331. prcm_init();
  332. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  333. update_rtc_magic();
  334. #endif
  335. return 0;
  336. }
  337. /*
  338. * This function is the place to do per-board things such as ramp up the
  339. * MPU clock frequency.
  340. */
  341. __weak void am33xx_spl_board_init(void)
  342. {
  343. }
  344. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  345. static void rtc32k_enable(void)
  346. {
  347. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  348. rtc32k_unlock(rtc);
  349. /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  350. writel((1 << 3) | (1 << 6), &rtc->osc);
  351. }
  352. #endif
  353. static void uart_soft_reset(void)
  354. {
  355. struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  356. u32 regval;
  357. regval = readl(&uart_base->uartsyscfg);
  358. regval |= UART_RESET;
  359. writel(regval, &uart_base->uartsyscfg);
  360. while ((readl(&uart_base->uartsyssts) &
  361. UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  362. ;
  363. /* Disable smart idle */
  364. regval = readl(&uart_base->uartsyscfg);
  365. regval |= UART_SMART_IDLE_EN;
  366. writel(regval, &uart_base->uartsyscfg);
  367. }
  368. static void watchdog_disable(void)
  369. {
  370. struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  371. writel(0xAAAA, &wdtimer->wdtwspr);
  372. while (readl(&wdtimer->wdtwwps) != 0x0)
  373. ;
  374. writel(0x5555, &wdtimer->wdtwspr);
  375. while (readl(&wdtimer->wdtwwps) != 0x0)
  376. ;
  377. }
  378. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  379. /*
  380. * Check if we are executing rtc-only + DDR mode, and resume from it if needed
  381. */
  382. static void rtc_only(void)
  383. {
  384. struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
  385. struct prm_device_inst *prm_device =
  386. (struct prm_device_inst *)PRM_DEVICE_INST;
  387. u32 scratch1, sdrc;
  388. void (*resume_func)(void);
  389. scratch1 = readl(&rtc->scratch1);
  390. /*
  391. * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
  392. * written to this register when we want to wake up from RTC only
  393. * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
  394. * bits 0-15: RTC_MAGIC_VAL
  395. * bits 16-31: board type (needed for sdram_init)
  396. */
  397. if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
  398. return;
  399. rtc32k_unlock(rtc);
  400. /* Clear RTC magic */
  401. writel(0, &rtc->scratch1);
  402. /*
  403. * Update board type based on value stored on RTC_SCRATCH1, this
  404. * is done so that we don't need to read the board type from eeprom
  405. * over i2c bus which is expensive
  406. */
  407. rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
  408. /*
  409. * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
  410. * are resuming from self-refresh. This avoids an unnecessary re-init
  411. * of the DDR. The re-init takes time and we would need to wait for
  412. * it to complete before accessing DDR to avoid L3 NOC errors.
  413. */
  414. writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
  415. rtc_only_prcm_init();
  416. sdram_init();
  417. /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
  418. /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
  419. sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
  420. sdrc &= AM43XX_SDRAM_TYPE_MASK;
  421. sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
  422. if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
  423. writel(AM43XX_RDWRLVLFULL_START,
  424. AM43XX_EMIF_BASE +
  425. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  426. mdelay(1);
  427. am43xx_wait:
  428. sdrc = readl(AM43XX_EMIF_BASE +
  429. AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
  430. if (sdrc == AM43XX_RDWRLVLFULL_START)
  431. goto am43xx_wait;
  432. }
  433. resume_func = (void *)readl(&rtc->scratch0);
  434. if (resume_func)
  435. resume_func();
  436. }
  437. #endif
  438. void s_init(void)
  439. {
  440. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
  441. rtc_only();
  442. #endif
  443. }
  444. void early_system_init(void)
  445. {
  446. /*
  447. * The ROM will only have set up sufficient pinmux to allow for the
  448. * first 4KiB NOR to be read, we must finish doing what we know of
  449. * the NOR mux in this space in order to continue.
  450. */
  451. #ifdef CONFIG_NOR_BOOT
  452. enable_norboot_pin_mux();
  453. #endif
  454. watchdog_disable();
  455. set_uart_mux_conf();
  456. setup_early_clocks();
  457. uart_soft_reset();
  458. #ifdef CONFIG_SPL_BUILD
  459. /*
  460. * Save the boot parameters passed from romcode.
  461. * We cannot delay the saving further than this,
  462. * to prevent overwrites.
  463. */
  464. save_omap_boot_params();
  465. #endif
  466. #ifdef CONFIG_DEBUG_UART_OMAP
  467. debug_uart_init();
  468. #endif
  469. #ifdef CONFIG_SPL_BUILD
  470. spl_early_init();
  471. #endif
  472. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  473. do_board_detect();
  474. #endif
  475. #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
  476. /* Enable RTC32K clock */
  477. rtc32k_enable();
  478. #endif
  479. }
  480. #ifdef CONFIG_SPL_BUILD
  481. void board_init_f(ulong dummy)
  482. {
  483. hw_data_init();
  484. early_system_init();
  485. board_early_init_f();
  486. sdram_init();
  487. /* dram_init must store complete ramsize in gd->ram_size */
  488. gd->ram_size = get_ram_size(
  489. (void *)CONFIG_SYS_SDRAM_BASE,
  490. CONFIG_MAX_RAM_BANK_SIZE);
  491. }
  492. #endif
  493. #endif
  494. int arch_cpu_init_dm(void)
  495. {
  496. hw_data_init();
  497. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  498. early_system_init();
  499. #endif
  500. return 0;
  501. }