sdhci.c 14 KB

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  1. /*
  2. * Copyright 2011, Marvell Semiconductor Inc.
  3. * Lei Wen <leiwen@marvell.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. *
  7. * Back ported to the 8xx platform (from the 8260 platform) by
  8. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  9. */
  10. #include <common.h>
  11. #include <malloc.h>
  12. #include <mmc.h>
  13. #include <sdhci.h>
  14. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  15. void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  16. #else
  17. void *aligned_buffer;
  18. #endif
  19. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  20. {
  21. unsigned long timeout;
  22. /* Wait max 100 ms */
  23. timeout = 100;
  24. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  25. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  26. if (timeout == 0) {
  27. printf("%s: Reset 0x%x never completed.\n",
  28. __func__, (int)mask);
  29. return;
  30. }
  31. timeout--;
  32. udelay(1000);
  33. }
  34. }
  35. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  36. {
  37. int i;
  38. if (cmd->resp_type & MMC_RSP_136) {
  39. /* CRC is stripped so we need to do some shifting. */
  40. for (i = 0; i < 4; i++) {
  41. cmd->response[i] = sdhci_readl(host,
  42. SDHCI_RESPONSE + (3-i)*4) << 8;
  43. if (i != 3)
  44. cmd->response[i] |= sdhci_readb(host,
  45. SDHCI_RESPONSE + (3-i)*4-1);
  46. }
  47. } else {
  48. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  49. }
  50. }
  51. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  52. {
  53. int i;
  54. char *offs;
  55. for (i = 0; i < data->blocksize; i += 4) {
  56. offs = data->dest + i;
  57. if (data->flags == MMC_DATA_READ)
  58. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  59. else
  60. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  61. }
  62. }
  63. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
  64. unsigned int start_addr)
  65. {
  66. unsigned int stat, rdy, mask, timeout, block = 0;
  67. #ifdef CONFIG_MMC_SDMA
  68. unsigned char ctrl;
  69. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  70. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  71. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  72. #endif
  73. timeout = 1000000;
  74. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  75. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  76. do {
  77. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  78. if (stat & SDHCI_INT_ERROR) {
  79. printf("%s: Error detected in status(0x%X)!\n",
  80. __func__, stat);
  81. return -1;
  82. }
  83. if (stat & rdy) {
  84. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  85. continue;
  86. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  87. sdhci_transfer_pio(host, data);
  88. data->dest += data->blocksize;
  89. if (++block >= data->blocks)
  90. break;
  91. }
  92. #ifdef CONFIG_MMC_SDMA
  93. if (stat & SDHCI_INT_DMA_END) {
  94. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  95. start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  96. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  97. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  98. }
  99. #endif
  100. if (timeout-- > 0)
  101. udelay(10);
  102. else {
  103. printf("%s: Transfer data timeout\n", __func__);
  104. return -1;
  105. }
  106. } while (!(stat & SDHCI_INT_DATA_END));
  107. return 0;
  108. }
  109. /*
  110. * No command will be sent by driver if card is busy, so driver must wait
  111. * for card ready state.
  112. * Every time when card is busy after timeout then (last) timeout value will be
  113. * increased twice but only if it doesn't exceed global defined maximum.
  114. * Each function call will use last timeout value. Max timeout can be redefined
  115. * in board config file.
  116. */
  117. #ifndef CONFIG_SDHCI_CMD_MAX_TIMEOUT
  118. #define CONFIG_SDHCI_CMD_MAX_TIMEOUT 3200
  119. #endif
  120. #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100
  121. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  122. struct mmc_data *data)
  123. {
  124. struct sdhci_host *host = mmc->priv;
  125. unsigned int stat = 0;
  126. int ret = 0;
  127. int trans_bytes = 0, is_aligned = 1;
  128. u32 mask, flags, mode;
  129. unsigned int time = 0, start_addr = 0;
  130. int mmc_dev = mmc->block_dev.devnum;
  131. unsigned start = get_timer(0);
  132. /* Timeout unit - ms */
  133. static unsigned int cmd_timeout = CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT;
  134. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  135. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  136. /* We shouldn't wait for data inihibit for stop commands, even
  137. though they might use busy signaling */
  138. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  139. mask &= ~SDHCI_DATA_INHIBIT;
  140. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  141. if (time >= cmd_timeout) {
  142. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  143. if (2 * cmd_timeout <= CONFIG_SDHCI_CMD_MAX_TIMEOUT) {
  144. cmd_timeout += cmd_timeout;
  145. printf("timeout increasing to: %u ms.\n",
  146. cmd_timeout);
  147. } else {
  148. puts("timeout.\n");
  149. return COMM_ERR;
  150. }
  151. }
  152. time++;
  153. udelay(1000);
  154. }
  155. mask = SDHCI_INT_RESPONSE;
  156. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  157. flags = SDHCI_CMD_RESP_NONE;
  158. else if (cmd->resp_type & MMC_RSP_136)
  159. flags = SDHCI_CMD_RESP_LONG;
  160. else if (cmd->resp_type & MMC_RSP_BUSY) {
  161. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  162. mask |= SDHCI_INT_DATA_END;
  163. } else
  164. flags = SDHCI_CMD_RESP_SHORT;
  165. if (cmd->resp_type & MMC_RSP_CRC)
  166. flags |= SDHCI_CMD_CRC;
  167. if (cmd->resp_type & MMC_RSP_OPCODE)
  168. flags |= SDHCI_CMD_INDEX;
  169. if (data)
  170. flags |= SDHCI_CMD_DATA;
  171. /* Set Transfer mode regarding to data flag */
  172. if (data != 0) {
  173. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  174. mode = SDHCI_TRNS_BLK_CNT_EN;
  175. trans_bytes = data->blocks * data->blocksize;
  176. if (data->blocks > 1)
  177. mode |= SDHCI_TRNS_MULTI;
  178. if (data->flags == MMC_DATA_READ)
  179. mode |= SDHCI_TRNS_READ;
  180. #ifdef CONFIG_MMC_SDMA
  181. if (data->flags == MMC_DATA_READ)
  182. start_addr = (unsigned long)data->dest;
  183. else
  184. start_addr = (unsigned long)data->src;
  185. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  186. (start_addr & 0x7) != 0x0) {
  187. is_aligned = 0;
  188. start_addr = (unsigned long)aligned_buffer;
  189. if (data->flags != MMC_DATA_READ)
  190. memcpy(aligned_buffer, data->src, trans_bytes);
  191. }
  192. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  193. /*
  194. * Always use this bounce-buffer when
  195. * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
  196. */
  197. is_aligned = 0;
  198. start_addr = (unsigned long)aligned_buffer;
  199. if (data->flags != MMC_DATA_READ)
  200. memcpy(aligned_buffer, data->src, trans_bytes);
  201. #endif
  202. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  203. mode |= SDHCI_TRNS_DMA;
  204. #endif
  205. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  206. data->blocksize),
  207. SDHCI_BLOCK_SIZE);
  208. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  209. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  210. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  211. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  212. }
  213. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  214. #ifdef CONFIG_MMC_SDMA
  215. flush_cache(start_addr, trans_bytes);
  216. #endif
  217. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  218. start = get_timer(0);
  219. do {
  220. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  221. if (stat & SDHCI_INT_ERROR)
  222. break;
  223. } while (((stat & mask) != mask) &&
  224. (get_timer(start) < CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT));
  225. if (get_timer(start) >= CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT) {
  226. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
  227. return 0;
  228. else {
  229. printf("%s: Timeout for status update!\n", __func__);
  230. return TIMEOUT;
  231. }
  232. }
  233. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  234. sdhci_cmd_done(host, cmd);
  235. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  236. } else
  237. ret = -1;
  238. if (!ret && data)
  239. ret = sdhci_transfer_data(host, data, start_addr);
  240. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  241. udelay(1000);
  242. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  243. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  244. if (!ret) {
  245. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  246. !is_aligned && (data->flags == MMC_DATA_READ))
  247. memcpy(data->dest, aligned_buffer, trans_bytes);
  248. return 0;
  249. }
  250. sdhci_reset(host, SDHCI_RESET_CMD);
  251. sdhci_reset(host, SDHCI_RESET_DATA);
  252. if (stat & SDHCI_INT_TIMEOUT)
  253. return TIMEOUT;
  254. else
  255. return COMM_ERR;
  256. }
  257. static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  258. {
  259. struct sdhci_host *host = mmc->priv;
  260. unsigned int div, clk, timeout, reg;
  261. /* Wait max 20 ms */
  262. timeout = 200;
  263. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  264. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  265. if (timeout == 0) {
  266. printf("%s: Timeout to wait cmd & data inhibit\n",
  267. __func__);
  268. return -1;
  269. }
  270. timeout--;
  271. udelay(100);
  272. }
  273. reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  274. reg &= ~SDHCI_CLOCK_CARD_EN;
  275. sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
  276. if (clock == 0)
  277. return 0;
  278. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  279. /* Version 3.00 divisors must be a multiple of 2. */
  280. if (mmc->cfg->f_max <= clock)
  281. div = 1;
  282. else {
  283. for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
  284. if ((mmc->cfg->f_max / div) <= clock)
  285. break;
  286. }
  287. }
  288. } else {
  289. /* Version 2.00 divisors must be a power of 2. */
  290. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  291. if ((mmc->cfg->f_max / div) <= clock)
  292. break;
  293. }
  294. }
  295. div >>= 1;
  296. if (host->set_clock)
  297. host->set_clock(host->index, div);
  298. clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  299. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  300. << SDHCI_DIVIDER_HI_SHIFT;
  301. clk |= SDHCI_CLOCK_INT_EN;
  302. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  303. /* Wait max 20 ms */
  304. timeout = 20;
  305. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  306. & SDHCI_CLOCK_INT_STABLE)) {
  307. if (timeout == 0) {
  308. printf("%s: Internal clock never stabilised.\n",
  309. __func__);
  310. return -1;
  311. }
  312. timeout--;
  313. udelay(1000);
  314. }
  315. clk |= SDHCI_CLOCK_CARD_EN;
  316. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  317. return 0;
  318. }
  319. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  320. {
  321. u8 pwr = 0;
  322. if (power != (unsigned short)-1) {
  323. switch (1 << power) {
  324. case MMC_VDD_165_195:
  325. pwr = SDHCI_POWER_180;
  326. break;
  327. case MMC_VDD_29_30:
  328. case MMC_VDD_30_31:
  329. pwr = SDHCI_POWER_300;
  330. break;
  331. case MMC_VDD_32_33:
  332. case MMC_VDD_33_34:
  333. pwr = SDHCI_POWER_330;
  334. break;
  335. }
  336. }
  337. if (pwr == 0) {
  338. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  339. return;
  340. }
  341. if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
  342. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  343. pwr |= SDHCI_POWER_ON;
  344. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  345. }
  346. static void sdhci_set_ios(struct mmc *mmc)
  347. {
  348. u32 ctrl;
  349. struct sdhci_host *host = mmc->priv;
  350. if (host->set_control_reg)
  351. host->set_control_reg(host);
  352. if (mmc->clock != host->clock)
  353. sdhci_set_clock(mmc, mmc->clock);
  354. /* Set bus width */
  355. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  356. if (mmc->bus_width == 8) {
  357. ctrl &= ~SDHCI_CTRL_4BITBUS;
  358. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  359. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  360. ctrl |= SDHCI_CTRL_8BITBUS;
  361. } else {
  362. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  363. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  364. ctrl &= ~SDHCI_CTRL_8BITBUS;
  365. if (mmc->bus_width == 4)
  366. ctrl |= SDHCI_CTRL_4BITBUS;
  367. else
  368. ctrl &= ~SDHCI_CTRL_4BITBUS;
  369. }
  370. if (mmc->clock > 26000000)
  371. ctrl |= SDHCI_CTRL_HISPD;
  372. else
  373. ctrl &= ~SDHCI_CTRL_HISPD;
  374. if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
  375. ctrl &= ~SDHCI_CTRL_HISPD;
  376. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  377. }
  378. static int sdhci_init(struct mmc *mmc)
  379. {
  380. struct sdhci_host *host = mmc->priv;
  381. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
  382. aligned_buffer = memalign(8, 512*1024);
  383. if (!aligned_buffer) {
  384. printf("%s: Aligned buffer alloc failed!!!\n",
  385. __func__);
  386. return -1;
  387. }
  388. }
  389. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  390. if (host->quirks & SDHCI_QUIRK_NO_CD) {
  391. #if defined(CONFIG_PIC32_SDHCI)
  392. /* PIC32 SDHCI CD errata:
  393. * - set CD_TEST and clear CD_TEST_INS bit
  394. */
  395. sdhci_writeb(host, SDHCI_CTRL_CD_TEST, SDHCI_HOST_CONTROL);
  396. #else
  397. unsigned int status;
  398. sdhci_writeb(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
  399. SDHCI_HOST_CONTROL);
  400. status = sdhci_readl(host, SDHCI_PRESENT_STATE);
  401. while ((!(status & SDHCI_CARD_PRESENT)) ||
  402. (!(status & SDHCI_CARD_STATE_STABLE)) ||
  403. (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
  404. status = sdhci_readl(host, SDHCI_PRESENT_STATE);
  405. #endif
  406. }
  407. /* Enable only interrupts served by the SD controller */
  408. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  409. SDHCI_INT_ENABLE);
  410. /* Mask all sdhci interrupt sources */
  411. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  412. return 0;
  413. }
  414. static const struct mmc_ops sdhci_ops = {
  415. .send_cmd = sdhci_send_command,
  416. .set_ios = sdhci_set_ios,
  417. .init = sdhci_init,
  418. };
  419. int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
  420. {
  421. unsigned int caps;
  422. host->cfg.name = host->name;
  423. host->cfg.ops = &sdhci_ops;
  424. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  425. #ifdef CONFIG_MMC_SDMA
  426. if (!(caps & SDHCI_CAN_DO_SDMA)) {
  427. printf("%s: Your controller doesn't support SDMA!!\n",
  428. __func__);
  429. return -1;
  430. }
  431. #endif
  432. if (max_clk)
  433. host->cfg.f_max = max_clk;
  434. else {
  435. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  436. host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
  437. >> SDHCI_CLOCK_BASE_SHIFT;
  438. else
  439. host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK)
  440. >> SDHCI_CLOCK_BASE_SHIFT;
  441. host->cfg.f_max *= 1000000;
  442. }
  443. if (host->cfg.f_max == 0) {
  444. printf("%s: Hardware doesn't specify base clock frequency\n",
  445. __func__);
  446. return -1;
  447. }
  448. if (min_clk)
  449. host->cfg.f_min = min_clk;
  450. else {
  451. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  452. host->cfg.f_min = host->cfg.f_max /
  453. SDHCI_MAX_DIV_SPEC_300;
  454. else
  455. host->cfg.f_min = host->cfg.f_max /
  456. SDHCI_MAX_DIV_SPEC_200;
  457. }
  458. host->cfg.voltages = 0;
  459. if (caps & SDHCI_CAN_VDD_330)
  460. host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  461. if (caps & SDHCI_CAN_VDD_300)
  462. host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  463. if (caps & SDHCI_CAN_VDD_180)
  464. host->cfg.voltages |= MMC_VDD_165_195;
  465. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  466. host->cfg.voltages |= host->voltages;
  467. host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
  468. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  469. if (caps & SDHCI_CAN_DO_8BIT)
  470. host->cfg.host_caps |= MMC_MODE_8BIT;
  471. }
  472. if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
  473. host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz);
  474. if (host->host_caps)
  475. host->cfg.host_caps |= host->host_caps;
  476. host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  477. sdhci_reset(host, SDHCI_RESET_ALL);
  478. host->mmc = mmc_create(&host->cfg, host);
  479. if (host->mmc == NULL) {
  480. printf("%s: mmc create fail!\n", __func__);
  481. return -1;
  482. }
  483. return 0;
  484. }