mxsmmc.c 11 KB

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  1. /*
  2. * Freescale i.MX28 SSP MMC driver
  3. *
  4. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  5. * on behalf of DENX Software Engineering GmbH
  6. *
  7. * Based on code from LTIB:
  8. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  9. * Terry Lv
  10. *
  11. * Copyright 2007, Freescale Semiconductor, Inc
  12. * Andy Fleming
  13. *
  14. * Based vaguely on the pxa mmc code:
  15. * (C) Copyright 2003
  16. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  17. *
  18. * SPDX-License-Identifier: GPL-2.0+
  19. */
  20. #include <common.h>
  21. #include <malloc.h>
  22. #include <mmc.h>
  23. #include <asm/errno.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/clock.h>
  26. #include <asm/arch/imx-regs.h>
  27. #include <asm/arch/sys_proto.h>
  28. #include <asm/imx-common/dma.h>
  29. #include <bouncebuf.h>
  30. struct mxsmmc_priv {
  31. int id;
  32. struct mxs_ssp_regs *regs;
  33. uint32_t buswidth;
  34. int (*mmc_is_wp)(int);
  35. int (*mmc_cd)(int);
  36. struct mxs_dma_desc *desc;
  37. struct mmc_config cfg; /* mmc configuration */
  38. };
  39. #define MXSMMC_MAX_TIMEOUT 10000
  40. #define MXSMMC_SMALL_TRANSFER 512
  41. static int mxsmmc_cd(struct mxsmmc_priv *priv)
  42. {
  43. struct mxs_ssp_regs *ssp_regs = priv->regs;
  44. if (priv->mmc_cd)
  45. return priv->mmc_cd(priv->id);
  46. return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
  47. }
  48. static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
  49. {
  50. struct mxs_ssp_regs *ssp_regs = priv->regs;
  51. uint32_t *data_ptr;
  52. int timeout = MXSMMC_MAX_TIMEOUT;
  53. uint32_t reg;
  54. uint32_t data_count = data->blocksize * data->blocks;
  55. if (data->flags & MMC_DATA_READ) {
  56. data_ptr = (uint32_t *)data->dest;
  57. while (data_count && --timeout) {
  58. reg = readl(&ssp_regs->hw_ssp_status);
  59. if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
  60. *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
  61. data_count -= 4;
  62. timeout = MXSMMC_MAX_TIMEOUT;
  63. } else
  64. udelay(1000);
  65. }
  66. } else {
  67. data_ptr = (uint32_t *)data->src;
  68. timeout *= 100;
  69. while (data_count && --timeout) {
  70. reg = readl(&ssp_regs->hw_ssp_status);
  71. if (!(reg & SSP_STATUS_FIFO_FULL)) {
  72. writel(*data_ptr++, &ssp_regs->hw_ssp_data);
  73. data_count -= 4;
  74. timeout = MXSMMC_MAX_TIMEOUT;
  75. } else
  76. udelay(1000);
  77. }
  78. }
  79. return timeout ? 0 : COMM_ERR;
  80. }
  81. static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
  82. {
  83. uint32_t data_count = data->blocksize * data->blocks;
  84. int dmach;
  85. struct mxs_dma_desc *desc = priv->desc;
  86. void *addr;
  87. unsigned int flags;
  88. struct bounce_buffer bbstate;
  89. memset(desc, 0, sizeof(struct mxs_dma_desc));
  90. desc->address = (dma_addr_t)desc;
  91. if (data->flags & MMC_DATA_READ) {
  92. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
  93. addr = data->dest;
  94. flags = GEN_BB_WRITE;
  95. } else {
  96. priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
  97. addr = (void *)data->src;
  98. flags = GEN_BB_READ;
  99. }
  100. bounce_buffer_start(&bbstate, addr, data_count, flags);
  101. priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
  102. priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
  103. (data_count << MXS_DMA_DESC_BYTES_OFFSET);
  104. dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
  105. mxs_dma_desc_append(dmach, priv->desc);
  106. if (mxs_dma_go(dmach)) {
  107. bounce_buffer_stop(&bbstate);
  108. return COMM_ERR;
  109. }
  110. bounce_buffer_stop(&bbstate);
  111. return 0;
  112. }
  113. /*
  114. * Sends a command out on the bus. Takes the mmc pointer,
  115. * a command pointer, and an optional data pointer.
  116. */
  117. static int
  118. mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  119. {
  120. struct mxsmmc_priv *priv = mmc->priv;
  121. struct mxs_ssp_regs *ssp_regs = priv->regs;
  122. uint32_t reg;
  123. int timeout;
  124. uint32_t ctrl0;
  125. int ret;
  126. debug("MMC%d: CMD%d\n", mmc->block_dev.devnum, cmd->cmdidx);
  127. /* Check bus busy */
  128. timeout = MXSMMC_MAX_TIMEOUT;
  129. while (--timeout) {
  130. udelay(1000);
  131. reg = readl(&ssp_regs->hw_ssp_status);
  132. if (!(reg &
  133. (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
  134. SSP_STATUS_CMD_BUSY))) {
  135. break;
  136. }
  137. }
  138. if (!timeout) {
  139. printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.devnum);
  140. return TIMEOUT;
  141. }
  142. /* See if card is present */
  143. if (!mxsmmc_cd(priv)) {
  144. printf("MMC%d: No card detected!\n", mmc->block_dev.devnum);
  145. return NO_CARD_ERR;
  146. }
  147. /* Start building CTRL0 contents */
  148. ctrl0 = priv->buswidth;
  149. /* Set up command */
  150. if (!(cmd->resp_type & MMC_RSP_CRC))
  151. ctrl0 |= SSP_CTRL0_IGNORE_CRC;
  152. if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
  153. ctrl0 |= SSP_CTRL0_GET_RESP;
  154. if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
  155. ctrl0 |= SSP_CTRL0_LONG_RESP;
  156. if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
  157. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
  158. else
  159. writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
  160. /* Command index */
  161. reg = readl(&ssp_regs->hw_ssp_cmd0);
  162. reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
  163. reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
  164. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  165. reg |= SSP_CMD0_APPEND_8CYC;
  166. writel(reg, &ssp_regs->hw_ssp_cmd0);
  167. /* Command argument */
  168. writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
  169. /* Set up data */
  170. if (data) {
  171. /* READ or WRITE */
  172. if (data->flags & MMC_DATA_READ) {
  173. ctrl0 |= SSP_CTRL0_READ;
  174. } else if (priv->mmc_is_wp &&
  175. priv->mmc_is_wp(mmc->block_dev.devnum)) {
  176. printf("MMC%d: Can not write a locked card!\n",
  177. mmc->block_dev.devnum);
  178. return UNUSABLE_ERR;
  179. }
  180. ctrl0 |= SSP_CTRL0_DATA_XFER;
  181. reg = data->blocksize * data->blocks;
  182. #if defined(CONFIG_MX23)
  183. ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
  184. clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
  185. SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
  186. ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
  187. ((ffs(data->blocksize) - 1) <<
  188. SSP_CMD0_BLOCK_SIZE_OFFSET));
  189. #elif defined(CONFIG_MX28)
  190. writel(reg, &ssp_regs->hw_ssp_xfer_size);
  191. reg = ((data->blocks - 1) <<
  192. SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
  193. ((ffs(data->blocksize) - 1) <<
  194. SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
  195. writel(reg, &ssp_regs->hw_ssp_block_size);
  196. #endif
  197. }
  198. /* Kick off the command */
  199. ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
  200. writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
  201. /* Wait for the command to complete */
  202. timeout = MXSMMC_MAX_TIMEOUT;
  203. while (--timeout) {
  204. udelay(1000);
  205. reg = readl(&ssp_regs->hw_ssp_status);
  206. if (!(reg & SSP_STATUS_CMD_BUSY))
  207. break;
  208. }
  209. if (!timeout) {
  210. printf("MMC%d: Command %d busy\n",
  211. mmc->block_dev.devnum, cmd->cmdidx);
  212. return TIMEOUT;
  213. }
  214. /* Check command timeout */
  215. if (reg & SSP_STATUS_RESP_TIMEOUT) {
  216. printf("MMC%d: Command %d timeout (status 0x%08x)\n",
  217. mmc->block_dev.devnum, cmd->cmdidx, reg);
  218. return TIMEOUT;
  219. }
  220. /* Check command errors */
  221. if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
  222. printf("MMC%d: Command %d error (status 0x%08x)!\n",
  223. mmc->block_dev.devnum, cmd->cmdidx, reg);
  224. return COMM_ERR;
  225. }
  226. /* Copy response to response buffer */
  227. if (cmd->resp_type & MMC_RSP_136) {
  228. cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
  229. cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
  230. cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
  231. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
  232. } else
  233. cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
  234. /* Return if no data to process */
  235. if (!data)
  236. return 0;
  237. if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
  238. ret = mxsmmc_send_cmd_pio(priv, data);
  239. if (ret) {
  240. printf("MMC%d: Data timeout with command %d "
  241. "(status 0x%08x)!\n",
  242. mmc->block_dev.devnum, cmd->cmdidx, reg);
  243. return ret;
  244. }
  245. } else {
  246. ret = mxsmmc_send_cmd_dma(priv, data);
  247. if (ret) {
  248. printf("MMC%d: DMA transfer failed\n",
  249. mmc->block_dev.devnum);
  250. return ret;
  251. }
  252. }
  253. /* Check data errors */
  254. reg = readl(&ssp_regs->hw_ssp_status);
  255. if (reg &
  256. (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
  257. SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
  258. printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
  259. mmc->block_dev.devnum, cmd->cmdidx, reg);
  260. return COMM_ERR;
  261. }
  262. return 0;
  263. }
  264. static void mxsmmc_set_ios(struct mmc *mmc)
  265. {
  266. struct mxsmmc_priv *priv = mmc->priv;
  267. struct mxs_ssp_regs *ssp_regs = priv->regs;
  268. /* Set the clock speed */
  269. if (mmc->clock)
  270. mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
  271. switch (mmc->bus_width) {
  272. case 1:
  273. priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
  274. break;
  275. case 4:
  276. priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
  277. break;
  278. case 8:
  279. priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
  280. break;
  281. }
  282. /* Set the bus width */
  283. clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
  284. SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
  285. debug("MMC%d: Set %d bits bus width\n",
  286. mmc->block_dev.devnum, mmc->bus_width);
  287. }
  288. static int mxsmmc_init(struct mmc *mmc)
  289. {
  290. struct mxsmmc_priv *priv = mmc->priv;
  291. struct mxs_ssp_regs *ssp_regs = priv->regs;
  292. /* Reset SSP */
  293. mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
  294. /* Reconfigure the SSP block for MMC operation */
  295. writel(SSP_CTRL1_SSP_MODE_SD_MMC |
  296. SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
  297. SSP_CTRL1_DMA_ENABLE |
  298. SSP_CTRL1_POLARITY |
  299. SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  300. SSP_CTRL1_DATA_CRC_IRQ_EN |
  301. SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  302. SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  303. SSP_CTRL1_RESP_ERR_IRQ_EN,
  304. &ssp_regs->hw_ssp_ctrl1_set);
  305. /* Set initial bit clock 400 KHz */
  306. mxs_set_ssp_busclock(priv->id, 400);
  307. /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
  308. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
  309. udelay(200);
  310. writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
  311. return 0;
  312. }
  313. static const struct mmc_ops mxsmmc_ops = {
  314. .send_cmd = mxsmmc_send_cmd,
  315. .set_ios = mxsmmc_set_ios,
  316. .init = mxsmmc_init,
  317. };
  318. int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
  319. {
  320. struct mmc *mmc = NULL;
  321. struct mxsmmc_priv *priv = NULL;
  322. int ret;
  323. const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
  324. if (!mxs_ssp_bus_id_valid(id))
  325. return -ENODEV;
  326. priv = malloc(sizeof(struct mxsmmc_priv));
  327. if (!priv)
  328. return -ENOMEM;
  329. priv->desc = mxs_dma_desc_alloc();
  330. if (!priv->desc) {
  331. free(priv);
  332. return -ENOMEM;
  333. }
  334. ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
  335. if (ret)
  336. return ret;
  337. priv->mmc_is_wp = wp;
  338. priv->mmc_cd = cd;
  339. priv->id = id;
  340. priv->regs = mxs_ssp_regs_by_bus(id);
  341. priv->cfg.name = "MXS MMC";
  342. priv->cfg.ops = &mxsmmc_ops;
  343. priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  344. priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
  345. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  346. /*
  347. * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
  348. * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
  349. * CLOCK_DIVIDE has to be an even value from 2 to 254, and
  350. * CLOCK_RATE could be any integer from 0 to 255.
  351. */
  352. priv->cfg.f_min = 400000;
  353. priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
  354. priv->cfg.b_max = 0x20;
  355. mmc = mmc_create(&priv->cfg, priv);
  356. if (mmc == NULL) {
  357. mxs_dma_desc_free(priv->desc);
  358. free(priv);
  359. return -ENOMEM;
  360. }
  361. return 0;
  362. }