tsec.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale Three Speed Ethernet Controller driver
  4. *
  5. * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2003, Motorola, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <command.h>
  15. #include <tsec.h>
  16. #include <fsl_mdio.h>
  17. #include <linux/errno.h>
  18. #include <asm/processor.h>
  19. #include <asm/io.h>
  20. #ifndef CONFIG_DM_ETH
  21. /* Default initializations for TSEC controllers. */
  22. static struct tsec_info_struct tsec_info[] = {
  23. #ifdef CONFIG_TSEC1
  24. STD_TSEC_INFO(1), /* TSEC1 */
  25. #endif
  26. #ifdef CONFIG_TSEC2
  27. STD_TSEC_INFO(2), /* TSEC2 */
  28. #endif
  29. #ifdef CONFIG_MPC85XX_FEC
  30. {
  31. .regs = TSEC_GET_REGS(2, 0x2000),
  32. .devname = CONFIG_MPC85XX_FEC_NAME,
  33. .phyaddr = FEC_PHY_ADDR,
  34. .flags = FEC_FLAGS,
  35. .mii_devname = DEFAULT_MII_NAME
  36. }, /* FEC */
  37. #endif
  38. #ifdef CONFIG_TSEC3
  39. STD_TSEC_INFO(3), /* TSEC3 */
  40. #endif
  41. #ifdef CONFIG_TSEC4
  42. STD_TSEC_INFO(4), /* TSEC4 */
  43. #endif
  44. };
  45. #endif /* CONFIG_DM_ETH */
  46. #define TBIANA_SETTINGS ( \
  47. TBIANA_ASYMMETRIC_PAUSE \
  48. | TBIANA_SYMMETRIC_PAUSE \
  49. | TBIANA_FULL_DUPLEX \
  50. )
  51. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  52. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  53. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  54. TBICR_PHY_RESET \
  55. | TBICR_ANEG_ENABLE \
  56. | TBICR_FULL_DUPLEX \
  57. | TBICR_SPEED1_SET \
  58. )
  59. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  60. /* Configure the TBI for SGMII operation */
  61. static void tsec_configure_serdes(struct tsec_private *priv)
  62. {
  63. /*
  64. * Access TBI PHY registers at given TSEC register offset as opposed
  65. * to the register offset used for external PHY accesses
  66. */
  67. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  68. 0, TBI_ANA, TBIANA_SETTINGS);
  69. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  70. 0, TBI_TBICON, TBICON_CLK_SELECT);
  71. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  72. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  73. }
  74. /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
  75. * and this is the ethernet-crc method needed for TSEC -- and perhaps
  76. * some other adapter -- hash tables
  77. */
  78. #define CRCPOLY_LE 0xedb88320
  79. static u32 ether_crc(size_t len, unsigned char const *p)
  80. {
  81. int i;
  82. u32 crc;
  83. crc = ~0;
  84. while (len--) {
  85. crc ^= *p++;
  86. for (i = 0; i < 8; i++)
  87. crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
  88. }
  89. /* an reverse the bits, cuz of way they arrive -- last-first */
  90. crc = (crc >> 16) | (crc << 16);
  91. crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
  92. crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
  93. crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
  94. crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
  95. return crc;
  96. }
  97. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  98. /* Set the appropriate hash bit for the given addr */
  99. /*
  100. * The algorithm works like so:
  101. * 1) Take the Destination Address (ie the multicast address), and
  102. * do a CRC on it (little endian), and reverse the bits of the
  103. * result.
  104. * 2) Use the 8 most significant bits as a hash into a 256-entry
  105. * table. The table is controlled through 8 32-bit registers:
  106. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  107. * 255. This means that the 3 most significant bits in the
  108. * hash index which gaddr register to use, and the 5 other bits
  109. * indicate which bit (assuming an IBM numbering scheme, which
  110. * for PowerPC (tm) is usually the case) in the register holds
  111. * the entry.
  112. */
  113. #ifndef CONFIG_DM_ETH
  114. static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
  115. int join)
  116. #else
  117. static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
  118. #endif
  119. {
  120. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  121. struct tsec __iomem *regs = priv->regs;
  122. u32 result, value;
  123. u8 whichbit, whichreg;
  124. result = ether_crc(MAC_ADDR_LEN, mcast_mac);
  125. whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
  126. whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
  127. value = BIT(31 - whichbit);
  128. if (join)
  129. setbits_be32(&regs->hash.gaddr0 + whichreg, value);
  130. else
  131. clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
  132. return 0;
  133. }
  134. /*
  135. * Initialized required registers to appropriate values, zeroing
  136. * those we don't care about (unless zero is bad, in which case,
  137. * choose a more appropriate value)
  138. */
  139. static void init_registers(struct tsec __iomem *regs)
  140. {
  141. /* Clear IEVENT */
  142. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  143. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  144. out_be32(&regs->hash.iaddr0, 0);
  145. out_be32(&regs->hash.iaddr1, 0);
  146. out_be32(&regs->hash.iaddr2, 0);
  147. out_be32(&regs->hash.iaddr3, 0);
  148. out_be32(&regs->hash.iaddr4, 0);
  149. out_be32(&regs->hash.iaddr5, 0);
  150. out_be32(&regs->hash.iaddr6, 0);
  151. out_be32(&regs->hash.iaddr7, 0);
  152. out_be32(&regs->hash.gaddr0, 0);
  153. out_be32(&regs->hash.gaddr1, 0);
  154. out_be32(&regs->hash.gaddr2, 0);
  155. out_be32(&regs->hash.gaddr3, 0);
  156. out_be32(&regs->hash.gaddr4, 0);
  157. out_be32(&regs->hash.gaddr5, 0);
  158. out_be32(&regs->hash.gaddr6, 0);
  159. out_be32(&regs->hash.gaddr7, 0);
  160. out_be32(&regs->rctrl, 0x00000000);
  161. /* Init RMON mib registers */
  162. memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
  163. out_be32(&regs->rmon.cam1, 0xffffffff);
  164. out_be32(&regs->rmon.cam2, 0xffffffff);
  165. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  166. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  167. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  168. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  169. }
  170. /*
  171. * Configure maccfg2 based on negotiated speed and duplex
  172. * reported by PHY handling code
  173. */
  174. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  175. {
  176. struct tsec __iomem *regs = priv->regs;
  177. u32 ecntrl, maccfg2;
  178. if (!phydev->link) {
  179. printf("%s: No link.\n", phydev->dev->name);
  180. return;
  181. }
  182. /* clear all bits relative with interface mode */
  183. ecntrl = in_be32(&regs->ecntrl);
  184. ecntrl &= ~ECNTRL_R100;
  185. maccfg2 = in_be32(&regs->maccfg2);
  186. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  187. if (phydev->duplex)
  188. maccfg2 |= MACCFG2_FULL_DUPLEX;
  189. switch (phydev->speed) {
  190. case 1000:
  191. maccfg2 |= MACCFG2_GMII;
  192. break;
  193. case 100:
  194. case 10:
  195. maccfg2 |= MACCFG2_MII;
  196. /*
  197. * Set R100 bit in all modes although
  198. * it is only used in RGMII mode
  199. */
  200. if (phydev->speed == 100)
  201. ecntrl |= ECNTRL_R100;
  202. break;
  203. default:
  204. printf("%s: Speed was bad\n", phydev->dev->name);
  205. break;
  206. }
  207. out_be32(&regs->ecntrl, ecntrl);
  208. out_be32(&regs->maccfg2, maccfg2);
  209. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  210. (phydev->duplex) ? "full" : "half",
  211. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  212. }
  213. /*
  214. * This returns the status bits of the device. The return value
  215. * is never checked, and this is what the 8260 driver did, so we
  216. * do the same. Presumably, this would be zero if there were no
  217. * errors
  218. */
  219. #ifndef CONFIG_DM_ETH
  220. static int tsec_send(struct eth_device *dev, void *packet, int length)
  221. #else
  222. static int tsec_send(struct udevice *dev, void *packet, int length)
  223. #endif
  224. {
  225. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  226. struct tsec __iomem *regs = priv->regs;
  227. u16 status;
  228. int result = 0;
  229. int i;
  230. /* Find an empty buffer descriptor */
  231. for (i = 0;
  232. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  233. i++) {
  234. if (i >= TOUT_LOOP) {
  235. debug("%s: tsec: tx buffers full\n", dev->name);
  236. return result;
  237. }
  238. }
  239. out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
  240. out_be16(&priv->txbd[priv->tx_idx].length, length);
  241. status = in_be16(&priv->txbd[priv->tx_idx].status);
  242. out_be16(&priv->txbd[priv->tx_idx].status, status |
  243. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
  244. /* Tell the DMA to go */
  245. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  246. /* Wait for buffer to be transmitted */
  247. for (i = 0;
  248. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  249. i++) {
  250. if (i >= TOUT_LOOP) {
  251. debug("%s: tsec: tx error\n", dev->name);
  252. return result;
  253. }
  254. }
  255. priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
  256. result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
  257. return result;
  258. }
  259. #ifndef CONFIG_DM_ETH
  260. static int tsec_recv(struct eth_device *dev)
  261. {
  262. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  263. struct tsec __iomem *regs = priv->regs;
  264. while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  265. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  266. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  267. uchar *packet = net_rx_packets[priv->rx_idx];
  268. /* Send the packet up if there were no errors */
  269. if (!(status & RXBD_STATS))
  270. net_process_received_packet(packet, length - 4);
  271. else
  272. printf("Got error %x\n", (status & RXBD_STATS));
  273. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  274. status = RXBD_EMPTY;
  275. /* Set the wrap bit if this is the last element in the list */
  276. if ((priv->rx_idx + 1) == PKTBUFSRX)
  277. status |= RXBD_WRAP;
  278. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  279. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  280. }
  281. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  282. out_be32(&regs->ievent, IEVENT_BSY);
  283. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  284. }
  285. return -1;
  286. }
  287. #else
  288. static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
  289. {
  290. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  291. struct tsec __iomem *regs = priv->regs;
  292. int ret = -1;
  293. if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  294. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  295. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  296. u32 buf;
  297. /* Send the packet up if there were no errors */
  298. if (!(status & RXBD_STATS)) {
  299. buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
  300. *packetp = (uchar *)buf;
  301. ret = length - 4;
  302. } else {
  303. printf("Got error %x\n", (status & RXBD_STATS));
  304. }
  305. }
  306. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  307. out_be32(&regs->ievent, IEVENT_BSY);
  308. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  309. }
  310. return ret;
  311. }
  312. static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
  313. {
  314. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  315. u16 status;
  316. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  317. status = RXBD_EMPTY;
  318. /* Set the wrap bit if this is the last element in the list */
  319. if ((priv->rx_idx + 1) == PKTBUFSRX)
  320. status |= RXBD_WRAP;
  321. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  322. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  323. return 0;
  324. }
  325. #endif
  326. /* Stop the interface */
  327. #ifndef CONFIG_DM_ETH
  328. static void tsec_halt(struct eth_device *dev)
  329. #else
  330. static void tsec_halt(struct udevice *dev)
  331. #endif
  332. {
  333. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  334. struct tsec __iomem *regs = priv->regs;
  335. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  336. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  337. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  338. != (IEVENT_GRSC | IEVENT_GTSC))
  339. ;
  340. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  341. /* Shut down the PHY, as needed */
  342. phy_shutdown(priv->phydev);
  343. }
  344. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  345. /*
  346. * When MACCFG1[Rx_EN] is enabled during system boot as part
  347. * of the eTSEC port initialization sequence,
  348. * the eTSEC Rx logic may not be properly initialized.
  349. */
  350. void redundant_init(struct tsec_private *priv)
  351. {
  352. struct tsec __iomem *regs = priv->regs;
  353. uint t, count = 0;
  354. int fail = 1;
  355. static const u8 pkt[] = {
  356. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  357. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  358. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  359. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  360. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  361. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  362. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  363. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  364. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  365. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  366. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  367. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  368. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  369. 0x71, 0x72};
  370. /* Enable promiscuous mode */
  371. setbits_be32(&regs->rctrl, 0x8);
  372. /* Enable loopback mode */
  373. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  374. /* Enable transmit and receive */
  375. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  376. /* Tell the DMA it is clear to go */
  377. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  378. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  379. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  380. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  381. do {
  382. u16 status;
  383. tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
  384. /* Wait for buffer to be received */
  385. for (t = 0;
  386. in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
  387. t++) {
  388. if (t >= 10 * TOUT_LOOP) {
  389. printf("%s: tsec: rx error\n", priv->dev->name);
  390. break;
  391. }
  392. }
  393. if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
  394. fail = 0;
  395. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  396. status = RXBD_EMPTY;
  397. if ((priv->rx_idx + 1) == PKTBUFSRX)
  398. status |= RXBD_WRAP;
  399. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  400. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  401. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  402. out_be32(&regs->ievent, IEVENT_BSY);
  403. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  404. }
  405. if (fail) {
  406. printf("loopback recv packet error!\n");
  407. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  408. udelay(1000);
  409. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  410. }
  411. } while ((count++ < 4) && (fail == 1));
  412. if (fail)
  413. panic("eTSEC init fail!\n");
  414. /* Disable promiscuous mode */
  415. clrbits_be32(&regs->rctrl, 0x8);
  416. /* Disable loopback mode */
  417. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  418. }
  419. #endif
  420. /*
  421. * Set up the buffers and their descriptors, and bring up the
  422. * interface
  423. */
  424. static void startup_tsec(struct tsec_private *priv)
  425. {
  426. struct tsec __iomem *regs = priv->regs;
  427. u16 status;
  428. int i;
  429. /* reset the indices to zero */
  430. priv->rx_idx = 0;
  431. priv->tx_idx = 0;
  432. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  433. uint svr;
  434. #endif
  435. /* Point to the buffer descriptors */
  436. out_be32(&regs->tbase, (u32)&priv->txbd[0]);
  437. out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
  438. /* Initialize the Rx Buffer descriptors */
  439. for (i = 0; i < PKTBUFSRX; i++) {
  440. out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
  441. out_be16(&priv->rxbd[i].length, 0);
  442. out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
  443. }
  444. status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
  445. out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
  446. /* Initialize the TX Buffer Descriptors */
  447. for (i = 0; i < TX_BUF_CNT; i++) {
  448. out_be16(&priv->txbd[i].status, 0);
  449. out_be16(&priv->txbd[i].length, 0);
  450. out_be32(&priv->txbd[i].bufptr, 0);
  451. }
  452. status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
  453. out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
  454. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  455. svr = get_svr();
  456. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  457. redundant_init(priv);
  458. #endif
  459. /* Enable Transmit and Receive */
  460. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  461. /* Tell the DMA it is clear to go */
  462. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  463. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  464. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  465. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  466. }
  467. /*
  468. * Initializes data structures and registers for the controller,
  469. * and brings the interface up. Returns the link status, meaning
  470. * that it returns success if the link is up, failure otherwise.
  471. * This allows U-Boot to find the first active controller.
  472. */
  473. #ifndef CONFIG_DM_ETH
  474. static int tsec_init(struct eth_device *dev, bd_t *bd)
  475. #else
  476. static int tsec_init(struct udevice *dev)
  477. #endif
  478. {
  479. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  480. #ifdef CONFIG_DM_ETH
  481. struct eth_pdata *pdata = dev_get_platdata(dev);
  482. #endif
  483. struct tsec __iomem *regs = priv->regs;
  484. u32 tempval;
  485. int ret;
  486. /* Make sure the controller is stopped */
  487. tsec_halt(dev);
  488. /* Init MACCFG2. Defaults to GMII */
  489. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  490. /* Init ECNTRL */
  491. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  492. /*
  493. * Copy the station address into the address registers.
  494. * For a station address of 0x12345678ABCD in transmission
  495. * order (BE), MACnADDR1 is set to 0xCDAB7856 and
  496. * MACnADDR2 is set to 0x34120000.
  497. */
  498. #ifndef CONFIG_DM_ETH
  499. tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
  500. (dev->enetaddr[3] << 8) | dev->enetaddr[2];
  501. #else
  502. tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
  503. (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
  504. #endif
  505. out_be32(&regs->macstnaddr1, tempval);
  506. #ifndef CONFIG_DM_ETH
  507. tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
  508. #else
  509. tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
  510. #endif
  511. out_be32(&regs->macstnaddr2, tempval);
  512. /* Clear out (for the most part) the other registers */
  513. init_registers(regs);
  514. /* Ready the device for tx/rx */
  515. startup_tsec(priv);
  516. /* Start up the PHY */
  517. ret = phy_startup(priv->phydev);
  518. if (ret) {
  519. printf("Could not initialize PHY %s\n",
  520. priv->phydev->dev->name);
  521. return ret;
  522. }
  523. adjust_link(priv, priv->phydev);
  524. /* If there's no link, fail */
  525. return priv->phydev->link ? 0 : -1;
  526. }
  527. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  528. {
  529. struct tsec __iomem *regs = priv->regs;
  530. u32 ecntrl;
  531. ecntrl = in_be32(&regs->ecntrl);
  532. if (ecntrl & ECNTRL_SGMII_MODE)
  533. return PHY_INTERFACE_MODE_SGMII;
  534. if (ecntrl & ECNTRL_TBI_MODE) {
  535. if (ecntrl & ECNTRL_REDUCED_MODE)
  536. return PHY_INTERFACE_MODE_RTBI;
  537. else
  538. return PHY_INTERFACE_MODE_TBI;
  539. }
  540. if (ecntrl & ECNTRL_REDUCED_MODE) {
  541. phy_interface_t interface;
  542. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  543. return PHY_INTERFACE_MODE_RMII;
  544. interface = priv->interface;
  545. /*
  546. * This isn't autodetected, so it must
  547. * be set by the platform code.
  548. */
  549. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  550. interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  551. interface == PHY_INTERFACE_MODE_RGMII_RXID)
  552. return interface;
  553. return PHY_INTERFACE_MODE_RGMII;
  554. }
  555. if (priv->flags & TSEC_GIGABIT)
  556. return PHY_INTERFACE_MODE_GMII;
  557. return PHY_INTERFACE_MODE_MII;
  558. }
  559. /*
  560. * Discover which PHY is attached to the device, and configure it
  561. * properly. If the PHY is not recognized, then return 0
  562. * (failure). Otherwise, return 1
  563. */
  564. static int init_phy(struct tsec_private *priv)
  565. {
  566. struct phy_device *phydev;
  567. struct tsec __iomem *regs = priv->regs;
  568. u32 supported = (SUPPORTED_10baseT_Half |
  569. SUPPORTED_10baseT_Full |
  570. SUPPORTED_100baseT_Half |
  571. SUPPORTED_100baseT_Full);
  572. if (priv->flags & TSEC_GIGABIT)
  573. supported |= SUPPORTED_1000baseT_Full;
  574. /* Assign a Physical address to the TBI */
  575. out_be32(&regs->tbipa, priv->tbiaddr);
  576. priv->interface = tsec_get_interface(priv);
  577. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  578. tsec_configure_serdes(priv);
  579. phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
  580. priv->interface);
  581. if (!phydev)
  582. return 0;
  583. phydev->supported &= supported;
  584. phydev->advertising = phydev->supported;
  585. priv->phydev = phydev;
  586. phy_config(phydev);
  587. return 1;
  588. }
  589. #ifndef CONFIG_DM_ETH
  590. /*
  591. * Initialize device structure. Returns success if PHY
  592. * initialization succeeded (i.e. if it recognizes the PHY)
  593. */
  594. static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
  595. {
  596. struct eth_device *dev;
  597. int i;
  598. struct tsec_private *priv;
  599. dev = (struct eth_device *)malloc(sizeof(*dev));
  600. if (!dev)
  601. return 0;
  602. memset(dev, 0, sizeof(*dev));
  603. priv = (struct tsec_private *)malloc(sizeof(*priv));
  604. if (!priv) {
  605. free(dev);
  606. return 0;
  607. }
  608. priv->regs = tsec_info->regs;
  609. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  610. priv->phyaddr = tsec_info->phyaddr;
  611. priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  612. priv->flags = tsec_info->flags;
  613. strcpy(dev->name, tsec_info->devname);
  614. priv->interface = tsec_info->interface;
  615. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  616. priv->dev = dev;
  617. dev->iobase = 0;
  618. dev->priv = priv;
  619. dev->init = tsec_init;
  620. dev->halt = tsec_halt;
  621. dev->send = tsec_send;
  622. dev->recv = tsec_recv;
  623. dev->mcast = tsec_mcast_addr;
  624. /* Tell U-Boot to get the addr from the env */
  625. for (i = 0; i < 6; i++)
  626. dev->enetaddr[i] = 0;
  627. eth_register(dev);
  628. /* Reset the MAC */
  629. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  630. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  631. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  632. /* Try to initialize PHY here, and return */
  633. return init_phy(priv);
  634. }
  635. /*
  636. * Initialize all the TSEC devices
  637. *
  638. * Returns the number of TSEC devices that were initialized
  639. */
  640. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  641. {
  642. int i;
  643. int count = 0;
  644. for (i = 0; i < num; i++) {
  645. int ret = tsec_initialize(bis, &tsecs[i]);
  646. if (ret > 0)
  647. count += ret;
  648. }
  649. return count;
  650. }
  651. int tsec_standard_init(bd_t *bis)
  652. {
  653. struct fsl_pq_mdio_info info;
  654. info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  655. info.name = DEFAULT_MII_NAME;
  656. fsl_pq_mdio_init(bis, &info);
  657. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  658. }
  659. #else /* CONFIG_DM_ETH */
  660. int tsec_probe(struct udevice *dev)
  661. {
  662. struct tsec_private *priv = dev_get_priv(dev);
  663. struct eth_pdata *pdata = dev_get_platdata(dev);
  664. struct fsl_pq_mdio_info mdio_info;
  665. struct ofnode_phandle_args phandle_args;
  666. u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  667. ofnode parent;
  668. const char *phy_mode;
  669. fdt_addr_t reg;
  670. int ret;
  671. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  672. priv->regs = (struct tsec *)pdata->iobase;
  673. if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  674. &phandle_args)) {
  675. debug("phy-handle does not exist under tsec %s\n", dev->name);
  676. return -ENOENT;
  677. } else {
  678. int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
  679. priv->phyaddr = reg;
  680. }
  681. parent = ofnode_get_parent(phandle_args.node);
  682. if (!ofnode_valid(parent)) {
  683. printf("No parent node for PHY?\n");
  684. return -ENOENT;
  685. }
  686. reg = ofnode_get_addr_index(parent, 0);
  687. priv->phyregs_sgmii = (struct tsec_mii_mng *)
  688. (reg + TSEC_MDIO_REGS_OFFSET);
  689. ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
  690. &phandle_args);
  691. if (ret == 0)
  692. ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
  693. priv->tbiaddr = tbiaddr;
  694. phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
  695. if (phy_mode)
  696. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  697. if (pdata->phy_interface == -1) {
  698. debug("Invalid PHY interface '%s'\n", phy_mode);
  699. return -EINVAL;
  700. }
  701. priv->interface = pdata->phy_interface;
  702. /* Initialize flags */
  703. priv->flags = TSEC_GIGABIT;
  704. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  705. priv->flags |= TSEC_SGMII;
  706. mdio_info.regs = priv->phyregs_sgmii;
  707. mdio_info.name = (char *)dev->name;
  708. ret = fsl_pq_mdio_init(NULL, &mdio_info);
  709. if (ret)
  710. return ret;
  711. /* Reset the MAC */
  712. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  713. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  714. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  715. priv->dev = dev;
  716. priv->bus = miiphy_get_dev_by_name(dev->name);
  717. /* Try to initialize PHY here, and return */
  718. return !init_phy(priv);
  719. }
  720. int tsec_remove(struct udevice *dev)
  721. {
  722. struct tsec_private *priv = dev->priv;
  723. free(priv->phydev);
  724. mdio_unregister(priv->bus);
  725. mdio_free(priv->bus);
  726. return 0;
  727. }
  728. static const struct eth_ops tsec_ops = {
  729. .start = tsec_init,
  730. .send = tsec_send,
  731. .recv = tsec_recv,
  732. .free_pkt = tsec_free_pkt,
  733. .stop = tsec_halt,
  734. .mcast = tsec_mcast_addr,
  735. };
  736. static const struct udevice_id tsec_ids[] = {
  737. { .compatible = "fsl,tsec" },
  738. { }
  739. };
  740. U_BOOT_DRIVER(eth_tsec) = {
  741. .name = "tsec",
  742. .id = UCLASS_ETH,
  743. .of_match = tsec_ids,
  744. .probe = tsec_probe,
  745. .remove = tsec_remove,
  746. .ops = &tsec_ops,
  747. .priv_auto_alloc_size = sizeof(struct tsec_private),
  748. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  749. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  750. };
  751. #endif /* CONFIG_DM_ETH */