stm32mp15xx-dhcor-u-boot.dtsi 2.6 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. *
  5. * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
  6. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. * Copyright (C) 2020 Marek Vasut <marex@denx.de>
  8. */
  9. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  10. #include "stm32mp15-u-boot.dtsi"
  11. #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  12. #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  13. #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  14. / {
  15. u-boot,dm-pre-reloc;
  16. config {
  17. dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  18. dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  19. };
  20. };
  21. &flash0 {
  22. u-boot,dm-spl;
  23. };
  24. &gpiof {
  25. snor-nwp {
  26. gpio-hog;
  27. gpios = <7 0>;
  28. output-high;
  29. line-name = "spi-nor-nwp";
  30. };
  31. };
  32. &i2c4 {
  33. u-boot,dm-pre-reloc;
  34. };
  35. &i2c4_pins_a {
  36. u-boot,dm-pre-reloc;
  37. pins {
  38. u-boot,dm-pre-reloc;
  39. };
  40. };
  41. &pmic {
  42. u-boot,dm-pre-reloc;
  43. };
  44. &qspi {
  45. u-boot,dm-spl;
  46. };
  47. &qspi_clk_pins_a {
  48. u-boot,dm-spl;
  49. pins {
  50. u-boot,dm-spl;
  51. };
  52. };
  53. &qspi_bk1_pins_a {
  54. u-boot,dm-spl;
  55. pins1 {
  56. u-boot,dm-spl;
  57. };
  58. pins2 {
  59. u-boot,dm-spl;
  60. };
  61. };
  62. &rcc {
  63. st,clksrc = <
  64. CLK_MPU_PLL1P
  65. CLK_AXI_PLL2P
  66. CLK_MCU_PLL3P
  67. CLK_PLL12_HSE
  68. CLK_PLL3_HSE
  69. CLK_PLL4_HSE
  70. CLK_RTC_LSE
  71. CLK_MCO1_DISABLED
  72. CLK_MCO2_DISABLED
  73. >;
  74. st,clkdiv = <
  75. 1 /*MPU*/
  76. 0 /*AXI*/
  77. 0 /*MCU*/
  78. 1 /*APB1*/
  79. 1 /*APB2*/
  80. 1 /*APB3*/
  81. 1 /*APB4*/
  82. 2 /*APB5*/
  83. 23 /*RTC*/
  84. 0 /*MCO1*/
  85. 0 /*MCO2*/
  86. >;
  87. st,pkcs = <
  88. CLK_CKPER_HSE
  89. CLK_FMC_ACLK
  90. CLK_QSPI_ACLK
  91. CLK_ETH_DISABLED
  92. CLK_SDMMC12_PLL4P
  93. CLK_DSI_DSIPLL
  94. CLK_STGEN_HSE
  95. CLK_USBPHY_HSE
  96. CLK_SPI2S1_PLL3Q
  97. CLK_SPI2S23_PLL3Q
  98. CLK_SPI45_HSI
  99. CLK_SPI6_HSI
  100. CLK_I2C46_HSI
  101. CLK_SDMMC3_PLL4P
  102. CLK_USBO_USBPHY
  103. CLK_ADC_CKPER
  104. CLK_CEC_LSE
  105. CLK_I2C12_HSI
  106. CLK_I2C35_HSI
  107. CLK_UART1_HSI
  108. CLK_UART24_HSI
  109. CLK_UART35_HSI
  110. CLK_UART6_HSI
  111. CLK_UART78_HSI
  112. CLK_SPDIF_PLL4P
  113. CLK_FDCAN_PLL4R
  114. CLK_SAI1_PLL3Q
  115. CLK_SAI2_PLL3Q
  116. CLK_SAI3_PLL3Q
  117. CLK_SAI4_PLL3Q
  118. CLK_RNG1_LSI
  119. CLK_RNG2_LSI
  120. CLK_LPTIM1_PCLK1
  121. CLK_LPTIM23_PCLK3
  122. CLK_LPTIM45_LSE
  123. >;
  124. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  125. pll2: st,pll@1 {
  126. compatible = "st,stm32mp1-pll";
  127. reg = <1>;
  128. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  129. frac = < 0x1400 >;
  130. u-boot,dm-pre-reloc;
  131. };
  132. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  133. pll3: st,pll@2 {
  134. compatible = "st,stm32mp1-pll";
  135. reg = <2>;
  136. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  137. frac = < 0x1a04 >;
  138. u-boot,dm-pre-reloc;
  139. };
  140. /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
  141. pll4: st,pll@3 {
  142. compatible = "st,stm32mp1-pll";
  143. reg = <3>;
  144. cfg = < 3 98 5 7 5 PQR(1,1,1) >;
  145. u-boot,dm-pre-reloc;
  146. };
  147. };