sdmmc_defs.h 4.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
  4. *
  5. * Copyright (C) 2010 Texas Instruments Incorporated
  6. */
  7. #ifndef _SDMMC_DEFS_H_
  8. #define _SDMMC_DEFS_H_
  9. #include <asm/arch/hardware.h>
  10. /* MMC Control Reg fields */
  11. #define MMCCTL_DATRST (1 << 0)
  12. #define MMCCTL_CMDRST (1 << 1)
  13. #define MMCCTL_WIDTH_4_BIT (1 << 2)
  14. #define MMCCTL_DATEG_DISABLED (0 << 6)
  15. #define MMCCTL_DATEG_RISING (1 << 6)
  16. #define MMCCTL_DATEG_FALLING (2 << 6)
  17. #define MMCCTL_DATEG_BOTH (3 << 6)
  18. #define MMCCTL_PERMDR_LE (0 << 9)
  19. #define MMCCTL_PERMDR_BE (1 << 9)
  20. #define MMCCTL_PERMDX_LE (0 << 10)
  21. #define MMCCTL_PERMDX_BE (1 << 10)
  22. /* MMC Clock Control Reg fields */
  23. #define MMCCLK_CLKEN (1 << 8)
  24. #define MMCCLK_CLKRT_MASK (0xFF << 0)
  25. /* MMC Status Reg0 fields */
  26. #define MMCST0_DATDNE (1 << 0)
  27. #define MMCST0_BSYDNE (1 << 1)
  28. #define MMCST0_RSPDNE (1 << 2)
  29. #define MMCST0_TOUTRD (1 << 3)
  30. #define MMCST0_TOUTRS (1 << 4)
  31. #define MMCST0_CRCWR (1 << 5)
  32. #define MMCST0_CRCRD (1 << 6)
  33. #define MMCST0_CRCRS (1 << 7)
  34. #define MMCST0_DXRDY (1 << 9)
  35. #define MMCST0_DRRDY (1 << 10)
  36. #define MMCST0_DATED (1 << 11)
  37. #define MMCST0_TRNDNE (1 << 12)
  38. #define MMCST0_ERR_MASK (0x00F8)
  39. /* MMC Status Reg1 fields */
  40. #define MMCST1_BUSY (1 << 0)
  41. #define MMCST1_CLKSTP (1 << 1)
  42. #define MMCST1_DXEMP (1 << 2)
  43. #define MMCST1_DRFUL (1 << 3)
  44. #define MMCST1_DAT3ST (1 << 4)
  45. #define MMCST1_FIFOEMP (1 << 5)
  46. #define MMCST1_FIFOFUL (1 << 6)
  47. /* MMC INT Mask Reg fields */
  48. #define MMCIM_EDATDNE (1 << 0)
  49. #define MMCIM_EBSYDNE (1 << 1)
  50. #define MMCIM_ERSPDNE (1 << 2)
  51. #define MMCIM_ETOUTRD (1 << 3)
  52. #define MMCIM_ETOUTRS (1 << 4)
  53. #define MMCIM_ECRCWR (1 << 5)
  54. #define MMCIM_ECRCRD (1 << 6)
  55. #define MMCIM_ECRCRS (1 << 7)
  56. #define MMCIM_EDXRDY (1 << 9)
  57. #define MMCIM_EDRRDY (1 << 10)
  58. #define MMCIM_EDATED (1 << 11)
  59. #define MMCIM_ETRNDNE (1 << 12)
  60. #define MMCIM_MASKALL (0xFFFFFFFF)
  61. /* MMC Resp Tout Reg fields */
  62. #define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
  63. #define MMCTOR_TOD_20_16_SHIFT (8)
  64. /* MMC Data Read Tout Reg fields */
  65. #define MMCTOD_TOD_0_15_MASK (0xFFFF)
  66. /* MMC Block len Reg fields */
  67. #define MMCBLEN_BLEN_MASK (0xFFF)
  68. /* MMC Num Blocks Reg fields */
  69. #define MMCNBLK_NBLK_MASK (0xFFFF)
  70. #define MMCNBLK_NBLK_MAX (0xFFFF)
  71. /* MMC Num Blocks Counter Reg fields */
  72. #define MMCNBLC_NBLC_MASK (0xFFFF)
  73. /* MMC Cmd Reg fields */
  74. #define MMCCMD_CMD_MASK (0x3F)
  75. #define MMCCMD_PPLEN (1 << 7)
  76. #define MMCCMD_BSYEXP (1 << 8)
  77. #define MMCCMD_RSPFMT_NONE (0 << 9)
  78. #define MMCCMD_RSPFMT_R1567 (1 << 9)
  79. #define MMCCMD_RSPFMT_R2 (2 << 9)
  80. #define MMCCMD_RSPFMT_R3 (3 << 9)
  81. #define MMCCMD_DTRW (1 << 11)
  82. #define MMCCMD_STRMTP (1 << 12)
  83. #define MMCCMD_WDATX (1 << 13)
  84. #define MMCCMD_INITCK (1 << 14)
  85. #define MMCCMD_DCLR (1 << 15)
  86. #define MMCCMD_DMATRIG (1 << 16)
  87. /* FIFO control Reg fields */
  88. #define MMCFIFOCTL_FIFORST (1 << 0)
  89. #define MMCFIFOCTL_FIFODIR (1 << 1)
  90. #define MMCFIFOCTL_FIFOLEV (1 << 2)
  91. #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
  92. #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
  93. #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
  94. #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
  95. /* Davinci MMC Register definitions */
  96. struct davinci_mmc_regs {
  97. dv_reg mmcctl;
  98. dv_reg mmcclk;
  99. dv_reg mmcst0;
  100. dv_reg mmcst1;
  101. dv_reg mmcim;
  102. dv_reg mmctor;
  103. dv_reg mmctod;
  104. dv_reg mmcblen;
  105. dv_reg mmcnblk;
  106. dv_reg mmcnblc;
  107. dv_reg mmcdrr;
  108. dv_reg mmcdxr;
  109. dv_reg mmccmd;
  110. dv_reg mmcarghl;
  111. dv_reg mmcrsp01;
  112. dv_reg mmcrsp23;
  113. dv_reg mmcrsp45;
  114. dv_reg mmcrsp67;
  115. dv_reg mmcdrsp;
  116. dv_reg mmcetok;
  117. dv_reg mmccidx;
  118. dv_reg mmcckc;
  119. dv_reg mmctorc;
  120. dv_reg mmctodc;
  121. dv_reg mmcblnc;
  122. dv_reg sdioctl;
  123. dv_reg sdiost0;
  124. dv_reg sdioien;
  125. dv_reg sdioist;
  126. dv_reg mmcfifoctl;
  127. };
  128. /* Davinci MMC board definitions */
  129. struct davinci_mmc {
  130. struct davinci_mmc_regs *reg_base; /* Register base address */
  131. uint input_clk; /* Input clock to MMC controller */
  132. uint host_caps; /* Host capabilities */
  133. uint voltages; /* Host supported voltages */
  134. struct mmc_config cfg;
  135. };
  136. #define DAVINCI_MAX_BLOCKS (32)
  137. struct davinci_mmc_plat {
  138. struct davinci_mmc_regs *reg_base; /* Register base address */
  139. struct mmc_config cfg;
  140. struct mmc mmc;
  141. };
  142. int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host);
  143. #endif /* _SDMMC_DEFS_H */