mvtwsi.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for the TWSI (i2c) controller found on the Marvell
  4. * orion5x and kirkwood SoC families.
  5. *
  6. * Author: Albert Aribaud <albert.u.boot@aribaud.net>
  7. * Copyright (c) 2010 Albert Aribaud.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/compat.h>
  15. #ifdef CONFIG_DM_I2C
  16. #include <dm.h>
  17. #endif
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /*
  20. * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
  21. * settings
  22. */
  23. #ifndef CONFIG_DM_I2C
  24. #if defined(CONFIG_ARCH_ORION5X)
  25. #include <asm/arch/orion5x.h>
  26. #elif (defined(CONFIG_ARCH_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
  27. #include <asm/arch/soc.h>
  28. #elif defined(CONFIG_ARCH_SUNXI)
  29. #include <asm/arch/i2c.h>
  30. #else
  31. #error Driver mvtwsi not supported by SoC or board
  32. #endif
  33. #endif /* CONFIG_DM_I2C */
  34. /*
  35. * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to
  36. * always have it.
  37. */
  38. #if defined(CONFIG_DM_I2C) && defined(CONFIG_ARCH_SUNXI)
  39. #include <asm/arch/i2c.h>
  40. #endif
  41. /*
  42. * TWSI register structure
  43. */
  44. #ifdef CONFIG_ARCH_SUNXI
  45. struct mvtwsi_registers {
  46. u32 slave_address;
  47. u32 xtnd_slave_addr;
  48. u32 data;
  49. u32 control;
  50. u32 status;
  51. u32 baudrate;
  52. u32 soft_reset;
  53. u32 debug; /* Dummy field for build compatibility with mvebu */
  54. };
  55. #else
  56. struct mvtwsi_registers {
  57. u32 slave_address;
  58. u32 data;
  59. u32 control;
  60. union {
  61. u32 status; /* When reading */
  62. u32 baudrate; /* When writing */
  63. };
  64. u32 xtnd_slave_addr;
  65. u32 reserved0[2];
  66. u32 soft_reset;
  67. u32 reserved1[27];
  68. u32 debug;
  69. };
  70. #endif
  71. #ifdef CONFIG_DM_I2C
  72. struct mvtwsi_i2c_dev {
  73. /* TWSI Register base for the device */
  74. struct mvtwsi_registers *base;
  75. /* Number of the device (determined from cell-index property) */
  76. int index;
  77. /* The I2C slave address for the device */
  78. u8 slaveadd;
  79. /* The configured I2C speed in Hz */
  80. uint speed;
  81. /* The current length of a clock period (depending on speed) */
  82. uint tick;
  83. };
  84. #endif /* CONFIG_DM_I2C */
  85. /*
  86. * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
  87. * register
  88. */
  89. enum mvtwsi_ctrl_register_fields {
  90. /* Acknowledge bit */
  91. MVTWSI_CONTROL_ACK = 0x00000004,
  92. /* Interrupt flag */
  93. MVTWSI_CONTROL_IFLG = 0x00000008,
  94. /* Stop bit */
  95. MVTWSI_CONTROL_STOP = 0x00000010,
  96. /* Start bit */
  97. MVTWSI_CONTROL_START = 0x00000020,
  98. /* I2C enable */
  99. MVTWSI_CONTROL_TWSIEN = 0x00000040,
  100. /* Interrupt enable */
  101. MVTWSI_CONTROL_INTEN = 0x00000080,
  102. };
  103. /*
  104. * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
  105. * on other platforms, it is a normal r/w bit, which is cleared by writing 0.
  106. */
  107. #ifdef CONFIG_SUNXI_GEN_SUN6I
  108. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008
  109. #else
  110. #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000
  111. #endif
  112. /*
  113. * enum mvstwsi_status_values - Possible values of I2C controller's status
  114. * register
  115. *
  116. * Only those statuses expected in normal master operation on
  117. * non-10-bit-address devices are specified.
  118. *
  119. * Every status that's unexpected during normal operation (bus errors,
  120. * arbitration losses, missing ACKs...) is passed back to the caller as an error
  121. * code.
  122. */
  123. enum mvstwsi_status_values {
  124. /* START condition transmitted */
  125. MVTWSI_STATUS_START = 0x08,
  126. /* Repeated START condition transmitted */
  127. MVTWSI_STATUS_REPEATED_START = 0x10,
  128. /* Address + write bit transmitted, ACK received */
  129. MVTWSI_STATUS_ADDR_W_ACK = 0x18,
  130. /* Data transmitted, ACK received */
  131. MVTWSI_STATUS_DATA_W_ACK = 0x28,
  132. /* Address + read bit transmitted, ACK received */
  133. MVTWSI_STATUS_ADDR_R_ACK = 0x40,
  134. /* Address + read bit transmitted, ACK not received */
  135. MVTWSI_STATUS_ADDR_R_NAK = 0x48,
  136. /* Data received, ACK transmitted */
  137. MVTWSI_STATUS_DATA_R_ACK = 0x50,
  138. /* Data received, ACK not transmitted */
  139. MVTWSI_STATUS_DATA_R_NAK = 0x58,
  140. /* No relevant status */
  141. MVTWSI_STATUS_IDLE = 0xF8,
  142. };
  143. /*
  144. * enum mvstwsi_ack_flags - Determine whether a read byte should be
  145. * acknowledged or not.
  146. */
  147. enum mvtwsi_ack_flags {
  148. /* Send NAK after received byte */
  149. MVTWSI_READ_NAK = 0,
  150. /* Send ACK after received byte */
  151. MVTWSI_READ_ACK = 1,
  152. };
  153. /*
  154. * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
  155. *
  156. * @speed: The speed in Hz to calculate the clock cycle duration for.
  157. * @return The duration of a clock cycle in ns.
  158. */
  159. inline uint calc_tick(uint speed)
  160. {
  161. /* One tick = the duration of a period at the specified speed in ns (we
  162. * add 100 ns to be on the safe side) */
  163. return (1000000000u / speed) + 100;
  164. }
  165. #ifndef CONFIG_DM_I2C
  166. /*
  167. * twsi_get_base() - Get controller register base for specified adapter
  168. *
  169. * @adap: Adapter to get the register base for.
  170. * @return Register base for the specified adapter.
  171. */
  172. static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
  173. {
  174. switch (adap->hwadapnr) {
  175. #ifdef CONFIG_I2C_MVTWSI_BASE0
  176. case 0:
  177. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
  178. #endif
  179. #ifdef CONFIG_I2C_MVTWSI_BASE1
  180. case 1:
  181. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
  182. #endif
  183. #ifdef CONFIG_I2C_MVTWSI_BASE2
  184. case 2:
  185. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
  186. #endif
  187. #ifdef CONFIG_I2C_MVTWSI_BASE3
  188. case 3:
  189. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
  190. #endif
  191. #ifdef CONFIG_I2C_MVTWSI_BASE4
  192. case 4:
  193. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
  194. #endif
  195. #ifdef CONFIG_I2C_MVTWSI_BASE5
  196. case 5:
  197. return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
  198. #endif
  199. default:
  200. printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
  201. break;
  202. }
  203. return NULL;
  204. }
  205. #endif
  206. /*
  207. * enum mvtwsi_error_class - types of I2C errors
  208. */
  209. enum mvtwsi_error_class {
  210. /* The controller returned a different status than expected */
  211. MVTWSI_ERROR_WRONG_STATUS = 0x01,
  212. /* The controller timed out */
  213. MVTWSI_ERROR_TIMEOUT = 0x02,
  214. };
  215. /*
  216. * mvtwsi_error() - Build I2C return code from error information
  217. *
  218. * For debugging purposes, this function packs some information of an occurred
  219. * error into a return code. These error codes are returned from I2C API
  220. * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
  221. *
  222. * @ec: The error class of the error (enum mvtwsi_error_class).
  223. * @lc: The last value of the control register.
  224. * @ls: The last value of the status register.
  225. * @es: The expected value of the status register.
  226. * @return The generated error code.
  227. */
  228. inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
  229. {
  230. return ((ec << 24) & 0xFF000000)
  231. | ((lc << 16) & 0x00FF0000)
  232. | ((ls << 8) & 0x0000FF00)
  233. | (es & 0xFF);
  234. }
  235. /*
  236. * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
  237. *
  238. * @return Zero if status is as expected, or a non-zero code if either a time
  239. * out occurred, or the status was not the expected one.
  240. */
  241. static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
  242. uint tick)
  243. {
  244. int control, status;
  245. int timeout = 1000;
  246. do {
  247. control = readl(&twsi->control);
  248. if (control & MVTWSI_CONTROL_IFLG) {
  249. /*
  250. * On Armada 38x it seems that the controller works as
  251. * if it first set the MVTWSI_CONTROL_IFLAG in the
  252. * control register and only after that it changed the
  253. * status register.
  254. * This sometimes caused weird bugs which only appeared
  255. * on selected I2C speeds and even then only sometimes.
  256. * We therefore add here a simple ndealy(100), which
  257. * seems to fix this weird bug.
  258. */
  259. ndelay(100);
  260. status = readl(&twsi->status);
  261. if (status == expected_status)
  262. return 0;
  263. else
  264. return mvtwsi_error(
  265. MVTWSI_ERROR_WRONG_STATUS,
  266. control, status, expected_status);
  267. }
  268. ndelay(tick); /* One clock cycle */
  269. } while (timeout--);
  270. status = readl(&twsi->status);
  271. return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
  272. expected_status);
  273. }
  274. /*
  275. * twsi_start() - Assert a START condition on the bus.
  276. *
  277. * This function is used in both single I2C transactions and inside
  278. * back-to-back transactions (repeated starts).
  279. *
  280. * @twsi: The MVTWSI register structure to use.
  281. * @expected_status: The I2C bus status expected to be asserted after the
  282. * operation completion.
  283. * @tick: The duration of a clock cycle at the current I2C speed.
  284. * @return Zero if status is as expected, or a non-zero code if either a time
  285. * out occurred or the status was not the expected one.
  286. */
  287. static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
  288. uint tick)
  289. {
  290. /* Assert START */
  291. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
  292. MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  293. /* Wait for controller to process START */
  294. return twsi_wait(twsi, expected_status, tick);
  295. }
  296. /*
  297. * twsi_send() - Send a byte on the I2C bus.
  298. *
  299. * The byte may be part of an address byte or data.
  300. *
  301. * @twsi: The MVTWSI register structure to use.
  302. * @byte: The byte to send.
  303. * @expected_status: The I2C bus status expected to be asserted after the
  304. * operation completion.
  305. * @tick: The duration of a clock cycle at the current I2C speed.
  306. * @return Zero if status is as expected, or a non-zero code if either a time
  307. * out occurred or the status was not the expected one.
  308. */
  309. static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
  310. int expected_status, uint tick)
  311. {
  312. /* Write byte to data register for sending */
  313. writel(byte, &twsi->data);
  314. /* Clear any pending interrupt -- that will cause sending */
  315. writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
  316. &twsi->control);
  317. /* Wait for controller to receive byte, and check ACK */
  318. return twsi_wait(twsi, expected_status, tick);
  319. }
  320. /*
  321. * twsi_recv() - Receive a byte on the I2C bus.
  322. *
  323. * The static variable mvtwsi_control_flags controls whether we ack or nak.
  324. *
  325. * @twsi: The MVTWSI register structure to use.
  326. * @byte: The byte to send.
  327. * @ack_flag: Flag that determines whether the received byte should
  328. * be acknowledged by the controller or not (sent ACK/NAK).
  329. * @tick: The duration of a clock cycle at the current I2C speed.
  330. * @return Zero if status is as expected, or a non-zero code if either a time
  331. * out occurred or the status was not the expected one.
  332. */
  333. static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
  334. uint tick)
  335. {
  336. int expected_status, status, control;
  337. /* Compute expected status based on passed ACK flag */
  338. expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
  339. MVTWSI_STATUS_DATA_R_NAK;
  340. /* Acknowledge *previous state*, and launch receive */
  341. control = MVTWSI_CONTROL_TWSIEN;
  342. control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
  343. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  344. /* Wait for controller to receive byte, and assert ACK or NAK */
  345. status = twsi_wait(twsi, expected_status, tick);
  346. /* If we did receive the expected byte, store it */
  347. if (status == 0)
  348. *byte = readl(&twsi->data);
  349. return status;
  350. }
  351. /*
  352. * twsi_stop() - Assert a STOP condition on the bus.
  353. *
  354. * This function is also used to force the bus back to idle state (SDA =
  355. * SCL = 1).
  356. *
  357. * @twsi: The MVTWSI register structure to use.
  358. * @tick: The duration of a clock cycle at the current I2C speed.
  359. * @return Zero if the operation succeeded, or a non-zero code if a time out
  360. * occurred.
  361. */
  362. static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
  363. {
  364. int control, stop_status;
  365. int status = 0;
  366. int timeout = 1000;
  367. /* Assert STOP */
  368. control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
  369. writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
  370. /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
  371. do {
  372. stop_status = readl(&twsi->status);
  373. if (stop_status == MVTWSI_STATUS_IDLE)
  374. break;
  375. ndelay(tick); /* One clock cycle */
  376. } while (timeout--);
  377. control = readl(&twsi->control);
  378. if (stop_status != MVTWSI_STATUS_IDLE)
  379. status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
  380. control, status, MVTWSI_STATUS_IDLE);
  381. return status;
  382. }
  383. /*
  384. * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
  385. *
  386. * @n: Parameter 'n' for the frequency calculation algorithm.
  387. * @m: Parameter 'm' for the frequency calculation algorithm.
  388. * @return The I2C frequency corresponding to the passed m and n parameters.
  389. */
  390. static uint twsi_calc_freq(const int n, const int m)
  391. {
  392. #ifdef CONFIG_ARCH_SUNXI
  393. return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
  394. #else
  395. return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
  396. #endif
  397. }
  398. /*
  399. * twsi_reset() - Reset the I2C controller.
  400. *
  401. * Resetting the controller also resets the baud rate and slave address, hence
  402. * they must be re-established after the reset.
  403. *
  404. * @twsi: The MVTWSI register structure to use.
  405. */
  406. static void twsi_reset(struct mvtwsi_registers *twsi)
  407. {
  408. /* Reset controller */
  409. writel(0, &twsi->soft_reset);
  410. /* Wait 2 ms -- this is what the Marvell LSP does */
  411. udelay(20000);
  412. }
  413. /*
  414. * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
  415. *
  416. * This function sets baud rate to the highest possible value that does not
  417. * exceed the requested rate.
  418. *
  419. * @twsi: The MVTWSI register structure to use.
  420. * @requested_speed: The desired frequency the controller should run at
  421. * in Hz.
  422. * @return The actual frequency the controller was configured to.
  423. */
  424. static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
  425. uint requested_speed)
  426. {
  427. uint tmp_speed, highest_speed, n, m;
  428. uint baud = 0x44; /* Baud rate after controller reset */
  429. highest_speed = 0;
  430. /* Successively try m, n combinations, and use the combination
  431. * resulting in the largest speed that's not above the requested
  432. * speed */
  433. for (n = 0; n < 8; n++) {
  434. for (m = 0; m < 16; m++) {
  435. tmp_speed = twsi_calc_freq(n, m);
  436. if ((tmp_speed <= requested_speed) &&
  437. (tmp_speed > highest_speed)) {
  438. highest_speed = tmp_speed;
  439. baud = (m << 3) | n;
  440. }
  441. }
  442. }
  443. writel(baud, &twsi->baudrate);
  444. /* Wait for controller for one tick */
  445. #ifdef CONFIG_DM_I2C
  446. ndelay(calc_tick(highest_speed));
  447. #else
  448. ndelay(10000);
  449. #endif
  450. return highest_speed;
  451. }
  452. /*
  453. * __twsi_i2c_init() - Initialize the I2C controller.
  454. *
  455. * @twsi: The MVTWSI register structure to use.
  456. * @speed: The initial frequency the controller should run at
  457. * in Hz.
  458. * @slaveadd: The I2C address to be set for the I2C master.
  459. * @actual_speed: A output parameter that receives the actual frequency
  460. * in Hz the controller was set to by the function.
  461. * @return Zero if the operation succeeded, or a non-zero code if a time out
  462. * occurred.
  463. */
  464. static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
  465. int slaveadd, uint *actual_speed)
  466. {
  467. uint tmp_speed;
  468. /* Reset controller */
  469. twsi_reset(twsi);
  470. /* Set speed */
  471. tmp_speed = __twsi_i2c_set_bus_speed(twsi, speed);
  472. if (actual_speed)
  473. *actual_speed = tmp_speed;
  474. /* Set slave address; even though we don't use it */
  475. writel(slaveadd, &twsi->slave_address);
  476. writel(0, &twsi->xtnd_slave_addr);
  477. /* Assert STOP, but don't care for the result */
  478. #ifdef CONFIG_DM_I2C
  479. (void) twsi_stop(twsi, calc_tick(*actual_speed));
  480. #else
  481. (void) twsi_stop(twsi, 10000);
  482. #endif
  483. }
  484. /*
  485. * i2c_begin() - Start a I2C transaction.
  486. *
  487. * Begin a I2C transaction with a given expected start status and chip address.
  488. * A START is asserted, and the address byte is sent to the I2C controller. The
  489. * expected address status will be derived from the direction bit (bit 0) of
  490. * the address byte.
  491. *
  492. * @twsi: The MVTWSI register structure to use.
  493. * @expected_start_status: The I2C status the controller is expected to
  494. * assert after the address byte was sent.
  495. * @addr: The address byte to be sent.
  496. * @tick: The duration of a clock cycle at the current
  497. * I2C speed.
  498. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  499. * unexpected I2C status occurred.
  500. */
  501. static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
  502. u8 addr, uint tick)
  503. {
  504. int status, expected_addr_status;
  505. /* Compute the expected address status from the direction bit in
  506. * the address byte */
  507. if (addr & 1) /* Reading */
  508. expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
  509. else /* Writing */
  510. expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
  511. /* Assert START */
  512. status = twsi_start(twsi, expected_start_status, tick);
  513. /* Send out the address if the start went well */
  514. if (status == 0)
  515. status = twsi_send(twsi, addr, expected_addr_status, tick);
  516. /* Return 0, or the status of the first failure */
  517. return status;
  518. }
  519. /*
  520. * __twsi_i2c_probe_chip() - Probe the given I2C chip address.
  521. *
  522. * This function begins a I2C read transaction, does a dummy read and NAKs; if
  523. * the procedure succeeds, the chip is considered to be present.
  524. *
  525. * @twsi: The MVTWSI register structure to use.
  526. * @chip: The chip address to probe.
  527. * @tick: The duration of a clock cycle at the current I2C speed.
  528. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  529. * unexpected I2C status occurred.
  530. */
  531. static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
  532. uint tick)
  533. {
  534. u8 dummy_byte;
  535. int status;
  536. /* Begin i2c read */
  537. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
  538. /* Dummy read was accepted: receive byte, but NAK it. */
  539. if (status == 0)
  540. status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
  541. /* Stop transaction */
  542. twsi_stop(twsi, tick);
  543. /* Return 0, or the status of the first failure */
  544. return status;
  545. }
  546. /*
  547. * __twsi_i2c_read() - Read data from a I2C chip.
  548. *
  549. * This function begins a I2C write transaction, and transmits the address
  550. * bytes; then begins a I2C read transaction, and receives the data bytes.
  551. *
  552. * NOTE: Some devices want a stop right before the second start, while some
  553. * will choke if it is there. Since deciding this is not yet supported in
  554. * higher level APIs, we need to make a decision here, and for the moment that
  555. * will be a repeated start without a preceding stop.
  556. *
  557. * @twsi: The MVTWSI register structure to use.
  558. * @chip: The chip address to read from.
  559. * @addr: The address bytes to send.
  560. * @alen: The length of the address bytes in bytes.
  561. * @data: The buffer to receive the data read from the chip (has to have
  562. * a size of at least 'length' bytes).
  563. * @length: The amount of data to be read from the chip in bytes.
  564. * @tick: The duration of a clock cycle at the current I2C speed.
  565. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  566. * unexpected I2C status occurred.
  567. */
  568. static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
  569. u8 *addr, int alen, uchar *data, int length,
  570. uint tick)
  571. {
  572. int status = 0;
  573. int stop_status;
  574. int expected_start = MVTWSI_STATUS_START;
  575. if (alen > 0) {
  576. /* Begin i2c write to send the address bytes */
  577. status = i2c_begin(twsi, expected_start, (chip << 1), tick);
  578. /* Send address bytes */
  579. while ((status == 0) && alen--)
  580. status = twsi_send(twsi, addr[alen],
  581. MVTWSI_STATUS_DATA_W_ACK, tick);
  582. /* Send repeated STARTs after the initial START */
  583. expected_start = MVTWSI_STATUS_REPEATED_START;
  584. }
  585. /* Begin i2c read to receive data bytes */
  586. if (status == 0)
  587. status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
  588. /* Receive actual data bytes; set NAK if we if we have nothing more to
  589. * read */
  590. while ((status == 0) && length--)
  591. status = twsi_recv(twsi, data++,
  592. length > 0 ?
  593. MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
  594. /* Stop transaction */
  595. stop_status = twsi_stop(twsi, tick);
  596. /* Return 0, or the status of the first failure */
  597. return status != 0 ? status : stop_status;
  598. }
  599. /*
  600. * __twsi_i2c_write() - Send data to a I2C chip.
  601. *
  602. * This function begins a I2C write transaction, and transmits the address
  603. * bytes; then begins a new I2C write transaction, and sends the data bytes.
  604. *
  605. * @twsi: The MVTWSI register structure to use.
  606. * @chip: The chip address to read from.
  607. * @addr: The address bytes to send.
  608. * @alen: The length of the address bytes in bytes.
  609. * @data: The buffer containing the data to be sent to the chip.
  610. * @length: The length of data to be sent to the chip in bytes.
  611. * @tick: The duration of a clock cycle at the current I2C speed.
  612. * @return Zero if the operation succeeded, or a non-zero code if a time out or
  613. * unexpected I2C status occurred.
  614. */
  615. static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
  616. u8 *addr, int alen, uchar *data, int length,
  617. uint tick)
  618. {
  619. int status, stop_status;
  620. /* Begin i2c write to send first the address bytes, then the
  621. * data bytes */
  622. status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
  623. /* Send address bytes */
  624. while ((status == 0) && (alen-- > 0))
  625. status = twsi_send(twsi, addr[alen], MVTWSI_STATUS_DATA_W_ACK,
  626. tick);
  627. /* Send data bytes */
  628. while ((status == 0) && (length-- > 0))
  629. status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
  630. tick);
  631. /* Stop transaction */
  632. stop_status = twsi_stop(twsi, tick);
  633. /* Return 0, or the status of the first failure */
  634. return status != 0 ? status : stop_status;
  635. }
  636. #ifndef CONFIG_DM_I2C
  637. static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
  638. int slaveadd)
  639. {
  640. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  641. __twsi_i2c_init(twsi, speed, slaveadd, NULL);
  642. }
  643. static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
  644. uint requested_speed)
  645. {
  646. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  647. __twsi_i2c_set_bus_speed(twsi, requested_speed);
  648. return 0;
  649. }
  650. static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
  651. {
  652. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  653. return __twsi_i2c_probe_chip(twsi, chip, 10000);
  654. }
  655. static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  656. int alen, uchar *data, int length)
  657. {
  658. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  659. u8 addr_bytes[4];
  660. addr_bytes[0] = (addr >> 0) & 0xFF;
  661. addr_bytes[1] = (addr >> 8) & 0xFF;
  662. addr_bytes[2] = (addr >> 16) & 0xFF;
  663. addr_bytes[3] = (addr >> 24) & 0xFF;
  664. return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
  665. 10000);
  666. }
  667. static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  668. int alen, uchar *data, int length)
  669. {
  670. struct mvtwsi_registers *twsi = twsi_get_base(adap);
  671. u8 addr_bytes[4];
  672. addr_bytes[0] = (addr >> 0) & 0xFF;
  673. addr_bytes[1] = (addr >> 8) & 0xFF;
  674. addr_bytes[2] = (addr >> 16) & 0xFF;
  675. addr_bytes[3] = (addr >> 24) & 0xFF;
  676. return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
  677. 10000);
  678. }
  679. #ifdef CONFIG_I2C_MVTWSI_BASE0
  680. U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
  681. twsi_i2c_read, twsi_i2c_write,
  682. twsi_i2c_set_bus_speed,
  683. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
  684. #endif
  685. #ifdef CONFIG_I2C_MVTWSI_BASE1
  686. U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
  687. twsi_i2c_read, twsi_i2c_write,
  688. twsi_i2c_set_bus_speed,
  689. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
  690. #endif
  691. #ifdef CONFIG_I2C_MVTWSI_BASE2
  692. U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
  693. twsi_i2c_read, twsi_i2c_write,
  694. twsi_i2c_set_bus_speed,
  695. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
  696. #endif
  697. #ifdef CONFIG_I2C_MVTWSI_BASE3
  698. U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
  699. twsi_i2c_read, twsi_i2c_write,
  700. twsi_i2c_set_bus_speed,
  701. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
  702. #endif
  703. #ifdef CONFIG_I2C_MVTWSI_BASE4
  704. U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
  705. twsi_i2c_read, twsi_i2c_write,
  706. twsi_i2c_set_bus_speed,
  707. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
  708. #endif
  709. #ifdef CONFIG_I2C_MVTWSI_BASE5
  710. U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
  711. twsi_i2c_read, twsi_i2c_write,
  712. twsi_i2c_set_bus_speed,
  713. CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
  714. #endif
  715. #else /* CONFIG_DM_I2C */
  716. static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  717. u32 chip_flags)
  718. {
  719. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  720. return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
  721. }
  722. static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
  723. {
  724. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  725. dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
  726. dev->tick = calc_tick(dev->speed);
  727. return 0;
  728. }
  729. static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
  730. {
  731. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  732. dev->base = devfdt_get_addr_ptr(bus);
  733. if (!dev->base)
  734. return -ENOMEM;
  735. dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  736. "cell-index", -1);
  737. dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
  738. "u-boot,i2c-slave-addr", 0x0);
  739. dev->speed = dev_read_u32_default(bus, "clock-frequency",
  740. I2C_SPEED_STANDARD_RATE);
  741. return 0;
  742. }
  743. static void twsi_disable_i2c_slave(struct mvtwsi_registers *twsi)
  744. {
  745. clrbits_le32(&twsi->debug, BIT(18));
  746. }
  747. static int mvtwsi_i2c_bind(struct udevice *bus)
  748. {
  749. struct mvtwsi_registers *twsi = devfdt_get_addr_ptr(bus);
  750. /* Disable the hidden slave in i2c0 of these platforms */
  751. if ((IS_ENABLED(CONFIG_ARMADA_38X) || IS_ENABLED(CONFIG_ARCH_KIRKWOOD))
  752. && bus->req_seq == 0)
  753. twsi_disable_i2c_slave(twsi);
  754. return 0;
  755. }
  756. static int mvtwsi_i2c_probe(struct udevice *bus)
  757. {
  758. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  759. uint actual_speed;
  760. __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
  761. dev->speed = actual_speed;
  762. dev->tick = calc_tick(dev->speed);
  763. return 0;
  764. }
  765. static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  766. {
  767. struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
  768. struct i2c_msg *dmsg, *omsg, dummy;
  769. memset(&dummy, 0, sizeof(struct i2c_msg));
  770. /* We expect either two messages (one with an offset and one with the
  771. * actual data) or one message (just data or offset/data combined) */
  772. if (nmsgs > 2 || nmsgs == 0) {
  773. debug("%s: Only one or two messages are supported.", __func__);
  774. return -1;
  775. }
  776. omsg = nmsgs == 1 ? &dummy : msg;
  777. dmsg = nmsgs == 1 ? msg : msg + 1;
  778. if (dmsg->flags & I2C_M_RD)
  779. return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
  780. omsg->len, dmsg->buf, dmsg->len,
  781. dev->tick);
  782. else
  783. return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
  784. omsg->len, dmsg->buf, dmsg->len,
  785. dev->tick);
  786. }
  787. static const struct dm_i2c_ops mvtwsi_i2c_ops = {
  788. .xfer = mvtwsi_i2c_xfer,
  789. .probe_chip = mvtwsi_i2c_probe_chip,
  790. .set_bus_speed = mvtwsi_i2c_set_bus_speed,
  791. };
  792. static const struct udevice_id mvtwsi_i2c_ids[] = {
  793. { .compatible = "marvell,mv64xxx-i2c", },
  794. { .compatible = "marvell,mv78230-i2c", },
  795. { .compatible = "allwinner,sun6i-a31-i2c", },
  796. { /* sentinel */ }
  797. };
  798. U_BOOT_DRIVER(i2c_mvtwsi) = {
  799. .name = "i2c_mvtwsi",
  800. .id = UCLASS_I2C,
  801. .of_match = mvtwsi_i2c_ids,
  802. .bind = mvtwsi_i2c_bind,
  803. .probe = mvtwsi_i2c_probe,
  804. .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
  805. .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
  806. .ops = &mvtwsi_i2c_ops,
  807. };
  808. #endif /* CONFIG_DM_I2C */