mp_init.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. *
  5. * Based on code from the coreboot file of the same name
  6. */
  7. #include <common.h>
  8. #include <cpu.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <qfw.h>
  13. #include <asm/atomic.h>
  14. #include <asm/cpu.h>
  15. #include <asm/interrupt.h>
  16. #include <asm/lapic.h>
  17. #include <asm/microcode.h>
  18. #include <asm/mp.h>
  19. #include <asm/msr.h>
  20. #include <asm/mtrr.h>
  21. #include <asm/processor.h>
  22. #include <asm/sipi.h>
  23. #include <dm/device-internal.h>
  24. #include <dm/uclass-internal.h>
  25. #include <dm/lists.h>
  26. #include <dm/root.h>
  27. #include <linux/linkage.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. /* Total CPUs include BSP */
  30. static int num_cpus;
  31. /* This also needs to match the sipi.S assembly code for saved MSR encoding */
  32. struct saved_msr {
  33. uint32_t index;
  34. uint32_t lo;
  35. uint32_t hi;
  36. } __packed;
  37. struct mp_flight_plan {
  38. int num_records;
  39. struct mp_flight_record *records;
  40. };
  41. static struct mp_flight_plan mp_info;
  42. struct cpu_map {
  43. struct udevice *dev;
  44. int apic_id;
  45. int err_code;
  46. };
  47. static inline void barrier_wait(atomic_t *b)
  48. {
  49. while (atomic_read(b) == 0)
  50. asm("pause");
  51. mfence();
  52. }
  53. static inline void release_barrier(atomic_t *b)
  54. {
  55. mfence();
  56. atomic_set(b, 1);
  57. }
  58. static inline void stop_this_cpu(void)
  59. {
  60. /* Called by an AP when it is ready to halt and wait for a new task */
  61. for (;;)
  62. cpu_hlt();
  63. }
  64. /* Returns 1 if timeout waiting for APs. 0 if target APs found */
  65. static int wait_for_aps(atomic_t *val, int target, int total_delay,
  66. int delay_step)
  67. {
  68. int timeout = 0;
  69. int delayed = 0;
  70. while (atomic_read(val) != target) {
  71. udelay(delay_step);
  72. delayed += delay_step;
  73. if (delayed >= total_delay) {
  74. timeout = 1;
  75. break;
  76. }
  77. }
  78. return timeout;
  79. }
  80. static void ap_do_flight_plan(struct udevice *cpu)
  81. {
  82. int i;
  83. for (i = 0; i < mp_info.num_records; i++) {
  84. struct mp_flight_record *rec = &mp_info.records[i];
  85. atomic_inc(&rec->cpus_entered);
  86. barrier_wait(&rec->barrier);
  87. if (rec->ap_call != NULL)
  88. rec->ap_call(cpu, rec->ap_arg);
  89. }
  90. }
  91. static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
  92. {
  93. struct udevice *dev;
  94. *devp = NULL;
  95. for (uclass_find_first_device(UCLASS_CPU, &dev);
  96. dev;
  97. uclass_find_next_device(&dev)) {
  98. struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  99. if (plat->cpu_id == apic_id) {
  100. *devp = dev;
  101. return 0;
  102. }
  103. }
  104. return -ENOENT;
  105. }
  106. /*
  107. * By the time APs call ap_init() caching has been setup, and microcode has
  108. * been loaded
  109. */
  110. static void ap_init(unsigned int cpu_index)
  111. {
  112. struct udevice *dev;
  113. int apic_id;
  114. int ret;
  115. /* Ensure the local apic is enabled */
  116. enable_lapic();
  117. apic_id = lapicid();
  118. ret = find_cpu_by_apic_id(apic_id, &dev);
  119. if (ret) {
  120. debug("Unknown CPU apic_id %x\n", apic_id);
  121. goto done;
  122. }
  123. debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
  124. dev ? dev->name : "(apic_id not found)");
  125. /* Walk the flight plan */
  126. ap_do_flight_plan(dev);
  127. /* Park the AP */
  128. debug("parking\n");
  129. done:
  130. stop_this_cpu();
  131. }
  132. static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
  133. MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
  134. MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
  135. MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
  136. MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
  137. };
  138. static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
  139. {
  140. msr_t msr;
  141. msr = msr_read(index);
  142. entry->index = index;
  143. entry->lo = msr.lo;
  144. entry->hi = msr.hi;
  145. /* Return the next entry */
  146. entry++;
  147. return entry;
  148. }
  149. static int save_bsp_msrs(char *start, int size)
  150. {
  151. int msr_count;
  152. int num_var_mtrrs;
  153. struct saved_msr *msr_entry;
  154. int i;
  155. msr_t msr;
  156. /* Determine number of MTRRs need to be saved */
  157. msr = msr_read(MTRR_CAP_MSR);
  158. num_var_mtrrs = msr.lo & 0xff;
  159. /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
  160. msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
  161. if ((msr_count * sizeof(struct saved_msr)) > size) {
  162. printf("Cannot mirror all %d msrs\n", msr_count);
  163. return -ENOSPC;
  164. }
  165. msr_entry = (void *)start;
  166. for (i = 0; i < NUM_FIXED_MTRRS; i++)
  167. msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
  168. for (i = 0; i < num_var_mtrrs; i++) {
  169. msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
  170. msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
  171. }
  172. msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
  173. return msr_count;
  174. }
  175. static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
  176. {
  177. struct sipi_params_16bit *params16;
  178. struct sipi_params *params;
  179. static char msr_save[512];
  180. char *stack;
  181. ulong addr;
  182. int code_len;
  183. int size;
  184. int ret;
  185. /* Copy in the code */
  186. code_len = ap_start16_code_end - ap_start16;
  187. debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
  188. code_len);
  189. memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
  190. addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
  191. params16 = (struct sipi_params_16bit *)addr;
  192. params16->ap_start = (uint32_t)ap_start;
  193. params16->gdt = (uint32_t)gd->arch.gdt;
  194. params16->gdt_limit = X86_GDT_SIZE - 1;
  195. debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
  196. params = (struct sipi_params *)sipi_params;
  197. debug("SIPI 32-bit params at %p\n", params);
  198. params->idt_ptr = (uint32_t)x86_get_idt();
  199. params->stack_size = CONFIG_AP_STACK_SIZE;
  200. size = params->stack_size * num_cpus;
  201. stack = memalign(4096, size);
  202. if (!stack)
  203. return -ENOMEM;
  204. params->stack_top = (u32)(stack + size);
  205. #if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \
  206. !defined(CONFIG_INTEL_MID)
  207. params->microcode_ptr = ucode_base;
  208. debug("Microcode at %x\n", params->microcode_ptr);
  209. #endif
  210. params->msr_table_ptr = (u32)msr_save;
  211. ret = save_bsp_msrs(msr_save, sizeof(msr_save));
  212. if (ret < 0)
  213. return ret;
  214. params->msr_count = ret;
  215. params->c_handler = (uint32_t)&ap_init;
  216. *ap_countp = &params->ap_count;
  217. atomic_set(*ap_countp, 0);
  218. debug("SIPI vector is ready\n");
  219. return 0;
  220. }
  221. static int check_cpu_devices(int expected_cpus)
  222. {
  223. int i;
  224. for (i = 0; i < expected_cpus; i++) {
  225. struct udevice *dev;
  226. int ret;
  227. ret = uclass_find_device(UCLASS_CPU, i, &dev);
  228. if (ret) {
  229. debug("Cannot find CPU %d in device tree\n", i);
  230. return ret;
  231. }
  232. }
  233. return 0;
  234. }
  235. /* Returns 1 for timeout. 0 on success */
  236. static int apic_wait_timeout(int total_delay, const char *msg)
  237. {
  238. int total = 0;
  239. if (!(lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY))
  240. return 0;
  241. debug("Waiting for %s...", msg);
  242. while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
  243. udelay(50);
  244. total += 50;
  245. if (total >= total_delay) {
  246. debug("timed out: aborting\n");
  247. return -ETIMEDOUT;
  248. }
  249. }
  250. debug("done\n");
  251. return 0;
  252. }
  253. static int start_aps(int ap_count, atomic_t *num_aps)
  254. {
  255. int sipi_vector;
  256. /* Max location is 4KiB below 1MiB */
  257. const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
  258. if (ap_count == 0)
  259. return 0;
  260. /* The vector is sent as a 4k aligned address in one byte */
  261. sipi_vector = AP_DEFAULT_BASE >> 12;
  262. if (sipi_vector > max_vector_loc) {
  263. printf("SIPI vector too large! 0x%08x\n",
  264. sipi_vector);
  265. return -ENOSPC;
  266. }
  267. debug("Attempting to start %d APs\n", ap_count);
  268. if (apic_wait_timeout(1000, "ICR not to be busy"))
  269. return -ETIMEDOUT;
  270. /* Send INIT IPI to all but self */
  271. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  272. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  273. LAPIC_DM_INIT);
  274. debug("Waiting for 10ms after sending INIT\n");
  275. mdelay(10);
  276. /* Send 1st SIPI */
  277. if (apic_wait_timeout(1000, "ICR not to be busy"))
  278. return -ETIMEDOUT;
  279. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  280. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  281. LAPIC_DM_STARTUP | sipi_vector);
  282. if (apic_wait_timeout(10000, "first SIPI to complete"))
  283. return -ETIMEDOUT;
  284. /* Wait for CPUs to check in up to 200 us */
  285. wait_for_aps(num_aps, ap_count, 200, 15);
  286. /* Send 2nd SIPI */
  287. if (apic_wait_timeout(1000, "ICR not to be busy"))
  288. return -ETIMEDOUT;
  289. lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
  290. lapic_write(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
  291. LAPIC_DM_STARTUP | sipi_vector);
  292. if (apic_wait_timeout(10000, "second SIPI to complete"))
  293. return -ETIMEDOUT;
  294. /* Wait for CPUs to check in */
  295. if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
  296. debug("Not all APs checked in: %d/%d\n",
  297. atomic_read(num_aps), ap_count);
  298. return -EIO;
  299. }
  300. return 0;
  301. }
  302. static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
  303. {
  304. int i;
  305. int ret = 0;
  306. const int timeout_us = 100000;
  307. const int step_us = 100;
  308. int num_aps = num_cpus - 1;
  309. for (i = 0; i < mp_params->num_records; i++) {
  310. struct mp_flight_record *rec = &mp_params->flight_plan[i];
  311. /* Wait for APs if the record is not released */
  312. if (atomic_read(&rec->barrier) == 0) {
  313. /* Wait for the APs to check in */
  314. if (wait_for_aps(&rec->cpus_entered, num_aps,
  315. timeout_us, step_us)) {
  316. debug("MP record %d timeout\n", i);
  317. ret = -ETIMEDOUT;
  318. }
  319. }
  320. if (rec->bsp_call != NULL)
  321. rec->bsp_call(cpu, rec->bsp_arg);
  322. release_barrier(&rec->barrier);
  323. }
  324. return ret;
  325. }
  326. static int init_bsp(struct udevice **devp)
  327. {
  328. char processor_name[CPU_MAX_NAME_LEN];
  329. int apic_id;
  330. int ret;
  331. cpu_get_name(processor_name);
  332. debug("CPU: %s\n", processor_name);
  333. apic_id = lapicid();
  334. ret = find_cpu_by_apic_id(apic_id, devp);
  335. if (ret) {
  336. printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
  337. return ret;
  338. }
  339. return 0;
  340. }
  341. int mp_init(struct mp_params *p)
  342. {
  343. int num_aps;
  344. atomic_t *ap_count;
  345. struct udevice *cpu;
  346. int ret;
  347. /* This will cause the CPUs devices to be bound */
  348. struct uclass *uc;
  349. ret = uclass_get(UCLASS_CPU, &uc);
  350. if (ret)
  351. return ret;
  352. if (IS_ENABLED(CONFIG_QFW)) {
  353. ret = qemu_cpu_fixup();
  354. if (ret)
  355. return ret;
  356. }
  357. ret = init_bsp(&cpu);
  358. if (ret) {
  359. debug("Cannot init boot CPU: err=%d\n", ret);
  360. return ret;
  361. }
  362. if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
  363. printf("Invalid MP parameters\n");
  364. return -EINVAL;
  365. }
  366. num_cpus = cpu_get_count(cpu);
  367. if (num_cpus < 0) {
  368. debug("Cannot get number of CPUs: err=%d\n", num_cpus);
  369. return num_cpus;
  370. }
  371. if (num_cpus < 2)
  372. debug("Warning: Only 1 CPU is detected\n");
  373. ret = check_cpu_devices(num_cpus);
  374. if (ret)
  375. debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
  376. /* Copy needed parameters so that APs have a reference to the plan */
  377. mp_info.num_records = p->num_records;
  378. mp_info.records = p->flight_plan;
  379. /* Load the SIPI vector */
  380. ret = load_sipi_vector(&ap_count, num_cpus);
  381. if (ap_count == NULL)
  382. return -ENOENT;
  383. /*
  384. * Make sure SIPI data hits RAM so the APs that come up will see
  385. * the startup code even if the caches are disabled
  386. */
  387. wbinvd();
  388. /* Start the APs providing number of APs and the cpus_entered field */
  389. num_aps = num_cpus - 1;
  390. ret = start_aps(num_aps, ap_count);
  391. if (ret) {
  392. mdelay(1000);
  393. debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
  394. num_aps);
  395. return ret;
  396. }
  397. /* Walk the flight plan for the BSP */
  398. ret = bsp_do_flight_plan(cpu, p);
  399. if (ret) {
  400. debug("CPU init failed: err=%d\n", ret);
  401. return ret;
  402. }
  403. return 0;
  404. }
  405. int mp_init_cpu(struct udevice *cpu, void *unused)
  406. {
  407. struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
  408. /*
  409. * Multiple APs are brought up simultaneously and they may get the same
  410. * seq num in the uclass_resolve_seq() during device_probe(). To avoid
  411. * this, set req_seq to the reg number in the device tree in advance.
  412. */
  413. cpu->req_seq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(cpu), "reg",
  414. -1);
  415. plat->ucode_version = microcode_read_rev();
  416. plat->device_id = gd->arch.x86_device;
  417. return device_probe(cpu);
  418. }