meson_vpu_init.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson Video Processing Unit driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #define DEBUG
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <asm/io.h>
  12. #include "meson_vpu.h"
  13. /* HHI Registers */
  14. #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
  15. #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */
  16. #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
  17. #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */
  18. #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
  19. /* OSDx_CTRL_STAT2 */
  20. #define OSD_REPLACE_EN BIT(14)
  21. #define OSD_REPLACE_SHIFT 6
  22. void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux)
  23. {
  24. writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
  25. }
  26. static unsigned int vpp_filter_coefs_4point_bspline[] = {
  27. 0x15561500, 0x14561600, 0x13561700, 0x12561800,
  28. 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
  29. 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
  30. 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
  31. 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
  32. 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
  33. 0x05473301, 0x05463401, 0x04453601, 0x04433702,
  34. 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
  35. 0x033d3d03
  36. };
  37. static void meson_vpp_write_scaling_filter_coefs(struct meson_vpu_priv *priv,
  38. const unsigned int *coefs,
  39. bool is_horizontal)
  40. {
  41. int i;
  42. writel(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
  43. priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
  44. for (i = 0; i < 33; i++)
  45. writel(coefs[i],
  46. priv->io_base + _REG(VPP_OSD_SCALE_COEF));
  47. }
  48. static const u32 vpp_filter_coefs_bicubic[] = {
  49. 0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
  50. 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
  51. 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
  52. 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
  53. 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
  54. 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
  55. 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
  56. 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
  57. 0xf84848f8
  58. };
  59. static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_vpu_priv *priv,
  60. const unsigned int *coefs,
  61. bool is_horizontal)
  62. {
  63. int i;
  64. writel(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
  65. priv->io_base + _REG(VPP_SCALE_COEF_IDX));
  66. for (i = 0; i < 33; i++)
  67. writel(coefs[i],
  68. priv->io_base + _REG(VPP_SCALE_COEF));
  69. }
  70. /* OSD csc defines */
  71. enum viu_matrix_sel_e {
  72. VIU_MATRIX_OSD_EOTF = 0,
  73. VIU_MATRIX_OSD,
  74. };
  75. enum viu_lut_sel_e {
  76. VIU_LUT_OSD_EOTF = 0,
  77. VIU_LUT_OSD_OETF,
  78. };
  79. #define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2))
  80. #define MATRIX_5X3_COEF_SIZE 24
  81. #define EOTF_COEFF_NORM(a) ((int)((((a) * 4096.0) + 1) / 2))
  82. #define EOTF_COEFF_SIZE 10
  83. #define EOTF_COEFF_RIGHTSHIFT 1
  84. static int RGB709_to_YUV709l_coeff[MATRIX_5X3_COEF_SIZE] = {
  85. 0, 0, 0, /* pre offset */
  86. COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
  87. COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
  88. COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
  89. 0, 0, 0, /* 10'/11'/12' */
  90. 0, 0, 0, /* 20'/21'/22' */
  91. 64, 512, 512, /* offset */
  92. 0, 0, 0 /* mode, right_shift, clip_en */
  93. };
  94. /* eotf matrix: bypass */
  95. static int eotf_bypass_coeff[EOTF_COEFF_SIZE] = {
  96. EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0),
  97. EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0), EOTF_COEFF_NORM(0.0),
  98. EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(0.0), EOTF_COEFF_NORM(1.0),
  99. EOTF_COEFF_RIGHTSHIFT /* right shift */
  100. };
  101. static void meson_viu_set_g12a_osd1_matrix(struct meson_vpu_priv *priv,
  102. int *m, bool csc_on)
  103. {
  104. /* VPP WRAP OSD1 matrix */
  105. writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
  106. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
  107. writel(m[2] & 0xfff,
  108. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
  109. writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
  110. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
  111. writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
  112. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
  113. writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
  114. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
  115. writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
  116. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
  117. writel((m[11] & 0x1fff) << 16,
  118. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22));
  119. writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
  120. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
  121. writel(m[20] & 0xfff,
  122. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
  123. writel_bits(BIT(0), csc_on ? BIT(0) : 0,
  124. priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
  125. }
  126. static void meson_viu_set_osd_matrix(struct meson_vpu_priv *priv,
  127. enum viu_matrix_sel_e m_select,
  128. int *m, bool csc_on)
  129. {
  130. if (m_select == VIU_MATRIX_OSD) {
  131. /* osd matrix, VIU_MATRIX_0 */
  132. writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
  133. priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1));
  134. writel(m[2] & 0xfff,
  135. priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2));
  136. writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
  137. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01));
  138. writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
  139. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10));
  140. writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
  141. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12));
  142. writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
  143. priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21));
  144. if (m[21]) {
  145. writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff),
  146. priv->io_base +
  147. _REG(VIU_OSD1_MATRIX_COEF22_30));
  148. writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff),
  149. priv->io_base +
  150. _REG(VIU_OSD1_MATRIX_COEF31_32));
  151. writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff),
  152. priv->io_base +
  153. _REG(VIU_OSD1_MATRIX_COEF40_41));
  154. writel(m[17] & 0x1fff, priv->io_base +
  155. _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  156. } else {
  157. writel((m[11] & 0x1fff) << 16, priv->io_base +
  158. _REG(VIU_OSD1_MATRIX_COEF22_30));
  159. }
  160. writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
  161. priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1));
  162. writel(m[20] & 0xfff,
  163. priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
  164. writel_bits(3 << 30, m[21] << 30,
  165. priv->io_base +
  166. _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  167. writel_bits(7 << 16, m[22] << 16,
  168. priv->io_base +
  169. _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
  170. /* 23 reserved for clipping control */
  171. writel_bits(BIT(0), csc_on ? BIT(0) : 0,
  172. priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
  173. writel_bits(BIT(1), 0,
  174. priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
  175. } else if (m_select == VIU_MATRIX_OSD_EOTF) {
  176. int i;
  177. /* osd eotf matrix, VIU_MATRIX_OSD_EOTF */
  178. for (i = 0; i < 5; i++)
  179. writel(((m[i * 2] & 0x1fff) << 16) |
  180. (m[i * 2 + 1] & 0x1fff), priv->io_base +
  181. _REG(VIU_OSD1_EOTF_CTL + i + 1));
  182. writel_bits(BIT(30), csc_on ? BIT(30) : 0,
  183. priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
  184. writel_bits(BIT(31), csc_on ? BIT(31) : 0,
  185. priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
  186. }
  187. }
  188. #define OSD_EOTF_LUT_SIZE 33
  189. #define OSD_OETF_LUT_SIZE 41
  190. static void meson_viu_set_osd_lut(struct meson_vpu_priv *priv,
  191. enum viu_lut_sel_e lut_sel,
  192. unsigned int *r_map, unsigned int *g_map,
  193. unsigned int *b_map,
  194. bool csc_on)
  195. {
  196. unsigned int addr_port;
  197. unsigned int data_port;
  198. unsigned int ctrl_port;
  199. int i;
  200. if (lut_sel == VIU_LUT_OSD_EOTF) {
  201. addr_port = VIU_OSD1_EOTF_LUT_ADDR_PORT;
  202. data_port = VIU_OSD1_EOTF_LUT_DATA_PORT;
  203. ctrl_port = VIU_OSD1_EOTF_CTL;
  204. } else if (lut_sel == VIU_LUT_OSD_OETF) {
  205. addr_port = VIU_OSD1_OETF_LUT_ADDR_PORT;
  206. data_port = VIU_OSD1_OETF_LUT_DATA_PORT;
  207. ctrl_port = VIU_OSD1_OETF_CTL;
  208. } else {
  209. return;
  210. }
  211. if (lut_sel == VIU_LUT_OSD_OETF) {
  212. writel(0, priv->io_base + _REG(addr_port));
  213. for (i = 0; i < 20; i++)
  214. writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
  215. priv->io_base + _REG(data_port));
  216. writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16),
  217. priv->io_base + _REG(data_port));
  218. for (i = 0; i < 20; i++)
  219. writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
  220. priv->io_base + _REG(data_port));
  221. for (i = 0; i < 20; i++)
  222. writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
  223. priv->io_base + _REG(data_port));
  224. writel(b_map[OSD_OETF_LUT_SIZE - 1],
  225. priv->io_base + _REG(data_port));
  226. if (csc_on)
  227. writel_bits(0x7 << 29, 7 << 29,
  228. priv->io_base + _REG(ctrl_port));
  229. else
  230. writel_bits(0x7 << 29, 0,
  231. priv->io_base + _REG(ctrl_port));
  232. } else if (lut_sel == VIU_LUT_OSD_EOTF) {
  233. writel(0, priv->io_base + _REG(addr_port));
  234. for (i = 0; i < 20; i++)
  235. writel(r_map[i * 2] | (r_map[i * 2 + 1] << 16),
  236. priv->io_base + _REG(data_port));
  237. writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16),
  238. priv->io_base + _REG(data_port));
  239. for (i = 0; i < 20; i++)
  240. writel(g_map[i * 2 + 1] | (g_map[i * 2 + 2] << 16),
  241. priv->io_base + _REG(data_port));
  242. for (i = 0; i < 20; i++)
  243. writel(b_map[i * 2] | (b_map[i * 2 + 1] << 16),
  244. priv->io_base + _REG(data_port));
  245. writel(b_map[OSD_EOTF_LUT_SIZE - 1],
  246. priv->io_base + _REG(data_port));
  247. if (csc_on)
  248. writel_bits(7 << 27, 7 << 27,
  249. priv->io_base + _REG(ctrl_port));
  250. else
  251. writel_bits(7 << 27, 0,
  252. priv->io_base + _REG(ctrl_port));
  253. writel_bits(BIT(31), BIT(31),
  254. priv->io_base + _REG(ctrl_port));
  255. }
  256. }
  257. /* eotf lut: linear */
  258. static unsigned int eotf_33_linear_mapping[OSD_EOTF_LUT_SIZE] = {
  259. 0x0000, 0x0200, 0x0400, 0x0600,
  260. 0x0800, 0x0a00, 0x0c00, 0x0e00,
  261. 0x1000, 0x1200, 0x1400, 0x1600,
  262. 0x1800, 0x1a00, 0x1c00, 0x1e00,
  263. 0x2000, 0x2200, 0x2400, 0x2600,
  264. 0x2800, 0x2a00, 0x2c00, 0x2e00,
  265. 0x3000, 0x3200, 0x3400, 0x3600,
  266. 0x3800, 0x3a00, 0x3c00, 0x3e00,
  267. 0x4000
  268. };
  269. /* osd oetf lut: linear */
  270. static unsigned int oetf_41_linear_mapping[OSD_OETF_LUT_SIZE] = {
  271. 0, 0, 0, 0,
  272. 0, 32, 64, 96,
  273. 128, 160, 196, 224,
  274. 256, 288, 320, 352,
  275. 384, 416, 448, 480,
  276. 512, 544, 576, 608,
  277. 640, 672, 704, 736,
  278. 768, 800, 832, 864,
  279. 896, 928, 960, 992,
  280. 1023, 1023, 1023, 1023,
  281. 1023
  282. };
  283. static void meson_viu_load_matrix(struct meson_vpu_priv *priv)
  284. {
  285. /* eotf lut bypass */
  286. meson_viu_set_osd_lut(priv, VIU_LUT_OSD_EOTF,
  287. eotf_33_linear_mapping, /* R */
  288. eotf_33_linear_mapping, /* G */
  289. eotf_33_linear_mapping, /* B */
  290. false);
  291. /* eotf matrix bypass */
  292. meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD_EOTF,
  293. eotf_bypass_coeff,
  294. false);
  295. /* oetf lut bypass */
  296. meson_viu_set_osd_lut(priv, VIU_LUT_OSD_OETF,
  297. oetf_41_linear_mapping, /* R */
  298. oetf_41_linear_mapping, /* G */
  299. oetf_41_linear_mapping, /* B */
  300. false);
  301. /* osd matrix RGB709 to YUV709 limit */
  302. meson_viu_set_osd_matrix(priv, VIU_MATRIX_OSD,
  303. RGB709_to_YUV709l_coeff,
  304. true);
  305. }
  306. static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length)
  307. {
  308. u32 val = (((length & 0x80) % 24) / 12);
  309. return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31));
  310. }
  311. void meson_vpu_init(struct udevice *dev)
  312. {
  313. struct meson_vpu_priv *priv = dev_get_priv(dev);
  314. u32 reg;
  315. /*
  316. * Slave dc0 and dc5 connected to master port 1.
  317. * By default other slaves are connected to master port 0.
  318. */
  319. reg = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
  320. VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
  321. writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
  322. /* Slave dc0 connected to master port 1 */
  323. reg = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
  324. writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
  325. /* Slave dc4 and dc7 connected to master port 1 */
  326. reg = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
  327. VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
  328. writel(reg, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
  329. /* Slave dc1 connected to master port 1 */
  330. reg = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
  331. writel(reg, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
  332. /* Disable CVBS VDAC */
  333. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  334. hhi_write(HHI_VDAC_CNTL0_G12A, 0);
  335. hhi_write(HHI_VDAC_CNTL1_G12A, 8);
  336. } else {
  337. hhi_write(HHI_VDAC_CNTL0, 0);
  338. hhi_write(HHI_VDAC_CNTL1, 8);
  339. }
  340. /* Power Down Dacs */
  341. writel(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
  342. /* Disable HDMI PHY */
  343. hhi_write(HHI_HDMI_PHY_CNTL0, 0);
  344. /* Disable HDMI */
  345. writel_bits(VPU_HDMI_ENCI_DATA_TO_HDMI |
  346. VPU_HDMI_ENCP_DATA_TO_HDMI, 0,
  347. priv->io_base + _REG(VPU_HDMI_SETTING));
  348. /* Disable all encoders */
  349. writel(0, priv->io_base + _REG(ENCI_VIDEO_EN));
  350. writel(0, priv->io_base + _REG(ENCP_VIDEO_EN));
  351. writel(0, priv->io_base + _REG(ENCL_VIDEO_EN));
  352. /* Disable VSync IRQ */
  353. writel(0, priv->io_base + _REG(VENC_INTCTRL));
  354. /* set dummy data default YUV black */
  355. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
  356. writel(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
  357. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
  358. writel_bits(0xff << 16, 0xff << 16,
  359. priv->io_base + _REG(VIU_MISC_CTRL1));
  360. writel(VPP_PPS_DUMMY_DATA_MODE,
  361. priv->io_base + _REG(VPP_DOLBY_CTRL));
  362. writel(0x1020080,
  363. priv->io_base + _REG(VPP_DUMMY_DATA1));
  364. } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  365. writel(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
  366. /* Initialize vpu fifo control registers */
  367. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  368. writel(VPP_OFIFO_SIZE_DEFAULT,
  369. priv->io_base + _REG(VPP_OFIFO_SIZE));
  370. else
  371. writel_bits(VPP_OFIFO_SIZE_MASK, 0x77f,
  372. priv->io_base + _REG(VPP_OFIFO_SIZE));
  373. writel(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4),
  374. priv->io_base + _REG(VPP_HOLD_LINES));
  375. if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  376. /* Turn off preblend */
  377. writel_bits(VPP_PREBLEND_ENABLE, 0,
  378. priv->io_base + _REG(VPP_MISC));
  379. /* Turn off POSTBLEND */
  380. writel_bits(VPP_POSTBLEND_ENABLE, 0,
  381. priv->io_base + _REG(VPP_MISC));
  382. /* Force all planes off */
  383. writel_bits(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
  384. VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
  385. VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
  386. priv->io_base + _REG(VPP_MISC));
  387. /* Setup default VD settings */
  388. writel(4096,
  389. priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
  390. writel(4096,
  391. priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
  392. }
  393. /* Disable Scalers */
  394. writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
  395. writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
  396. writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
  397. writel(VPP_VSC_BANK_LENGTH(4) | VPP_HSC_BANK_LENGTH(4) |
  398. VPP_SC_VD_EN_ENABLE,
  399. priv->io_base + _REG(VPP_SC_MISC));
  400. /* Enable minus black level for vadj1 */
  401. writel(VPP_MINUS_BLACK_LVL_VADJ1_ENABLE,
  402. priv->io_base + _REG(VPP_VADJ_CTRL));
  403. /* Write in the proper filter coefficients. */
  404. meson_vpp_write_scaling_filter_coefs(priv,
  405. vpp_filter_coefs_4point_bspline, false);
  406. meson_vpp_write_scaling_filter_coefs(priv,
  407. vpp_filter_coefs_4point_bspline, true);
  408. /* Write the VD proper filter coefficients. */
  409. meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
  410. false);
  411. meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
  412. true);
  413. /* Disable OSDs */
  414. writel_bits(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
  415. priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
  416. writel_bits(VIU_OSD1_OSD_BLK_ENABLE | VIU_OSD1_OSD_ENABLE, 0,
  417. priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
  418. /* On GXL/GXM, Use the 10bit HDR conversion matrix */
  419. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
  420. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
  421. meson_viu_load_matrix(priv);
  422. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  423. meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
  424. true);
  425. /* Initialize OSD1 fifo control register */
  426. reg = VIU_OSD_DDR_PRIORITY_URGENT |
  427. VIU_OSD_HOLD_FIFO_LINES(4) |
  428. VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
  429. VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
  430. VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
  431. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  432. reg |= meson_viu_osd_burst_length_reg(32);
  433. else
  434. reg |= meson_viu_osd_burst_length_reg(64);
  435. writel(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
  436. writel(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
  437. /* Set OSD alpha replace value */
  438. writel_bits(0xff << OSD_REPLACE_SHIFT,
  439. 0xff << OSD_REPLACE_SHIFT,
  440. priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
  441. writel_bits(0xff << OSD_REPLACE_SHIFT,
  442. 0xff << OSD_REPLACE_SHIFT,
  443. priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
  444. /* Disable VD1 AFBC */
  445. /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/
  446. writel_bits(VIU_CTRL0_VD1_AFBC_MASK, 0,
  447. priv->io_base + _REG(VIU_MISC_CTRL0));
  448. writel(0, priv->io_base + _REG(AFBC_ENABLE));
  449. writel(0x00FF00C0,
  450. priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
  451. writel(0x00FF00C0,
  452. priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
  453. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
  454. writel(VIU_OSD_BLEND_REORDER(0, 1) |
  455. VIU_OSD_BLEND_REORDER(1, 0) |
  456. VIU_OSD_BLEND_REORDER(2, 0) |
  457. VIU_OSD_BLEND_REORDER(3, 0) |
  458. VIU_OSD_BLEND_DIN_EN(1) |
  459. VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
  460. VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
  461. VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
  462. VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
  463. VIU_OSD_BLEND_HOLD_LINES(4),
  464. priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
  465. writel(OSD_BLEND_PATH_SEL_ENABLE,
  466. priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
  467. writel(OSD_BLEND_PATH_SEL_ENABLE,
  468. priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
  469. writel(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
  470. writel(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
  471. writel(0, priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0));
  472. writel(0, priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA));
  473. writel_bits(DOLBY_BYPASS_EN(0xc), DOLBY_BYPASS_EN(0xc),
  474. priv->io_base + _REG(DOLBY_PATH_CTRL));
  475. }
  476. }