meson_vpu.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Amlogic Meson Video Processing Unit driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #ifndef __MESON_VPU_H__
  9. #define __MESON_VPU_H__
  10. #include <video.h>
  11. #include "meson_registers.h"
  12. struct display_timing;
  13. struct udevice;
  14. enum {
  15. /* Maximum size we support */
  16. VPU_MAX_WIDTH = 3840,
  17. VPU_MAX_HEIGHT = 2160,
  18. VPU_MAX_LOG2_BPP = VIDEO_BPP32,
  19. };
  20. enum vpu_compatible {
  21. VPU_COMPATIBLE_GXBB = 0,
  22. VPU_COMPATIBLE_GXL = 1,
  23. VPU_COMPATIBLE_GXM = 2,
  24. VPU_COMPATIBLE_G12A = 3,
  25. };
  26. struct meson_vpu_priv {
  27. struct udevice *dev;
  28. void __iomem *io_base;
  29. void __iomem *hhi_base;
  30. void __iomem *dmc_base;
  31. };
  32. bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
  33. enum vpu_compatible family);
  34. #define hhi_update_bits(offset, mask, value) \
  35. writel_bits(mask, value, priv->hhi_base + offset)
  36. #define hhi_write(offset, value) \
  37. writel(value, priv->hhi_base + offset)
  38. #define hhi_read(offset) \
  39. readl(priv->hhi_base + offset)
  40. #define dmc_update_bits(offset, mask, value) \
  41. writel_bits(mask, value, priv->dmc_base + offset)
  42. #define dmc_write(offset, value) \
  43. writel(value, priv->dmc_base + offset)
  44. #define dmc_read(offset) \
  45. readl(priv->dmc_base + offset)
  46. #define MESON_CANVAS_ID_OSD1 0x4e
  47. /* Canvas configuration. */
  48. #define MESON_CANVAS_WRAP_NONE 0x00
  49. #define MESON_CANVAS_WRAP_X 0x01
  50. #define MESON_CANVAS_WRAP_Y 0x02
  51. #define MESON_CANVAS_BLKMODE_LINEAR 0x00
  52. #define MESON_CANVAS_BLKMODE_32x32 0x01
  53. #define MESON_CANVAS_BLKMODE_64x64 0x02
  54. void meson_canvas_setup(struct meson_vpu_priv *priv,
  55. u32 canvas_index, u32 addr,
  56. u32 stride, u32 height,
  57. unsigned int wrap,
  58. unsigned int blkmode);
  59. /* Mux VIU/VPP to ENCI */
  60. #define MESON_VIU_VPP_MUX_ENCI 0x5
  61. /* Mux VIU/VPP to ENCP */
  62. #define MESON_VIU_VPP_MUX_ENCP 0xA
  63. void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux);
  64. void meson_vpu_init(struct udevice *dev);
  65. void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced);
  66. bool meson_venc_hdmi_supported_mode(const struct display_timing *mode);
  67. void meson_vpu_setup_venc(struct udevice *dev,
  68. const struct display_timing *mode, bool is_cvbs);
  69. bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
  70. unsigned int freq);
  71. void meson_vpu_setup_vclk(struct udevice *dev,
  72. const struct display_timing *mode, bool is_cvbs);
  73. #endif