meson_venc.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Amlogic Meson Video Processing Unit driver
  4. *
  5. * Copyright (c) 2018 BayLibre, SAS.
  6. * Author: Neil Armstrong <narmstrong@baylibre.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <edid.h>
  11. #include <fdtdec.h>
  12. #include <asm/io.h>
  13. #include "meson_vpu.h"
  14. enum {
  15. MESON_VENC_MODE_NONE = 0,
  16. MESON_VENC_MODE_CVBS_PAL,
  17. MESON_VENC_MODE_CVBS_NTSC,
  18. MESON_VENC_MODE_HDMI,
  19. };
  20. enum meson_venc_source {
  21. MESON_VENC_SOURCE_NONE = 0,
  22. MESON_VENC_SOURCE_ENCI = 1,
  23. MESON_VENC_SOURCE_ENCP = 2,
  24. };
  25. #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
  26. #define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */
  27. #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
  28. #define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */
  29. struct meson_cvbs_enci_mode {
  30. unsigned int mode_tag;
  31. unsigned int hso_begin; /* HSO begin position */
  32. unsigned int hso_end; /* HSO end position */
  33. unsigned int vso_even; /* VSO even line */
  34. unsigned int vso_odd; /* VSO odd line */
  35. unsigned int macv_max_amp; /* Macrovision max amplitude */
  36. unsigned int video_prog_mode;
  37. unsigned int video_mode;
  38. unsigned int sch_adjust;
  39. unsigned int yc_delay;
  40. unsigned int pixel_start;
  41. unsigned int pixel_end;
  42. unsigned int top_field_line_start;
  43. unsigned int top_field_line_end;
  44. unsigned int bottom_field_line_start;
  45. unsigned int bottom_field_line_end;
  46. unsigned int video_saturation;
  47. unsigned int video_contrast;
  48. unsigned int video_brightness;
  49. unsigned int video_hue;
  50. unsigned int analog_sync_adj;
  51. };
  52. struct meson_cvbs_enci_mode meson_cvbs_enci_pal = {
  53. .mode_tag = MESON_VENC_MODE_CVBS_PAL,
  54. .hso_begin = 3,
  55. .hso_end = 129,
  56. .vso_even = 3,
  57. .vso_odd = 260,
  58. .macv_max_amp = 7,
  59. .video_prog_mode = 0xff,
  60. .video_mode = 0x13,
  61. .sch_adjust = 0x28,
  62. .yc_delay = 0x343,
  63. .pixel_start = 251,
  64. .pixel_end = 1691,
  65. .top_field_line_start = 22,
  66. .top_field_line_end = 310,
  67. .bottom_field_line_start = 23,
  68. .bottom_field_line_end = 311,
  69. .video_saturation = 9,
  70. .video_contrast = 0,
  71. .video_brightness = 0,
  72. .video_hue = 0,
  73. .analog_sync_adj = 0x8080,
  74. };
  75. struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc = {
  76. .mode_tag = MESON_VENC_MODE_CVBS_NTSC,
  77. .hso_begin = 5,
  78. .hso_end = 129,
  79. .vso_even = 3,
  80. .vso_odd = 260,
  81. .macv_max_amp = 0xb,
  82. .video_prog_mode = 0xf0,
  83. .video_mode = 0x8,
  84. .sch_adjust = 0x20,
  85. .yc_delay = 0x333,
  86. .pixel_start = 227,
  87. .pixel_end = 1667,
  88. .top_field_line_start = 18,
  89. .top_field_line_end = 258,
  90. .bottom_field_line_start = 19,
  91. .bottom_field_line_end = 259,
  92. .video_saturation = 18,
  93. .video_contrast = 3,
  94. .video_brightness = 0,
  95. .video_hue = 0,
  96. .analog_sync_adj = 0x9c00,
  97. };
  98. union meson_hdmi_venc_mode {
  99. struct {
  100. unsigned int mode_tag;
  101. unsigned int hso_begin;
  102. unsigned int hso_end;
  103. unsigned int vso_even;
  104. unsigned int vso_odd;
  105. unsigned int macv_max_amp;
  106. unsigned int video_prog_mode;
  107. unsigned int video_mode;
  108. unsigned int sch_adjust;
  109. unsigned int yc_delay;
  110. unsigned int pixel_start;
  111. unsigned int pixel_end;
  112. unsigned int top_field_line_start;
  113. unsigned int top_field_line_end;
  114. unsigned int bottom_field_line_start;
  115. unsigned int bottom_field_line_end;
  116. } enci;
  117. struct {
  118. unsigned int dvi_settings;
  119. unsigned int video_mode;
  120. unsigned int video_mode_adv;
  121. unsigned int video_prog_mode;
  122. bool video_prog_mode_present;
  123. unsigned int video_sync_mode;
  124. bool video_sync_mode_present;
  125. unsigned int video_yc_dly;
  126. bool video_yc_dly_present;
  127. unsigned int video_rgb_ctrl;
  128. bool video_rgb_ctrl_present;
  129. unsigned int video_filt_ctrl;
  130. bool video_filt_ctrl_present;
  131. unsigned int video_ofld_voav_ofst;
  132. bool video_ofld_voav_ofst_present;
  133. unsigned int yfp1_htime;
  134. unsigned int yfp2_htime;
  135. unsigned int max_pxcnt;
  136. unsigned int hspuls_begin;
  137. unsigned int hspuls_end;
  138. unsigned int hspuls_switch;
  139. unsigned int vspuls_begin;
  140. unsigned int vspuls_end;
  141. unsigned int vspuls_bline;
  142. unsigned int vspuls_eline;
  143. unsigned int eqpuls_begin;
  144. bool eqpuls_begin_present;
  145. unsigned int eqpuls_end;
  146. bool eqpuls_end_present;
  147. unsigned int eqpuls_bline;
  148. bool eqpuls_bline_present;
  149. unsigned int eqpuls_eline;
  150. bool eqpuls_eline_present;
  151. unsigned int havon_begin;
  152. unsigned int havon_end;
  153. unsigned int vavon_bline;
  154. unsigned int vavon_eline;
  155. unsigned int hso_begin;
  156. unsigned int hso_end;
  157. unsigned int vso_begin;
  158. unsigned int vso_end;
  159. unsigned int vso_bline;
  160. unsigned int vso_eline;
  161. bool vso_eline_present;
  162. unsigned int sy_val;
  163. bool sy_val_present;
  164. unsigned int sy2_val;
  165. bool sy2_val_present;
  166. unsigned int max_lncnt;
  167. } encp;
  168. };
  169. union meson_hdmi_venc_mode meson_hdmi_enci_mode_480i = {
  170. .enci = {
  171. .hso_begin = 5,
  172. .hso_end = 129,
  173. .vso_even = 3,
  174. .vso_odd = 260,
  175. .macv_max_amp = 0xb,
  176. .video_prog_mode = 0xf0,
  177. .video_mode = 0x8,
  178. .sch_adjust = 0x20,
  179. .yc_delay = 0,
  180. .pixel_start = 227,
  181. .pixel_end = 1667,
  182. .top_field_line_start = 18,
  183. .top_field_line_end = 258,
  184. .bottom_field_line_start = 19,
  185. .bottom_field_line_end = 259,
  186. },
  187. };
  188. union meson_hdmi_venc_mode meson_hdmi_enci_mode_576i = {
  189. .enci = {
  190. .hso_begin = 3,
  191. .hso_end = 129,
  192. .vso_even = 3,
  193. .vso_odd = 260,
  194. .macv_max_amp = 0x7,
  195. .video_prog_mode = 0xff,
  196. .video_mode = 0x13,
  197. .sch_adjust = 0x28,
  198. .yc_delay = 0x333,
  199. .pixel_start = 251,
  200. .pixel_end = 1691,
  201. .top_field_line_start = 22,
  202. .top_field_line_end = 310,
  203. .bottom_field_line_start = 23,
  204. .bottom_field_line_end = 311,
  205. },
  206. };
  207. union meson_hdmi_venc_mode meson_hdmi_encp_mode_480p = {
  208. .encp = {
  209. .dvi_settings = 0x21,
  210. .video_mode = 0x4000,
  211. .video_mode_adv = 0x9,
  212. .video_prog_mode = 0,
  213. .video_prog_mode_present = true,
  214. .video_sync_mode = 7,
  215. .video_sync_mode_present = true,
  216. /* video_yc_dly */
  217. /* video_rgb_ctrl */
  218. .video_filt_ctrl = 0x2052,
  219. .video_filt_ctrl_present = true,
  220. /* video_ofld_voav_ofst */
  221. .yfp1_htime = 244,
  222. .yfp2_htime = 1630,
  223. .max_pxcnt = 1715,
  224. .hspuls_begin = 0x22,
  225. .hspuls_end = 0xa0,
  226. .hspuls_switch = 88,
  227. .vspuls_begin = 0,
  228. .vspuls_end = 1589,
  229. .vspuls_bline = 0,
  230. .vspuls_eline = 5,
  231. .havon_begin = 249,
  232. .havon_end = 1689,
  233. .vavon_bline = 42,
  234. .vavon_eline = 521,
  235. /* eqpuls_begin */
  236. /* eqpuls_end */
  237. /* eqpuls_bline */
  238. /* eqpuls_eline */
  239. .hso_begin = 3,
  240. .hso_end = 5,
  241. .vso_begin = 3,
  242. .vso_end = 5,
  243. .vso_bline = 0,
  244. /* vso_eline */
  245. .sy_val = 8,
  246. .sy_val_present = true,
  247. .sy2_val = 0x1d8,
  248. .sy2_val_present = true,
  249. .max_lncnt = 524,
  250. },
  251. };
  252. union meson_hdmi_venc_mode meson_hdmi_encp_mode_576p = {
  253. .encp = {
  254. .dvi_settings = 0x21,
  255. .video_mode = 0x4000,
  256. .video_mode_adv = 0x9,
  257. .video_prog_mode = 0,
  258. .video_prog_mode_present = true,
  259. .video_sync_mode = 7,
  260. .video_sync_mode_present = true,
  261. /* video_yc_dly */
  262. /* video_rgb_ctrl */
  263. .video_filt_ctrl = 0x52,
  264. .video_filt_ctrl_present = true,
  265. /* video_ofld_voav_ofst */
  266. .yfp1_htime = 235,
  267. .yfp2_htime = 1674,
  268. .max_pxcnt = 1727,
  269. .hspuls_begin = 0,
  270. .hspuls_end = 0x80,
  271. .hspuls_switch = 88,
  272. .vspuls_begin = 0,
  273. .vspuls_end = 1599,
  274. .vspuls_bline = 0,
  275. .vspuls_eline = 4,
  276. .havon_begin = 235,
  277. .havon_end = 1674,
  278. .vavon_bline = 44,
  279. .vavon_eline = 619,
  280. /* eqpuls_begin */
  281. /* eqpuls_end */
  282. /* eqpuls_bline */
  283. /* eqpuls_eline */
  284. .hso_begin = 0x80,
  285. .hso_end = 0,
  286. .vso_begin = 0,
  287. .vso_end = 5,
  288. .vso_bline = 0,
  289. /* vso_eline */
  290. .sy_val = 8,
  291. .sy_val_present = true,
  292. .sy2_val = 0x1d8,
  293. .sy2_val_present = true,
  294. .max_lncnt = 624,
  295. },
  296. };
  297. union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p60 = {
  298. .encp = {
  299. .dvi_settings = 0x2029,
  300. .video_mode = 0x4040,
  301. .video_mode_adv = 0x19,
  302. /* video_prog_mode */
  303. /* video_sync_mode */
  304. /* video_yc_dly */
  305. /* video_rgb_ctrl */
  306. /* video_filt_ctrl */
  307. /* video_ofld_voav_ofst */
  308. .yfp1_htime = 648,
  309. .yfp2_htime = 3207,
  310. .max_pxcnt = 3299,
  311. .hspuls_begin = 80,
  312. .hspuls_end = 240,
  313. .hspuls_switch = 80,
  314. .vspuls_begin = 688,
  315. .vspuls_end = 3248,
  316. .vspuls_bline = 4,
  317. .vspuls_eline = 8,
  318. .havon_begin = 648,
  319. .havon_end = 3207,
  320. .vavon_bline = 29,
  321. .vavon_eline = 748,
  322. /* eqpuls_begin */
  323. /* eqpuls_end */
  324. /* eqpuls_bline */
  325. /* eqpuls_eline */
  326. .hso_begin = 256,
  327. .hso_end = 168,
  328. .vso_begin = 168,
  329. .vso_end = 256,
  330. .vso_bline = 0,
  331. .vso_eline = 5,
  332. .vso_eline_present = true,
  333. /* sy_val */
  334. /* sy2_val */
  335. .max_lncnt = 749,
  336. },
  337. };
  338. union meson_hdmi_venc_mode meson_hdmi_encp_mode_720p50 = {
  339. .encp = {
  340. .dvi_settings = 0x202d,
  341. .video_mode = 0x4040,
  342. .video_mode_adv = 0x19,
  343. .video_prog_mode = 0x100,
  344. .video_prog_mode_present = true,
  345. .video_sync_mode = 0x407,
  346. .video_sync_mode_present = true,
  347. .video_yc_dly = 0,
  348. .video_yc_dly_present = true,
  349. /* video_rgb_ctrl */
  350. /* video_filt_ctrl */
  351. /* video_ofld_voav_ofst */
  352. .yfp1_htime = 648,
  353. .yfp2_htime = 3207,
  354. .max_pxcnt = 3959,
  355. .hspuls_begin = 80,
  356. .hspuls_end = 240,
  357. .hspuls_switch = 80,
  358. .vspuls_begin = 688,
  359. .vspuls_end = 3248,
  360. .vspuls_bline = 4,
  361. .vspuls_eline = 8,
  362. .havon_begin = 648,
  363. .havon_end = 3207,
  364. .vavon_bline = 29,
  365. .vavon_eline = 748,
  366. /* eqpuls_begin */
  367. /* eqpuls_end */
  368. /* eqpuls_bline */
  369. /* eqpuls_eline */
  370. .hso_begin = 128,
  371. .hso_end = 208,
  372. .vso_begin = 128,
  373. .vso_end = 128,
  374. .vso_bline = 0,
  375. .vso_eline = 5,
  376. .vso_eline_present = true,
  377. /* sy_val */
  378. /* sy2_val */
  379. .max_lncnt = 749,
  380. },
  381. };
  382. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i60 = {
  383. .encp = {
  384. .dvi_settings = 0x2029,
  385. .video_mode = 0x5ffc,
  386. .video_mode_adv = 0x19,
  387. .video_prog_mode = 0x100,
  388. .video_prog_mode_present = true,
  389. .video_sync_mode = 0x207,
  390. .video_sync_mode_present = true,
  391. /* video_yc_dly */
  392. /* video_rgb_ctrl */
  393. /* video_filt_ctrl */
  394. .video_ofld_voav_ofst = 0x11,
  395. .video_ofld_voav_ofst_present = true,
  396. .yfp1_htime = 516,
  397. .yfp2_htime = 4355,
  398. .max_pxcnt = 4399,
  399. .hspuls_begin = 88,
  400. .hspuls_end = 264,
  401. .hspuls_switch = 88,
  402. .vspuls_begin = 440,
  403. .vspuls_end = 2200,
  404. .vspuls_bline = 0,
  405. .vspuls_eline = 4,
  406. .havon_begin = 516,
  407. .havon_end = 4355,
  408. .vavon_bline = 20,
  409. .vavon_eline = 559,
  410. .eqpuls_begin = 2288,
  411. .eqpuls_begin_present = true,
  412. .eqpuls_end = 2464,
  413. .eqpuls_end_present = true,
  414. .eqpuls_bline = 0,
  415. .eqpuls_bline_present = true,
  416. .eqpuls_eline = 4,
  417. .eqpuls_eline_present = true,
  418. .hso_begin = 264,
  419. .hso_end = 176,
  420. .vso_begin = 88,
  421. .vso_end = 88,
  422. .vso_bline = 0,
  423. .vso_eline = 5,
  424. .vso_eline_present = true,
  425. /* sy_val */
  426. /* sy2_val */
  427. .max_lncnt = 1124,
  428. },
  429. };
  430. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080i50 = {
  431. .encp = {
  432. .dvi_settings = 0x202d,
  433. .video_mode = 0x5ffc,
  434. .video_mode_adv = 0x19,
  435. .video_prog_mode = 0x100,
  436. .video_prog_mode_present = true,
  437. .video_sync_mode = 0x7,
  438. .video_sync_mode_present = true,
  439. /* video_yc_dly */
  440. /* video_rgb_ctrl */
  441. /* video_filt_ctrl */
  442. .video_ofld_voav_ofst = 0x11,
  443. .video_ofld_voav_ofst_present = true,
  444. .yfp1_htime = 526,
  445. .yfp2_htime = 4365,
  446. .max_pxcnt = 5279,
  447. .hspuls_begin = 88,
  448. .hspuls_end = 264,
  449. .hspuls_switch = 88,
  450. .vspuls_begin = 440,
  451. .vspuls_end = 2200,
  452. .vspuls_bline = 0,
  453. .vspuls_eline = 4,
  454. .havon_begin = 526,
  455. .havon_end = 4365,
  456. .vavon_bline = 20,
  457. .vavon_eline = 559,
  458. .eqpuls_begin = 2288,
  459. .eqpuls_begin_present = true,
  460. .eqpuls_end = 2464,
  461. .eqpuls_end_present = true,
  462. .eqpuls_bline = 0,
  463. .eqpuls_bline_present = true,
  464. .eqpuls_eline = 4,
  465. .eqpuls_eline_present = true,
  466. .hso_begin = 142,
  467. .hso_end = 230,
  468. .vso_begin = 142,
  469. .vso_end = 142,
  470. .vso_bline = 0,
  471. .vso_eline = 5,
  472. .vso_eline_present = true,
  473. /* sy_val */
  474. /* sy2_val */
  475. .max_lncnt = 1124,
  476. },
  477. };
  478. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p24 = {
  479. .encp = {
  480. .dvi_settings = 0xd,
  481. .video_mode = 0x4040,
  482. .video_mode_adv = 0x18,
  483. .video_prog_mode = 0x100,
  484. .video_prog_mode_present = true,
  485. .video_sync_mode = 0x7,
  486. .video_sync_mode_present = true,
  487. .video_yc_dly = 0,
  488. .video_yc_dly_present = true,
  489. .video_rgb_ctrl = 2,
  490. .video_rgb_ctrl_present = true,
  491. .video_filt_ctrl = 0x1052,
  492. .video_filt_ctrl_present = true,
  493. /* video_ofld_voav_ofst */
  494. .yfp1_htime = 271,
  495. .yfp2_htime = 2190,
  496. .max_pxcnt = 2749,
  497. .hspuls_begin = 44,
  498. .hspuls_end = 132,
  499. .hspuls_switch = 44,
  500. .vspuls_begin = 220,
  501. .vspuls_end = 2140,
  502. .vspuls_bline = 0,
  503. .vspuls_eline = 4,
  504. .havon_begin = 271,
  505. .havon_end = 2190,
  506. .vavon_bline = 41,
  507. .vavon_eline = 1120,
  508. /* eqpuls_begin */
  509. /* eqpuls_end */
  510. .eqpuls_bline = 0,
  511. .eqpuls_bline_present = true,
  512. .eqpuls_eline = 4,
  513. .eqpuls_eline_present = true,
  514. .hso_begin = 79,
  515. .hso_end = 123,
  516. .vso_begin = 79,
  517. .vso_end = 79,
  518. .vso_bline = 0,
  519. .vso_eline = 5,
  520. .vso_eline_present = true,
  521. /* sy_val */
  522. /* sy2_val */
  523. .max_lncnt = 1124,
  524. },
  525. };
  526. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p30 = {
  527. .encp = {
  528. .dvi_settings = 0x1,
  529. .video_mode = 0x4040,
  530. .video_mode_adv = 0x18,
  531. .video_prog_mode = 0x100,
  532. .video_prog_mode_present = true,
  533. /* video_sync_mode */
  534. /* video_yc_dly */
  535. /* video_rgb_ctrl */
  536. .video_filt_ctrl = 0x1052,
  537. .video_filt_ctrl_present = true,
  538. /* video_ofld_voav_ofst */
  539. .yfp1_htime = 140,
  540. .yfp2_htime = 2060,
  541. .max_pxcnt = 2199,
  542. .hspuls_begin = 2156,
  543. .hspuls_end = 44,
  544. .hspuls_switch = 44,
  545. .vspuls_begin = 140,
  546. .vspuls_end = 2059,
  547. .vspuls_bline = 0,
  548. .vspuls_eline = 4,
  549. .havon_begin = 148,
  550. .havon_end = 2067,
  551. .vavon_bline = 41,
  552. .vavon_eline = 1120,
  553. /* eqpuls_begin */
  554. /* eqpuls_end */
  555. /* eqpuls_bline */
  556. /* eqpuls_eline */
  557. .hso_begin = 44,
  558. .hso_end = 2156,
  559. .vso_begin = 2100,
  560. .vso_end = 2164,
  561. .vso_bline = 0,
  562. .vso_eline = 5,
  563. .vso_eline_present = true,
  564. /* sy_val */
  565. /* sy2_val */
  566. .max_lncnt = 1124,
  567. },
  568. };
  569. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p50 = {
  570. .encp = {
  571. .dvi_settings = 0xd,
  572. .video_mode = 0x4040,
  573. .video_mode_adv = 0x18,
  574. .video_prog_mode = 0x100,
  575. .video_prog_mode_present = true,
  576. .video_sync_mode = 0x7,
  577. .video_sync_mode_present = true,
  578. .video_yc_dly = 0,
  579. .video_yc_dly_present = true,
  580. .video_rgb_ctrl = 2,
  581. .video_rgb_ctrl_present = true,
  582. /* video_filt_ctrl */
  583. /* video_ofld_voav_ofst */
  584. .yfp1_htime = 271,
  585. .yfp2_htime = 2190,
  586. .max_pxcnt = 2639,
  587. .hspuls_begin = 44,
  588. .hspuls_end = 132,
  589. .hspuls_switch = 44,
  590. .vspuls_begin = 220,
  591. .vspuls_end = 2140,
  592. .vspuls_bline = 0,
  593. .vspuls_eline = 4,
  594. .havon_begin = 271,
  595. .havon_end = 2190,
  596. .vavon_bline = 41,
  597. .vavon_eline = 1120,
  598. /* eqpuls_begin */
  599. /* eqpuls_end */
  600. .eqpuls_bline = 0,
  601. .eqpuls_bline_present = true,
  602. .eqpuls_eline = 4,
  603. .eqpuls_eline_present = true,
  604. .hso_begin = 79,
  605. .hso_end = 123,
  606. .vso_begin = 79,
  607. .vso_end = 79,
  608. .vso_bline = 0,
  609. .vso_eline = 5,
  610. .vso_eline_present = true,
  611. /* sy_val */
  612. /* sy2_val */
  613. .max_lncnt = 1124,
  614. },
  615. };
  616. union meson_hdmi_venc_mode meson_hdmi_encp_mode_1080p60 = {
  617. .encp = {
  618. .dvi_settings = 0x1,
  619. .video_mode = 0x4040,
  620. .video_mode_adv = 0x18,
  621. .video_prog_mode = 0x100,
  622. .video_prog_mode_present = true,
  623. /* video_sync_mode */
  624. /* video_yc_dly */
  625. /* video_rgb_ctrl */
  626. .video_filt_ctrl = 0x1052,
  627. .video_filt_ctrl_present = true,
  628. /* video_ofld_voav_ofst */
  629. .yfp1_htime = 140,
  630. .yfp2_htime = 2060,
  631. .max_pxcnt = 2199,
  632. .hspuls_begin = 2156,
  633. .hspuls_end = 44,
  634. .hspuls_switch = 44,
  635. .vspuls_begin = 140,
  636. .vspuls_end = 2059,
  637. .vspuls_bline = 0,
  638. .vspuls_eline = 4,
  639. .havon_begin = 148,
  640. .havon_end = 2067,
  641. .vavon_bline = 41,
  642. .vavon_eline = 1120,
  643. /* eqpuls_begin */
  644. /* eqpuls_end */
  645. /* eqpuls_bline */
  646. /* eqpuls_eline */
  647. .hso_begin = 44,
  648. .hso_end = 2156,
  649. .vso_begin = 2100,
  650. .vso_end = 2164,
  651. .vso_bline = 0,
  652. .vso_eline = 5,
  653. .vso_eline_present = true,
  654. /* sy_val */
  655. /* sy2_val */
  656. .max_lncnt = 1124,
  657. },
  658. };
  659. static signed int to_signed(unsigned int a)
  660. {
  661. if (a <= 7)
  662. return a;
  663. else
  664. return a - 16;
  665. }
  666. static unsigned long modulo(unsigned long a, unsigned long b)
  667. {
  668. if (a >= b)
  669. return a - b;
  670. else
  671. return a;
  672. }
  673. bool meson_venc_hdmi_supported_mode(const struct display_timing *mode)
  674. {
  675. if (mode->flags & ~(DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_HSYNC_HIGH |
  676. DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_VSYNC_HIGH))
  677. return false;
  678. if (mode->hactive.typ < 640 || mode->hactive.typ > 1920)
  679. return false;
  680. if (mode->vactive.typ < 480 || mode->vactive.typ > 1200)
  681. return false;
  682. return true;
  683. }
  684. static void meson_venc_hdmi_get_dmt_vmode(const struct display_timing *mode,
  685. union meson_hdmi_venc_mode *dmt_mode)
  686. {
  687. memset(dmt_mode, 0, sizeof(*dmt_mode));
  688. dmt_mode->encp.dvi_settings = 0x21;
  689. dmt_mode->encp.video_mode = 0x4040;
  690. dmt_mode->encp.video_mode_adv = 0x18;
  691. dmt_mode->encp.max_pxcnt = mode->hactive.typ +
  692. mode->hfront_porch.typ +
  693. mode->hback_porch.typ +
  694. mode->hsync_len.typ - 1;
  695. dmt_mode->encp.havon_begin = mode->hback_porch.typ +
  696. mode->hsync_len.typ;
  697. dmt_mode->encp.havon_end = dmt_mode->encp.havon_begin +
  698. mode->hactive.typ - 1;
  699. dmt_mode->encp.vavon_bline = mode->vback_porch.typ +
  700. mode->vsync_len.typ;
  701. dmt_mode->encp.vavon_eline = dmt_mode->encp.vavon_bline +
  702. mode->vactive.typ - 1;
  703. /* to investigate */
  704. dmt_mode->encp.hso_begin = 0;
  705. dmt_mode->encp.hso_end = mode->hsync_len.typ;
  706. dmt_mode->encp.vso_begin = 30;
  707. dmt_mode->encp.vso_end = 50;
  708. dmt_mode->encp.vso_bline = 0;
  709. dmt_mode->encp.vso_eline = mode->vsync_len.typ;
  710. dmt_mode->encp.vso_eline_present = true;
  711. dmt_mode->encp.max_lncnt = mode->vactive.typ +
  712. mode->vfront_porch.typ +
  713. mode->vback_porch.typ +
  714. mode->vsync_len.typ - 1;
  715. }
  716. static void meson_venc_hdmi_mode_set(struct meson_vpu_priv *priv,
  717. const struct display_timing *mode)
  718. {
  719. union meson_hdmi_venc_mode *vmode = NULL;
  720. union meson_hdmi_venc_mode vmode_dmt;
  721. bool use_enci = false;
  722. bool venc_repeat = false;
  723. bool hdmi_repeat = false;
  724. unsigned int venc_hdmi_latency = 2;
  725. unsigned long total_pixels_venc = 0;
  726. unsigned long active_pixels_venc = 0;
  727. unsigned long front_porch_venc = 0;
  728. unsigned long hsync_pixels_venc = 0;
  729. unsigned long de_h_begin = 0;
  730. unsigned long de_h_end = 0;
  731. unsigned long de_v_begin_even = 0;
  732. unsigned long de_v_end_even = 0;
  733. unsigned long de_v_begin_odd = 0;
  734. unsigned long de_v_end_odd = 0;
  735. unsigned long hs_begin = 0;
  736. unsigned long hs_end = 0;
  737. unsigned long vs_adjust = 0;
  738. unsigned long vs_bline_evn = 0;
  739. unsigned long vs_eline_evn = 0;
  740. unsigned long vs_bline_odd = 0;
  741. unsigned long vs_eline_odd = 0;
  742. unsigned long vso_begin_evn = 0;
  743. unsigned long vso_begin_odd = 0;
  744. unsigned int eof_lines;
  745. unsigned int sof_lines;
  746. unsigned int vsync_lines;
  747. u32 reg;
  748. /* Use VENCI for 480i and 576i and double HDMI pixels */
  749. if (mode->flags & DISPLAY_FLAGS_DOUBLECLK) {
  750. hdmi_repeat = true;
  751. use_enci = true;
  752. venc_hdmi_latency = 1;
  753. }
  754. meson_venc_hdmi_get_dmt_vmode(mode, &vmode_dmt);
  755. vmode = &vmode_dmt;
  756. use_enci = false;
  757. debug(" max_pxcnt %04d, max_lncnt %04d\n"
  758. " havon_begin %04d, havon_end %04d\n"
  759. " vavon_bline %04d, vavon_eline %04d\n"
  760. " hso_begin %04d, hso_end %04d\n"
  761. " vso_begin %04d, vso_end %04d\n"
  762. " vso_bline %04d, vso_eline %04d\n",
  763. vmode->encp.max_pxcnt, vmode->encp.max_lncnt,
  764. vmode->encp.havon_begin, vmode->encp.havon_end,
  765. vmode->encp.vavon_bline, vmode->encp.vavon_eline,
  766. vmode->encp.hso_begin, vmode->encp.hso_end,
  767. vmode->encp.vso_begin, vmode->encp.vso_end,
  768. vmode->encp.vso_bline, vmode->encp.vso_eline);
  769. eof_lines = mode->vfront_porch.typ;
  770. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  771. eof_lines /= 2;
  772. sof_lines = mode->vback_porch.typ;
  773. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  774. sof_lines /= 2;
  775. vsync_lines = mode->vsync_len.typ;
  776. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  777. vsync_lines /= 2;
  778. total_pixels_venc = mode->hback_porch.typ + mode->hactive.typ +
  779. mode->hfront_porch.typ + mode->hsync_len.typ;
  780. if (hdmi_repeat)
  781. total_pixels_venc /= 2;
  782. if (venc_repeat)
  783. total_pixels_venc *= 2;
  784. active_pixels_venc = mode->hactive.typ;
  785. if (hdmi_repeat)
  786. active_pixels_venc /= 2;
  787. if (venc_repeat)
  788. active_pixels_venc *= 2;
  789. front_porch_venc = mode->hfront_porch.typ;
  790. if (hdmi_repeat)
  791. front_porch_venc /= 2;
  792. if (venc_repeat)
  793. front_porch_venc *= 2;
  794. hsync_pixels_venc = mode->hsync_len.typ;
  795. if (hdmi_repeat)
  796. hsync_pixels_venc /= 2;
  797. if (venc_repeat)
  798. hsync_pixels_venc *= 2;
  799. /* Disable VDACs */
  800. writel_bits(0xff, 0xff,
  801. priv->io_base + _REG(VENC_VDAC_SETTING));
  802. writel(0, priv->io_base + _REG(ENCI_VIDEO_EN));
  803. writel(0, priv->io_base + _REG(ENCP_VIDEO_EN));
  804. debug("use_enci: %d, hdmi_repeat: %d\n", use_enci, hdmi_repeat);
  805. if (use_enci) {
  806. unsigned int lines_f0;
  807. unsigned int lines_f1;
  808. /* CVBS Filter settings */
  809. writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
  810. priv->io_base + _REG(ENCI_CFILT_CTRL));
  811. writel(ENCI_CFILT_CMPT_CR_DLY(2) |
  812. ENCI_CFILT_CMPT_CB_DLY(1),
  813. priv->io_base + _REG(ENCI_CFILT_CTRL2));
  814. /* Digital Video Select : Interlace, clk27 clk, external */
  815. writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
  816. /* Reset Video Mode */
  817. writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
  818. writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
  819. /* Horizontal sync signal output */
  820. writel(vmode->enci.hso_begin,
  821. priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
  822. writel(vmode->enci.hso_end,
  823. priv->io_base + _REG(ENCI_SYNC_HSO_END));
  824. /* Vertical Sync lines */
  825. writel(vmode->enci.vso_even,
  826. priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
  827. writel(vmode->enci.vso_odd,
  828. priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
  829. /* Macrovision max amplitude change */
  830. writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
  831. ENCI_MACV_MAX_AMP_VAL(vmode->enci.macv_max_amp),
  832. priv->io_base + _REG(ENCI_MACV_MAX_AMP));
  833. /* Video mode */
  834. writel(vmode->enci.video_prog_mode,
  835. priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
  836. writel(vmode->enci.video_mode,
  837. priv->io_base + _REG(ENCI_VIDEO_MODE));
  838. /*
  839. * Advanced Video Mode :
  840. * Demux shifting 0x2
  841. * Blank line end at line17/22
  842. * High bandwidth Luma Filter
  843. * Low bandwidth Chroma Filter
  844. * Bypass luma low pass filter
  845. * No macrovision on CSYNC
  846. */
  847. writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
  848. ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
  849. ENCI_VIDEO_MODE_ADV_YBW_HIGH,
  850. priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
  851. writel(vmode->enci.sch_adjust,
  852. priv->io_base + _REG(ENCI_VIDEO_SCH));
  853. /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
  854. writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
  855. if (vmode->enci.yc_delay)
  856. writel(vmode->enci.yc_delay,
  857. priv->io_base + _REG(ENCI_YC_DELAY));
  858. /* UNreset Interlaced TV Encoder */
  859. writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
  860. /*
  861. * Enable Vfifo2vd and set Y_Cb_Y_Cr:
  862. * Corresponding value:
  863. * Y => 00 or 10
  864. * Cb => 01
  865. * Cr => 11
  866. * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
  867. */
  868. writel(ENCI_VFIFO2VD_CTL_ENABLE |
  869. ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
  870. priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
  871. /* Timings */
  872. writel(vmode->enci.pixel_start,
  873. priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
  874. writel(vmode->enci.pixel_end,
  875. priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
  876. writel(vmode->enci.top_field_line_start,
  877. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
  878. writel(vmode->enci.top_field_line_end,
  879. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
  880. writel(vmode->enci.bottom_field_line_start,
  881. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
  882. writel(vmode->enci.bottom_field_line_end,
  883. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
  884. /* Select ENCI for VIU */
  885. meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
  886. /* Interlace video enable */
  887. writel(ENCI_VIDEO_EN_ENABLE,
  888. priv->io_base + _REG(ENCI_VIDEO_EN));
  889. lines_f0 = mode->vback_porch.typ + mode->vactive.typ +
  890. mode->vback_porch.typ + mode->vsync_len.typ;
  891. lines_f0 = lines_f0 >> 1;
  892. lines_f1 = lines_f0 + 1;
  893. de_h_begin = modulo(readl(priv->io_base +
  894. _REG(ENCI_VFIFO2VD_PIXEL_START))
  895. + venc_hdmi_latency,
  896. total_pixels_venc);
  897. de_h_end = modulo(de_h_begin + active_pixels_venc,
  898. total_pixels_venc);
  899. writel(de_h_begin,
  900. priv->io_base + _REG(ENCI_DE_H_BEGIN));
  901. writel(de_h_end,
  902. priv->io_base + _REG(ENCI_DE_H_END));
  903. de_v_begin_even = readl(priv->io_base +
  904. _REG(ENCI_VFIFO2VD_LINE_TOP_START));
  905. de_v_end_even = de_v_begin_even + mode->vactive.typ;
  906. de_v_begin_odd = readl(priv->io_base +
  907. _REG(ENCI_VFIFO2VD_LINE_BOT_START));
  908. de_v_end_odd = de_v_begin_odd + mode->vactive.typ;
  909. writel(de_v_begin_even,
  910. priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
  911. writel(de_v_end_even,
  912. priv->io_base + _REG(ENCI_DE_V_END_EVEN));
  913. writel(de_v_begin_odd,
  914. priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
  915. writel(de_v_end_odd,
  916. priv->io_base + _REG(ENCI_DE_V_END_ODD));
  917. /* Program Hsync timing */
  918. hs_begin = de_h_end + front_porch_venc;
  919. if (de_h_end + front_porch_venc >= total_pixels_venc) {
  920. hs_begin -= total_pixels_venc;
  921. vs_adjust = 1;
  922. } else {
  923. hs_begin = de_h_end + front_porch_venc;
  924. vs_adjust = 0;
  925. }
  926. hs_end = modulo(hs_begin + hsync_pixels_venc,
  927. total_pixels_venc);
  928. writel(hs_begin,
  929. priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
  930. writel(hs_end,
  931. priv->io_base + _REG(ENCI_DVI_HSO_END));
  932. /* Program Vsync timing for even field */
  933. if (((de_v_end_odd - 1) + eof_lines + vs_adjust) >= lines_f1) {
  934. vs_bline_evn = (de_v_end_odd - 1)
  935. + eof_lines
  936. + vs_adjust
  937. - lines_f1;
  938. vs_eline_evn = vs_bline_evn + vsync_lines;
  939. writel(vs_bline_evn,
  940. priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
  941. writel(vs_eline_evn,
  942. priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
  943. writel(hs_begin,
  944. priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
  945. writel(hs_begin,
  946. priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
  947. } else {
  948. vs_bline_odd = (de_v_end_odd - 1)
  949. + eof_lines
  950. + vs_adjust;
  951. writel(vs_bline_odd,
  952. priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
  953. writel(hs_begin,
  954. priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
  955. if ((vs_bline_odd + vsync_lines) >= lines_f1) {
  956. vs_eline_evn = vs_bline_odd
  957. + vsync_lines
  958. - lines_f1;
  959. writel(vs_eline_evn, priv->io_base
  960. + _REG(ENCI_DVI_VSO_ELINE_EVN));
  961. writel(hs_begin, priv->io_base
  962. + _REG(ENCI_DVI_VSO_END_EVN));
  963. } else {
  964. vs_eline_odd = vs_bline_odd
  965. + vsync_lines;
  966. writel(vs_eline_odd, priv->io_base
  967. + _REG(ENCI_DVI_VSO_ELINE_ODD));
  968. writel(hs_begin, priv->io_base
  969. + _REG(ENCI_DVI_VSO_END_ODD));
  970. }
  971. }
  972. /* Program Vsync timing for odd field */
  973. if (((de_v_end_even - 1) + (eof_lines + 1)) >= lines_f0) {
  974. vs_bline_odd = (de_v_end_even - 1)
  975. + (eof_lines + 1)
  976. - lines_f0;
  977. vs_eline_odd = vs_bline_odd + vsync_lines;
  978. writel(vs_bline_odd,
  979. priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
  980. writel(vs_eline_odd,
  981. priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
  982. vso_begin_odd = modulo(hs_begin
  983. + (total_pixels_venc >> 1),
  984. total_pixels_venc);
  985. writel(vso_begin_odd,
  986. priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
  987. writel(vso_begin_odd,
  988. priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
  989. } else {
  990. vs_bline_evn = (de_v_end_even - 1)
  991. + (eof_lines + 1);
  992. writel(vs_bline_evn,
  993. priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
  994. vso_begin_evn = modulo(hs_begin
  995. + (total_pixels_venc >> 1),
  996. total_pixels_venc);
  997. writel(vso_begin_evn, priv->io_base
  998. + _REG(ENCI_DVI_VSO_BEGIN_EVN));
  999. if (vs_bline_evn + vsync_lines >= lines_f0) {
  1000. vs_eline_odd = vs_bline_evn
  1001. + vsync_lines
  1002. - lines_f0;
  1003. writel(vs_eline_odd, priv->io_base
  1004. + _REG(ENCI_DVI_VSO_ELINE_ODD));
  1005. writel(vso_begin_evn, priv->io_base
  1006. + _REG(ENCI_DVI_VSO_END_ODD));
  1007. } else {
  1008. vs_eline_evn = vs_bline_evn + vsync_lines;
  1009. writel(vs_eline_evn, priv->io_base
  1010. + _REG(ENCI_DVI_VSO_ELINE_EVN));
  1011. writel(vso_begin_evn, priv->io_base
  1012. + _REG(ENCI_DVI_VSO_END_EVN));
  1013. }
  1014. }
  1015. } else {
  1016. writel(vmode->encp.dvi_settings,
  1017. priv->io_base + _REG(VENC_DVI_SETTING));
  1018. writel(vmode->encp.video_mode,
  1019. priv->io_base + _REG(ENCP_VIDEO_MODE));
  1020. writel(vmode->encp.video_mode_adv,
  1021. priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
  1022. if (vmode->encp.video_prog_mode_present)
  1023. writel(vmode->encp.video_prog_mode,
  1024. priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
  1025. if (vmode->encp.video_sync_mode_present)
  1026. writel(vmode->encp.video_sync_mode,
  1027. priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
  1028. if (vmode->encp.video_yc_dly_present)
  1029. writel(vmode->encp.video_yc_dly,
  1030. priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
  1031. if (vmode->encp.video_rgb_ctrl_present)
  1032. writel(vmode->encp.video_rgb_ctrl,
  1033. priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
  1034. if (vmode->encp.video_filt_ctrl_present)
  1035. writel(vmode->encp.video_filt_ctrl,
  1036. priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
  1037. if (vmode->encp.video_ofld_voav_ofst_present)
  1038. writel(vmode->encp.video_ofld_voav_ofst,
  1039. priv->io_base
  1040. + _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
  1041. writel(vmode->encp.yfp1_htime,
  1042. priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
  1043. writel(vmode->encp.yfp2_htime,
  1044. priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
  1045. writel(vmode->encp.max_pxcnt,
  1046. priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
  1047. writel(vmode->encp.hspuls_begin,
  1048. priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
  1049. writel(vmode->encp.hspuls_end,
  1050. priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
  1051. writel(vmode->encp.hspuls_switch,
  1052. priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
  1053. writel(vmode->encp.vspuls_begin,
  1054. priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
  1055. writel(vmode->encp.vspuls_end,
  1056. priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
  1057. writel(vmode->encp.vspuls_bline,
  1058. priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
  1059. writel(vmode->encp.vspuls_eline,
  1060. priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
  1061. if (vmode->encp.eqpuls_begin_present)
  1062. writel(vmode->encp.eqpuls_begin,
  1063. priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
  1064. if (vmode->encp.eqpuls_end_present)
  1065. writel(vmode->encp.eqpuls_end,
  1066. priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
  1067. if (vmode->encp.eqpuls_bline_present)
  1068. writel(vmode->encp.eqpuls_bline,
  1069. priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
  1070. if (vmode->encp.eqpuls_eline_present)
  1071. writel(vmode->encp.eqpuls_eline,
  1072. priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
  1073. writel(vmode->encp.havon_begin,
  1074. priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
  1075. writel(vmode->encp.havon_end,
  1076. priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
  1077. writel(vmode->encp.vavon_bline,
  1078. priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
  1079. writel(vmode->encp.vavon_eline,
  1080. priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
  1081. writel(vmode->encp.hso_begin,
  1082. priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
  1083. writel(vmode->encp.hso_end,
  1084. priv->io_base + _REG(ENCP_VIDEO_HSO_END));
  1085. writel(vmode->encp.vso_begin,
  1086. priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
  1087. writel(vmode->encp.vso_end,
  1088. priv->io_base + _REG(ENCP_VIDEO_VSO_END));
  1089. writel(vmode->encp.vso_bline,
  1090. priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
  1091. if (vmode->encp.vso_eline_present)
  1092. writel(vmode->encp.vso_eline,
  1093. priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
  1094. if (vmode->encp.sy_val_present)
  1095. writel(vmode->encp.sy_val,
  1096. priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
  1097. if (vmode->encp.sy2_val_present)
  1098. writel(vmode->encp.sy2_val,
  1099. priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
  1100. writel(vmode->encp.max_lncnt,
  1101. priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
  1102. writel(1, priv->io_base + _REG(ENCP_VIDEO_EN));
  1103. /* Set DE signal's polarity is active high */
  1104. writel_bits(ENCP_VIDEO_MODE_DE_V_HIGH,
  1105. ENCP_VIDEO_MODE_DE_V_HIGH,
  1106. priv->io_base + _REG(ENCP_VIDEO_MODE));
  1107. /* Program DE timing */
  1108. de_h_begin = modulo(readl(priv->io_base +
  1109. _REG(ENCP_VIDEO_HAVON_BEGIN))
  1110. + venc_hdmi_latency,
  1111. total_pixels_venc);
  1112. de_h_end = modulo(de_h_begin + active_pixels_venc,
  1113. total_pixels_venc);
  1114. writel(de_h_begin,
  1115. priv->io_base + _REG(ENCP_DE_H_BEGIN));
  1116. writel(de_h_end,
  1117. priv->io_base + _REG(ENCP_DE_H_END));
  1118. /* Program DE timing for even field */
  1119. de_v_begin_even = readl(priv->io_base
  1120. + _REG(ENCP_VIDEO_VAVON_BLINE));
  1121. if (mode->flags & DISPLAY_FLAGS_INTERLACED)
  1122. de_v_end_even = de_v_begin_even +
  1123. (mode->vactive.typ / 2);
  1124. else
  1125. de_v_end_even = de_v_begin_even + mode->vactive.typ;
  1126. writel(de_v_begin_even,
  1127. priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
  1128. writel(de_v_end_even,
  1129. priv->io_base + _REG(ENCP_DE_V_END_EVEN));
  1130. /* Program DE timing for odd field if needed */
  1131. if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
  1132. unsigned int ofld_voav_ofst =
  1133. readl(priv->io_base +
  1134. _REG(ENCP_VIDEO_OFLD_VOAV_OFST));
  1135. de_v_begin_odd = to_signed((ofld_voav_ofst & 0xf0) >> 4)
  1136. + de_v_begin_even
  1137. + ((mode->vfront_porch.typ +
  1138. mode->vactive.typ +
  1139. mode->vsync_len.typ - 1) / 2);
  1140. de_v_end_odd = de_v_begin_odd + (mode->vactive.typ / 2);
  1141. writel(de_v_begin_odd,
  1142. priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
  1143. writel(de_v_end_odd,
  1144. priv->io_base + _REG(ENCP_DE_V_END_ODD));
  1145. }
  1146. /* Program Hsync timing */
  1147. if ((de_h_end + front_porch_venc) >= total_pixels_venc) {
  1148. hs_begin = de_h_end
  1149. + front_porch_venc
  1150. - total_pixels_venc;
  1151. vs_adjust = 1;
  1152. } else {
  1153. hs_begin = de_h_end
  1154. + front_porch_venc;
  1155. vs_adjust = 0;
  1156. }
  1157. hs_end = modulo(hs_begin + hsync_pixels_venc,
  1158. total_pixels_venc);
  1159. writel(hs_begin,
  1160. priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
  1161. writel(hs_end,
  1162. priv->io_base + _REG(ENCP_DVI_HSO_END));
  1163. /* Program Vsync timing for even field */
  1164. if (de_v_begin_even >=
  1165. (sof_lines + vsync_lines + (1 - vs_adjust)))
  1166. vs_bline_evn = de_v_begin_even
  1167. - sof_lines
  1168. - vsync_lines
  1169. - (1 - vs_adjust);
  1170. else
  1171. vs_bline_evn = (mode->vfront_porch.typ +
  1172. mode->vactive.typ +
  1173. mode->vsync_len.typ) +
  1174. + de_v_begin_even
  1175. - sof_lines
  1176. - vsync_lines
  1177. - (1 - vs_adjust);
  1178. vs_eline_evn = modulo(vs_bline_evn + vsync_lines,
  1179. mode->hfront_porch.typ +
  1180. mode->hactive.typ +
  1181. mode->hsync_len.typ);
  1182. writel(vs_bline_evn,
  1183. priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
  1184. writel(vs_eline_evn,
  1185. priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
  1186. vso_begin_evn = hs_begin;
  1187. writel(vso_begin_evn,
  1188. priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
  1189. writel(vso_begin_evn,
  1190. priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
  1191. /* Program Vsync timing for odd field if needed */
  1192. if (mode->flags & DISPLAY_FLAGS_INTERLACED) {
  1193. vs_bline_odd = (de_v_begin_odd - 1)
  1194. - sof_lines
  1195. - vsync_lines;
  1196. vs_eline_odd = (de_v_begin_odd - 1)
  1197. - vsync_lines;
  1198. vso_begin_odd = modulo(hs_begin
  1199. + (total_pixels_venc >> 1),
  1200. total_pixels_venc);
  1201. writel(vs_bline_odd,
  1202. priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
  1203. writel(vs_eline_odd,
  1204. priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
  1205. writel(vso_begin_odd,
  1206. priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
  1207. writel(vso_begin_odd,
  1208. priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
  1209. }
  1210. /* Select ENCP for VIU */
  1211. meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCP);
  1212. }
  1213. /* Set VPU HDMI setting */
  1214. /* Select ENCP or ENCI data to HDMI */
  1215. if (use_enci)
  1216. reg = VPU_HDMI_ENCI_DATA_TO_HDMI;
  1217. else
  1218. reg = VPU_HDMI_ENCP_DATA_TO_HDMI;
  1219. /* Invert polarity of HSYNC from VENC */
  1220. if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
  1221. reg |= VPU_HDMI_INV_HSYNC;
  1222. /* Invert polarity of VSYNC from VENC */
  1223. if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
  1224. reg |= VPU_HDMI_INV_VSYNC;
  1225. /* Output data format: CbYCr */
  1226. reg |= VPU_HDMI_OUTPUT_CBYCR;
  1227. /*
  1228. * Write rate to the async FIFO between VENC and HDMI.
  1229. * One write every 2 wr_clk.
  1230. */
  1231. if (venc_repeat)
  1232. reg |= VPU_HDMI_WR_RATE(2);
  1233. /*
  1234. * Read rate to the async FIFO between VENC and HDMI.
  1235. * One read every 2 wr_clk.
  1236. */
  1237. if (hdmi_repeat)
  1238. reg |= VPU_HDMI_RD_RATE(2);
  1239. writel(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
  1240. }
  1241. static void meson_venci_cvbs_mode_set(struct meson_vpu_priv *priv,
  1242. struct meson_cvbs_enci_mode *mode)
  1243. {
  1244. u32 reg;
  1245. /* CVBS Filter settings */
  1246. writel(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
  1247. priv->io_base + _REG(ENCI_CFILT_CTRL));
  1248. writel(ENCI_CFILT_CMPT_CR_DLY(2) |
  1249. ENCI_CFILT_CMPT_CB_DLY(1),
  1250. priv->io_base + _REG(ENCI_CFILT_CTRL2));
  1251. /* Digital Video Select : Interlace, clk27 clk, external */
  1252. writel(0, priv->io_base + _REG(VENC_DVI_SETTING));
  1253. /* Reset Video Mode */
  1254. writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
  1255. writel(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
  1256. /* Horizontal sync signal output */
  1257. writel(mode->hso_begin,
  1258. priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
  1259. writel(mode->hso_end,
  1260. priv->io_base + _REG(ENCI_SYNC_HSO_END));
  1261. /* Vertical Sync lines */
  1262. writel(mode->vso_even,
  1263. priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
  1264. writel(mode->vso_odd,
  1265. priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
  1266. /* Macrovision max amplitude change */
  1267. writel(ENCI_MACV_MAX_AMP_ENABLE_CHANGE |
  1268. ENCI_MACV_MAX_AMP_VAL(mode->macv_max_amp),
  1269. priv->io_base + _REG(ENCI_MACV_MAX_AMP));
  1270. /* Video mode */
  1271. writel(mode->video_prog_mode,
  1272. priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
  1273. writel(mode->video_mode,
  1274. priv->io_base + _REG(ENCI_VIDEO_MODE));
  1275. /*
  1276. * Advanced Video Mode :
  1277. * Demux shifting 0x2
  1278. * Blank line end at line17/22
  1279. * High bandwidth Luma Filter
  1280. * Low bandwidth Chroma Filter
  1281. * Bypass luma low pass filter
  1282. * No macrovision on CSYNC
  1283. */
  1284. writel(ENCI_VIDEO_MODE_ADV_DMXMD(2) |
  1285. ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 |
  1286. ENCI_VIDEO_MODE_ADV_YBW_HIGH,
  1287. priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
  1288. writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
  1289. /* Sync mode : MASTER Master mode, free run, send HSO/VSO out */
  1290. writel(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
  1291. /* 0x3 Y, C, and Component Y delay */
  1292. writel(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
  1293. /* Timings */
  1294. writel(mode->pixel_start,
  1295. priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
  1296. writel(mode->pixel_end,
  1297. priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
  1298. writel(mode->top_field_line_start,
  1299. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
  1300. writel(mode->top_field_line_end,
  1301. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
  1302. writel(mode->bottom_field_line_start,
  1303. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
  1304. writel(mode->bottom_field_line_end,
  1305. priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
  1306. /* Internal Venc, Internal VIU Sync, Internal Vencoder */
  1307. writel(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
  1308. /* UNreset Interlaced TV Encoder */
  1309. writel(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
  1310. /*
  1311. * Enable Vfifo2vd and set Y_Cb_Y_Cr:
  1312. * Corresponding value:
  1313. * Y => 00 or 10
  1314. * Cb => 01
  1315. * Cr => 11
  1316. * Ex: 0x4e => 01001110 would mean Cb/Y/Cr/Y
  1317. */
  1318. writel(ENCI_VFIFO2VD_CTL_ENABLE |
  1319. ENCI_VFIFO2VD_CTL_VD_SEL(0x4e),
  1320. priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
  1321. /* Power UP Dacs */
  1322. writel(0, priv->io_base + _REG(VENC_VDAC_SETTING));
  1323. /* Video Upsampling */
  1324. /*
  1325. * CTRL0, CTRL1 and CTRL2:
  1326. * Filter0: input data sample every 2 cloks
  1327. * Filter1: filtering and upsample enable
  1328. */
  1329. reg = VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO | VENC_UPSAMPLE_CTRL_F1_EN |
  1330. VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN;
  1331. /*
  1332. * Upsample CTRL0:
  1333. * Interlace High Bandwidth Luma
  1334. */
  1335. writel(VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA | reg,
  1336. priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
  1337. /*
  1338. * Upsample CTRL1:
  1339. * Interlace Pb
  1340. */
  1341. writel(VENC_UPSAMPLE_CTRL_INTERLACE_PB | reg,
  1342. priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
  1343. /*
  1344. * Upsample CTRL2:
  1345. * Interlace R
  1346. */
  1347. writel(VENC_UPSAMPLE_CTRL_INTERLACE_PR | reg,
  1348. priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
  1349. /* Select Interlace Y DACs */
  1350. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
  1351. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
  1352. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
  1353. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
  1354. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
  1355. writel(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
  1356. /* Select ENCI for VIU */
  1357. meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCI);
  1358. /* Enable ENCI FIFO */
  1359. writel(VENC_VDAC_FIFO_EN_ENCI_ENABLE,
  1360. priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
  1361. /* Select ENCI DACs 0, 1, 4, and 5 */
  1362. writel(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
  1363. writel(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
  1364. /* Interlace video enable */
  1365. writel(ENCI_VIDEO_EN_ENABLE,
  1366. priv->io_base + _REG(ENCI_VIDEO_EN));
  1367. /* Configure Video Saturation / Contrast / Brightness / Hue */
  1368. writel(mode->video_saturation,
  1369. priv->io_base + _REG(ENCI_VIDEO_SAT));
  1370. writel(mode->video_contrast,
  1371. priv->io_base + _REG(ENCI_VIDEO_CONT));
  1372. writel(mode->video_brightness,
  1373. priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
  1374. writel(mode->video_hue,
  1375. priv->io_base + _REG(ENCI_VIDEO_HUE));
  1376. /* Enable DAC0 Filter */
  1377. writel(VENC_VDAC_DAC0_FILT_CTRL0_EN,
  1378. priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
  1379. writel(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
  1380. /* 0 in Macrovision register 0 */
  1381. writel(0, priv->io_base + _REG(ENCI_MACV_N0));
  1382. /* Analog Synchronization and color burst value adjust */
  1383. writel(mode->analog_sync_adj,
  1384. priv->io_base + _REG(ENCI_SYNC_ADJ));
  1385. /* enable VDAC */
  1386. writel_bits(VENC_VDAC_SEL_ATV_DMD, 0,
  1387. priv->io_base + _REG(VENC_VDAC_DACSEL0));
  1388. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
  1389. hhi_write(HHI_VDAC_CNTL0, 1);
  1390. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
  1391. meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM))
  1392. hhi_write(HHI_VDAC_CNTL0, 0xf0001);
  1393. else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  1394. hhi_write(HHI_VDAC_CNTL0_G12A, 0x906001);
  1395. if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
  1396. hhi_write(HHI_VDAC_CNTL1_G12A, 0);
  1397. else
  1398. hhi_write(HHI_VDAC_CNTL1, 0);
  1399. }
  1400. void meson_vpu_setup_venc(struct udevice *dev,
  1401. const struct display_timing *mode, bool is_cvbs)
  1402. {
  1403. struct meson_vpu_priv *priv = dev_get_priv(dev);
  1404. if (is_cvbs)
  1405. return meson_venci_cvbs_mode_set(priv, &meson_cvbs_enci_pal);
  1406. meson_venc_hdmi_mode_set(priv, mode);
  1407. }