jr.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. *
  5. * Based on CAAM driver in drivers/crypto/caam in Linux
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <linux/kernel.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include "fsl_sec.h"
  13. #include "jr.h"
  14. #include "jobdesc.h"
  15. #include "desc_constr.h"
  16. #include <time.h>
  17. #include <asm/cache.h>
  18. #ifdef CONFIG_FSL_CORENET
  19. #include <asm/cache.h>
  20. #include <asm/fsl_pamu.h>
  21. #endif
  22. #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
  23. #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
  24. uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
  25. 0,
  26. #if defined(CONFIG_ARCH_C29X)
  27. CONFIG_SYS_FSL_SEC_IDX_OFFSET,
  28. 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
  29. #endif
  30. };
  31. #define SEC_ADDR(idx) \
  32. ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
  33. #define SEC_JR0_ADDR(idx) \
  34. (SEC_ADDR(idx) + \
  35. (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
  36. struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
  37. static inline void start_jr0(uint8_t sec_idx)
  38. {
  39. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  40. u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
  41. u32 scfgr = sec_in32(&sec->scfgr);
  42. if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
  43. /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
  44. * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
  45. */
  46. if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
  47. (scfgr & SEC_SCFGR_VIRT_EN))
  48. sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  49. } else {
  50. /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
  51. if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
  52. sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
  53. }
  54. }
  55. static inline void jr_reset_liodn(uint8_t sec_idx)
  56. {
  57. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  58. sec_out32(&sec->jrliodnr[0].ls, 0);
  59. }
  60. static inline void jr_disable_irq(uint8_t sec_idx)
  61. {
  62. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  63. uint32_t jrcfg = sec_in32(&regs->jrcfg1);
  64. jrcfg = jrcfg | JR_INTMASK;
  65. sec_out32(&regs->jrcfg1, jrcfg);
  66. }
  67. static void jr_initregs(uint8_t sec_idx)
  68. {
  69. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  70. struct jobring *jr = &jr0[sec_idx];
  71. phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
  72. phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
  73. #ifdef CONFIG_PHYS_64BIT
  74. sec_out32(&regs->irba_h, ip_base >> 32);
  75. #else
  76. sec_out32(&regs->irba_h, 0x0);
  77. #endif
  78. sec_out32(&regs->irba_l, (uint32_t)ip_base);
  79. #ifdef CONFIG_PHYS_64BIT
  80. sec_out32(&regs->orba_h, op_base >> 32);
  81. #else
  82. sec_out32(&regs->orba_h, 0x0);
  83. #endif
  84. sec_out32(&regs->orba_l, (uint32_t)op_base);
  85. sec_out32(&regs->ors, JR_SIZE);
  86. sec_out32(&regs->irs, JR_SIZE);
  87. if (!jr->irq)
  88. jr_disable_irq(sec_idx);
  89. }
  90. static int jr_init(uint8_t sec_idx)
  91. {
  92. struct jobring *jr = &jr0[sec_idx];
  93. memset(jr, 0, sizeof(struct jobring));
  94. jr->jq_id = DEFAULT_JR_ID;
  95. jr->irq = DEFAULT_IRQ;
  96. #ifdef CONFIG_FSL_CORENET
  97. jr->liodn = DEFAULT_JR_LIODN;
  98. #endif
  99. jr->size = JR_SIZE;
  100. jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
  101. JR_SIZE * sizeof(dma_addr_t));
  102. if (!jr->input_ring)
  103. return -1;
  104. jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
  105. ARCH_DMA_MINALIGN);
  106. jr->output_ring =
  107. (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
  108. if (!jr->output_ring)
  109. return -1;
  110. memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
  111. memset(jr->output_ring, 0, jr->op_size);
  112. start_jr0(sec_idx);
  113. jr_initregs(sec_idx);
  114. return 0;
  115. }
  116. static int jr_sw_cleanup(uint8_t sec_idx)
  117. {
  118. struct jobring *jr = &jr0[sec_idx];
  119. jr->head = 0;
  120. jr->tail = 0;
  121. jr->read_idx = 0;
  122. jr->write_idx = 0;
  123. memset(jr->info, 0, sizeof(jr->info));
  124. memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
  125. memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
  126. return 0;
  127. }
  128. static int jr_hw_reset(uint8_t sec_idx)
  129. {
  130. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  131. uint32_t timeout = 100000;
  132. uint32_t jrint, jrcr;
  133. sec_out32(&regs->jrcr, JRCR_RESET);
  134. do {
  135. jrint = sec_in32(&regs->jrint);
  136. } while (((jrint & JRINT_ERR_HALT_MASK) ==
  137. JRINT_ERR_HALT_INPROGRESS) && --timeout);
  138. jrint = sec_in32(&regs->jrint);
  139. if (((jrint & JRINT_ERR_HALT_MASK) !=
  140. JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
  141. return -1;
  142. timeout = 100000;
  143. sec_out32(&regs->jrcr, JRCR_RESET);
  144. do {
  145. jrcr = sec_in32(&regs->jrcr);
  146. } while ((jrcr & JRCR_RESET) && --timeout);
  147. if (timeout == 0)
  148. return -1;
  149. return 0;
  150. }
  151. /* -1 --- error, can't enqueue -- no space available */
  152. static int jr_enqueue(uint32_t *desc_addr,
  153. void (*callback)(uint32_t status, void *arg),
  154. void *arg, uint8_t sec_idx)
  155. {
  156. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  157. struct jobring *jr = &jr0[sec_idx];
  158. int head = jr->head;
  159. uint32_t desc_word;
  160. int length = desc_len(desc_addr);
  161. int i;
  162. #ifdef CONFIG_PHYS_64BIT
  163. uint32_t *addr_hi, *addr_lo;
  164. #endif
  165. /* The descriptor must be submitted to SEC block as per endianness
  166. * of the SEC Block.
  167. * So, if the endianness of Core and SEC block is different, each word
  168. * of the descriptor will be byte-swapped.
  169. */
  170. for (i = 0; i < length; i++) {
  171. desc_word = desc_addr[i];
  172. sec_out32((uint32_t *)&desc_addr[i], desc_word);
  173. }
  174. phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
  175. jr->info[head].desc_phys_addr = desc_phys_addr;
  176. jr->info[head].callback = (void *)callback;
  177. jr->info[head].arg = arg;
  178. jr->info[head].op_done = 0;
  179. unsigned long start = (unsigned long)&jr->info[head] &
  180. ~(ARCH_DMA_MINALIGN - 1);
  181. unsigned long end = ALIGN((unsigned long)&jr->info[head] +
  182. sizeof(struct jr_info), ARCH_DMA_MINALIGN);
  183. flush_dcache_range(start, end);
  184. #ifdef CONFIG_PHYS_64BIT
  185. /* Write the 64 bit Descriptor address on Input Ring.
  186. * The 32 bit hign and low part of the address will
  187. * depend on endianness of SEC block.
  188. */
  189. #ifdef CONFIG_SYS_FSL_SEC_LE
  190. addr_lo = (uint32_t *)(&jr->input_ring[head]);
  191. addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
  192. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  193. addr_hi = (uint32_t *)(&jr->input_ring[head]);
  194. addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
  195. #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
  196. sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
  197. sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
  198. #else
  199. /* Write the 32 bit Descriptor address on Input Ring. */
  200. sec_out32(&jr->input_ring[head], desc_phys_addr);
  201. #endif /* ifdef CONFIG_PHYS_64BIT */
  202. start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
  203. end = ALIGN((unsigned long)&jr->input_ring[head] +
  204. sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
  205. flush_dcache_range(start, end);
  206. jr->head = (head + 1) & (jr->size - 1);
  207. /* Invalidate output ring */
  208. start = (unsigned long)jr->output_ring &
  209. ~(ARCH_DMA_MINALIGN - 1);
  210. end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
  211. ARCH_DMA_MINALIGN);
  212. invalidate_dcache_range(start, end);
  213. sec_out32(&regs->irja, 1);
  214. return 0;
  215. }
  216. static int jr_dequeue(int sec_idx)
  217. {
  218. struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
  219. struct jobring *jr = &jr0[sec_idx];
  220. int head = jr->head;
  221. int tail = jr->tail;
  222. int idx, i, found;
  223. void (*callback)(uint32_t status, void *arg);
  224. void *arg = NULL;
  225. #ifdef CONFIG_PHYS_64BIT
  226. uint32_t *addr_hi, *addr_lo;
  227. #else
  228. uint32_t *addr;
  229. #endif
  230. while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
  231. jr->size)) {
  232. found = 0;
  233. phys_addr_t op_desc;
  234. #ifdef CONFIG_PHYS_64BIT
  235. /* Read the 64 bit Descriptor address from Output Ring.
  236. * The 32 bit hign and low part of the address will
  237. * depend on endianness of SEC block.
  238. */
  239. #ifdef CONFIG_SYS_FSL_SEC_LE
  240. addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
  241. addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
  242. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  243. addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
  244. addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
  245. #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
  246. op_desc = ((u64)sec_in32(addr_hi) << 32) |
  247. ((u64)sec_in32(addr_lo));
  248. #else
  249. /* Read the 32 bit Descriptor address from Output Ring. */
  250. addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
  251. op_desc = sec_in32(addr);
  252. #endif /* ifdef CONFIG_PHYS_64BIT */
  253. uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
  254. for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
  255. idx = (tail + i) & (jr->size - 1);
  256. if (op_desc == jr->info[idx].desc_phys_addr) {
  257. found = 1;
  258. break;
  259. }
  260. }
  261. /* Error condition if match not found */
  262. if (!found)
  263. return -1;
  264. jr->info[idx].op_done = 1;
  265. callback = (void *)jr->info[idx].callback;
  266. arg = jr->info[idx].arg;
  267. /* When the job on tail idx gets done, increment
  268. * tail till the point where job completed out of oredr has
  269. * been taken into account
  270. */
  271. if (idx == tail)
  272. do {
  273. tail = (tail + 1) & (jr->size - 1);
  274. } while (jr->info[tail].op_done);
  275. jr->tail = tail;
  276. jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
  277. sec_out32(&regs->orjr, 1);
  278. jr->info[idx].op_done = 0;
  279. callback(status, arg);
  280. }
  281. return 0;
  282. }
  283. static void desc_done(uint32_t status, void *arg)
  284. {
  285. struct result *x = arg;
  286. x->status = status;
  287. #ifndef CONFIG_SPL_BUILD
  288. caam_jr_strstatus(status);
  289. #endif
  290. x->done = 1;
  291. }
  292. static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
  293. {
  294. unsigned long long timeval = get_ticks();
  295. unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
  296. struct result op;
  297. int ret = 0;
  298. memset(&op, 0, sizeof(op));
  299. ret = jr_enqueue(desc, desc_done, &op, sec_idx);
  300. if (ret) {
  301. debug("Error in SEC enq\n");
  302. ret = JQ_ENQ_ERR;
  303. goto out;
  304. }
  305. timeval = get_ticks();
  306. timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
  307. while (op.done != 1) {
  308. ret = jr_dequeue(sec_idx);
  309. if (ret) {
  310. debug("Error in SEC deq\n");
  311. ret = JQ_DEQ_ERR;
  312. goto out;
  313. }
  314. if ((get_ticks() - timeval) > timeout) {
  315. debug("SEC Dequeue timed out\n");
  316. ret = JQ_DEQ_TO_ERR;
  317. goto out;
  318. }
  319. }
  320. if (op.status) {
  321. debug("Error %x\n", op.status);
  322. ret = op.status;
  323. }
  324. out:
  325. return ret;
  326. }
  327. int run_descriptor_jr(uint32_t *desc)
  328. {
  329. return run_descriptor_jr_idx(desc, 0);
  330. }
  331. static inline int jr_reset_sec(uint8_t sec_idx)
  332. {
  333. if (jr_hw_reset(sec_idx) < 0)
  334. return -1;
  335. /* Clean up the jobring structure maintained by software */
  336. jr_sw_cleanup(sec_idx);
  337. return 0;
  338. }
  339. int jr_reset(void)
  340. {
  341. return jr_reset_sec(0);
  342. }
  343. static inline int sec_reset_idx(uint8_t sec_idx)
  344. {
  345. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  346. uint32_t mcfgr = sec_in32(&sec->mcfgr);
  347. uint32_t timeout = 100000;
  348. mcfgr |= MCFGR_SWRST;
  349. sec_out32(&sec->mcfgr, mcfgr);
  350. mcfgr |= MCFGR_DMA_RST;
  351. sec_out32(&sec->mcfgr, mcfgr);
  352. do {
  353. mcfgr = sec_in32(&sec->mcfgr);
  354. } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
  355. if (timeout == 0)
  356. return -1;
  357. timeout = 100000;
  358. do {
  359. mcfgr = sec_in32(&sec->mcfgr);
  360. } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
  361. if (timeout == 0)
  362. return -1;
  363. return 0;
  364. }
  365. int sec_reset(void)
  366. {
  367. return sec_reset_idx(0);
  368. }
  369. #ifndef CONFIG_SPL_BUILD
  370. static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
  371. {
  372. u32 *desc;
  373. int sh_idx, ret = 0;
  374. int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN);
  375. desc = memalign(ARCH_DMA_MINALIGN, desc_size);
  376. if (!desc) {
  377. debug("cannot allocate RNG init descriptor memory\n");
  378. return -ENOMEM;
  379. }
  380. for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
  381. /*
  382. * If the corresponding bit is set, then it means the state
  383. * handle was initialized by us, and thus it needs to be
  384. * deinitialized as well
  385. */
  386. if (state_handle_mask & RDSTA_IF(sh_idx)) {
  387. /*
  388. * Create the descriptor for deinstantating this state
  389. * handle.
  390. */
  391. inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx);
  392. flush_dcache_range((unsigned long)desc,
  393. (unsigned long)desc + desc_size);
  394. ret = run_descriptor_jr_idx(desc, sec_idx);
  395. if (ret) {
  396. printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n",
  397. sec_idx, sh_idx, ret);
  398. ret = -EIO;
  399. break;
  400. }
  401. printf("SEC%u: Deinstantiated RNG4 SH%d\n",
  402. sec_idx, sh_idx);
  403. }
  404. }
  405. free(desc);
  406. return ret;
  407. }
  408. static int instantiate_rng(u8 sec_idx, int gen_sk)
  409. {
  410. u32 *desc;
  411. u32 rdsta_val;
  412. int ret = 0, sh_idx, size;
  413. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  414. struct rng4tst __iomem *rng =
  415. (struct rng4tst __iomem *)&sec->rng;
  416. desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * 6);
  417. if (!desc) {
  418. printf("cannot allocate RNG init descriptor memory\n");
  419. return -1;
  420. }
  421. for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
  422. /*
  423. * If the corresponding bit is set, this state handle
  424. * was initialized by somebody else, so it's left alone.
  425. */
  426. rdsta_val = sec_in32(&rng->rdsta);
  427. if (rdsta_val & (RDSTA_IF(sh_idx))) {
  428. if (rdsta_val & RDSTA_PR(sh_idx))
  429. continue;
  430. printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n",
  431. sec_idx, sh_idx);
  432. ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx));
  433. if (ret)
  434. break;
  435. }
  436. inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk);
  437. size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN);
  438. flush_dcache_range((unsigned long)desc,
  439. (unsigned long)desc + size);
  440. ret = run_descriptor_jr_idx(desc, sec_idx);
  441. if (ret)
  442. printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n",
  443. sec_idx, sh_idx, ret);
  444. rdsta_val = sec_in32(&rng->rdsta);
  445. if (!(rdsta_val & RDSTA_IF(sh_idx))) {
  446. free(desc);
  447. return -1;
  448. }
  449. memset(desc, 0, sizeof(uint32_t) * 6);
  450. }
  451. free(desc);
  452. return ret;
  453. }
  454. static u8 get_rng_vid(uint8_t sec_idx)
  455. {
  456. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  457. u8 vid;
  458. if (caam_get_era() < 10) {
  459. vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK)
  460. >> SEC_CHAVID_LS_RNG_SHIFT;
  461. } else {
  462. vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK)
  463. >> CHA_VER_VID_SHIFT;
  464. }
  465. return vid;
  466. }
  467. /*
  468. * By default, the TRNG runs for 200 clocks per sample;
  469. * 1200 clocks per sample generates better entropy.
  470. */
  471. static void kick_trng(int ent_delay, uint8_t sec_idx)
  472. {
  473. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  474. struct rng4tst __iomem *rng =
  475. (struct rng4tst __iomem *)&sec->rng;
  476. u32 val;
  477. /* put RNG4 into program mode */
  478. sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
  479. /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
  480. * length (in system clocks) of each Entropy sample taken
  481. * */
  482. val = sec_in32(&rng->rtsdctl);
  483. val = (val & ~RTSDCTL_ENT_DLY_MASK) |
  484. (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
  485. sec_out32(&rng->rtsdctl, val);
  486. /* min. freq. count, equal to 1/4 of the entropy sample length */
  487. sec_out32(&rng->rtfreqmin, ent_delay >> 2);
  488. /* disable maximum frequency count */
  489. sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
  490. /*
  491. * select raw sampling in both entropy shifter
  492. * and statistical checker
  493. */
  494. sec_setbits32(&rng->rtmctl, RTMCTL_SAMP_MODE_RAW_ES_SC);
  495. /* put RNG4 into run mode */
  496. sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
  497. }
  498. static int rng_init(uint8_t sec_idx)
  499. {
  500. int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
  501. ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
  502. struct rng4tst __iomem *rng =
  503. (struct rng4tst __iomem *)&sec->rng;
  504. u32 inst_handles;
  505. gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN);
  506. do {
  507. inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK;
  508. /*
  509. * If either of the SH's were instantiated by somebody else
  510. * then it is assumed that the entropy
  511. * parameters are properly set and thus the function
  512. * setting these (kick_trng(...)) is skipped.
  513. * Also, if a handle was instantiated, do not change
  514. * the TRNG parameters.
  515. */
  516. if (!inst_handles) {
  517. kick_trng(ent_delay, sec_idx);
  518. ent_delay += 400;
  519. }
  520. /*
  521. * if instantiate_rng(...) fails, the loop will rerun
  522. * and the kick_trng(...) function will modfiy the
  523. * upper and lower limits of the entropy sampling
  524. * interval, leading to a sucessful initialization of
  525. * the RNG.
  526. */
  527. ret = instantiate_rng(sec_idx, gen_sk);
  528. } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
  529. if (ret) {
  530. printf("SEC%u: Failed to instantiate RNG\n", sec_idx);
  531. return ret;
  532. }
  533. /* Enable RDB bit so that RNG works faster */
  534. sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
  535. return ret;
  536. }
  537. #endif
  538. int sec_init_idx(uint8_t sec_idx)
  539. {
  540. ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
  541. uint32_t mcr = sec_in32(&sec->mcfgr);
  542. int ret = 0;
  543. #ifdef CONFIG_FSL_CORENET
  544. uint32_t liodnr;
  545. uint32_t liodn_ns;
  546. uint32_t liodn_s;
  547. #endif
  548. if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
  549. printf("SEC%u: initialization failed\n", sec_idx);
  550. return -1;
  551. }
  552. /*
  553. * Modifying CAAM Read/Write Attributes
  554. * For LS2080A
  555. * For AXI Write - Cacheable, Write Back, Write allocate
  556. * For AXI Read - Cacheable, Read allocate
  557. * Only For LS2080a, to solve CAAM coherency issues
  558. */
  559. #ifdef CONFIG_ARCH_LS2080A
  560. mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
  561. mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
  562. #else
  563. mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
  564. #endif
  565. #ifdef CONFIG_PHYS_64BIT
  566. mcr |= (1 << MCFGR_PS_SHIFT);
  567. #endif
  568. sec_out32(&sec->mcfgr, mcr);
  569. #ifdef CONFIG_FSL_CORENET
  570. #ifdef CONFIG_SPL_BUILD
  571. /*
  572. * For SPL Build, Set the Liodns in SEC JR0 for
  573. * creating PAMU entries corresponding to these.
  574. * For normal build, these are set in set_liodns().
  575. */
  576. liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
  577. liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
  578. liodnr = sec_in32(&sec->jrliodnr[0].ls) &
  579. ~(JRNSLIODN_MASK | JRSLIODN_MASK);
  580. liodnr = liodnr |
  581. (liodn_ns << JRNSLIODN_SHIFT) |
  582. (liodn_s << JRSLIODN_SHIFT);
  583. sec_out32(&sec->jrliodnr[0].ls, liodnr);
  584. #else
  585. liodnr = sec_in32(&sec->jrliodnr[0].ls);
  586. liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
  587. liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
  588. #endif
  589. #endif
  590. ret = jr_init(sec_idx);
  591. if (ret < 0) {
  592. printf("SEC%u: initialization failed\n", sec_idx);
  593. return -1;
  594. }
  595. #ifdef CONFIG_FSL_CORENET
  596. ret = sec_config_pamu_table(liodn_ns, liodn_s);
  597. if (ret < 0)
  598. return -1;
  599. pamu_enable();
  600. #endif
  601. #ifndef CONFIG_SPL_BUILD
  602. if (get_rng_vid(sec_idx) >= 4) {
  603. if (rng_init(sec_idx) < 0) {
  604. printf("SEC%u: RNG instantiation failed\n", sec_idx);
  605. return -1;
  606. }
  607. printf("SEC%u: RNG instantiated\n", sec_idx);
  608. }
  609. #endif
  610. return ret;
  611. }
  612. int sec_init(void)
  613. {
  614. return sec_init_idx(0);
  615. }