cpu.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008-2011
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. *
  9. * (C) Copyright 2002
  10. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11. * Marius Groeger <mgroeger@sysgo.de>
  12. *
  13. * (C) Copyright 2002
  14. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  15. * Alex Zuepke <azu@sysgo.de>
  16. *
  17. * Part of this file is adapted from coreboot
  18. * src/arch/x86/lib/cpu.c
  19. */
  20. #include <common.h>
  21. #include <bootstage.h>
  22. #include <command.h>
  23. #include <cpu_func.h>
  24. #include <dm.h>
  25. #include <errno.h>
  26. #include <init.h>
  27. #include <irq.h>
  28. #include <log.h>
  29. #include <malloc.h>
  30. #include <syscon.h>
  31. #include <acpi/acpi_s3.h>
  32. #include <acpi/acpi_table.h>
  33. #include <asm/acpi.h>
  34. #include <asm/control_regs.h>
  35. #include <asm/coreboot_tables.h>
  36. #include <asm/cpu.h>
  37. #include <asm/lapic.h>
  38. #include <asm/microcode.h>
  39. #include <asm/mp.h>
  40. #include <asm/mrccache.h>
  41. #include <asm/msr.h>
  42. #include <asm/mtrr.h>
  43. #include <asm/post.h>
  44. #include <asm/processor.h>
  45. #include <asm/processor-flags.h>
  46. #include <asm/interrupt.h>
  47. #include <asm/tables.h>
  48. #include <linux/compiler.h>
  49. DECLARE_GLOBAL_DATA_PTR;
  50. #ifndef CONFIG_TPL_BUILD
  51. static const char *const x86_vendor_name[] = {
  52. [X86_VENDOR_INTEL] = "Intel",
  53. [X86_VENDOR_CYRIX] = "Cyrix",
  54. [X86_VENDOR_AMD] = "AMD",
  55. [X86_VENDOR_UMC] = "UMC",
  56. [X86_VENDOR_NEXGEN] = "NexGen",
  57. [X86_VENDOR_CENTAUR] = "Centaur",
  58. [X86_VENDOR_RISE] = "Rise",
  59. [X86_VENDOR_TRANSMETA] = "Transmeta",
  60. [X86_VENDOR_NSC] = "NSC",
  61. [X86_VENDOR_SIS] = "SiS",
  62. };
  63. #endif
  64. int __weak x86_cleanup_before_linux(void)
  65. {
  66. #ifdef CONFIG_BOOTSTAGE_STASH
  67. bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
  68. CONFIG_BOOTSTAGE_STASH_SIZE);
  69. #endif
  70. return 0;
  71. }
  72. int x86_init_cache(void)
  73. {
  74. enable_caches();
  75. return 0;
  76. }
  77. int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
  78. void flush_cache(unsigned long dummy1, unsigned long dummy2)
  79. {
  80. asm("wbinvd\n");
  81. }
  82. /* Define these functions to allow ehch-hcd to function */
  83. void flush_dcache_range(unsigned long start, unsigned long stop)
  84. {
  85. }
  86. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  87. {
  88. }
  89. void dcache_enable(void)
  90. {
  91. enable_caches();
  92. }
  93. void dcache_disable(void)
  94. {
  95. disable_caches();
  96. }
  97. void icache_enable(void)
  98. {
  99. }
  100. void icache_disable(void)
  101. {
  102. }
  103. int icache_status(void)
  104. {
  105. return 1;
  106. }
  107. #ifndef CONFIG_TPL_BUILD
  108. const char *cpu_vendor_name(int vendor)
  109. {
  110. const char *name;
  111. name = "<invalid cpu vendor>";
  112. if (vendor < ARRAY_SIZE(x86_vendor_name) &&
  113. x86_vendor_name[vendor])
  114. name = x86_vendor_name[vendor];
  115. return name;
  116. }
  117. #endif
  118. char *cpu_get_name(char *name)
  119. {
  120. unsigned int *name_as_ints = (unsigned int *)name;
  121. struct cpuid_result regs;
  122. char *ptr;
  123. int i;
  124. /* This bit adds up to 48 bytes */
  125. for (i = 0; i < 3; i++) {
  126. regs = cpuid(0x80000002 + i);
  127. name_as_ints[i * 4 + 0] = regs.eax;
  128. name_as_ints[i * 4 + 1] = regs.ebx;
  129. name_as_ints[i * 4 + 2] = regs.ecx;
  130. name_as_ints[i * 4 + 3] = regs.edx;
  131. }
  132. name[CPU_MAX_NAME_LEN - 1] = '\0';
  133. /* Skip leading spaces. */
  134. ptr = name;
  135. while (*ptr == ' ')
  136. ptr++;
  137. return ptr;
  138. }
  139. int default_print_cpuinfo(void)
  140. {
  141. printf("CPU: %s, vendor %s, device %xh\n",
  142. cpu_has_64bit() ? "x86_64" : "x86",
  143. cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
  144. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  145. debug("ACPI previous sleep state: %s\n",
  146. acpi_ss_string(gd->arch.prev_sleep_state));
  147. }
  148. return 0;
  149. }
  150. void show_boot_progress(int val)
  151. {
  152. outb(val, POST_PORT);
  153. }
  154. #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
  155. /*
  156. * Implement a weak default function for boards that optionally
  157. * need to clean up the system before jumping to the kernel.
  158. */
  159. __weak void board_final_cleanup(void)
  160. {
  161. }
  162. int last_stage_init(void)
  163. {
  164. struct acpi_fadt __maybe_unused *fadt;
  165. board_final_cleanup();
  166. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  167. fadt = acpi_find_fadt();
  168. if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
  169. acpi_resume(fadt);
  170. }
  171. write_tables();
  172. #ifdef CONFIG_GENERATE_ACPI_TABLE
  173. fadt = acpi_find_fadt();
  174. /* Don't touch ACPI hardware on HW reduced platforms */
  175. if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
  176. /*
  177. * Other than waiting for OSPM to request us to switch to ACPI
  178. * mode, do it by ourselves, since SMI will not be triggered.
  179. */
  180. enter_acpi_mode(fadt->pm1a_cnt_blk);
  181. }
  182. #endif
  183. return 0;
  184. }
  185. #endif
  186. static int x86_init_cpus(void)
  187. {
  188. #ifdef CONFIG_SMP
  189. debug("Init additional CPUs\n");
  190. x86_mp_init();
  191. #else
  192. struct udevice *dev;
  193. /*
  194. * This causes the cpu-x86 driver to be probed.
  195. * We don't check return value here as we want to allow boards
  196. * which have not been converted to use cpu uclass driver to boot.
  197. */
  198. uclass_first_device(UCLASS_CPU, &dev);
  199. #endif
  200. return 0;
  201. }
  202. int cpu_init_r(void)
  203. {
  204. struct udevice *dev;
  205. int ret;
  206. if (!ll_boot_init()) {
  207. uclass_first_device(UCLASS_PCI, &dev);
  208. return 0;
  209. }
  210. ret = x86_init_cpus();
  211. if (ret)
  212. return ret;
  213. /*
  214. * Set up the northbridge, PCH and LPC if available. Note that these
  215. * may have had some limited pre-relocation init if they were probed
  216. * before relocation, but this is post relocation.
  217. */
  218. uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
  219. uclass_first_device(UCLASS_PCH, &dev);
  220. uclass_first_device(UCLASS_LPC, &dev);
  221. /* Set up pin control if available */
  222. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  223. debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
  224. return 0;
  225. }
  226. #ifndef CONFIG_EFI_STUB
  227. int reserve_arch(void)
  228. {
  229. struct udevice *itss;
  230. int ret;
  231. if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
  232. mrccache_reserve();
  233. #ifdef CONFIG_SEABIOS
  234. high_table_reserve();
  235. #endif
  236. if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
  237. acpi_s3_reserve();
  238. if (IS_ENABLED(CONFIG_HAVE_FSP)) {
  239. /*
  240. * Save stack address to CMOS so that at next S3 boot,
  241. * we can use it as the stack address for fsp_contiue()
  242. */
  243. fsp_save_s3_stack();
  244. }
  245. }
  246. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  247. if (!ret) {
  248. /*
  249. * Snapshot the current GPIO IRQ polarities. FSP-S is about to
  250. * run and will set a default policy that doesn't honour boards'
  251. * requirements
  252. */
  253. irq_snapshot_polarities(itss);
  254. }
  255. return 0;
  256. }
  257. #endif
  258. long detect_coreboot_table_at(ulong start, ulong size)
  259. {
  260. u32 *ptr, *end;
  261. size /= 4;
  262. for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
  263. if (*ptr == 0x4f49424c) /* "LBIO" */
  264. return (long)ptr;
  265. }
  266. return -ENOENT;
  267. }
  268. long locate_coreboot_table(void)
  269. {
  270. long addr;
  271. /* We look for LBIO in the first 4K of RAM and again at 960KB */
  272. addr = detect_coreboot_table_at(0x0, 0x1000);
  273. if (addr < 0)
  274. addr = detect_coreboot_table_at(0xf0000, 0x1000);
  275. return addr;
  276. }