fsp_s.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <binman.h>
  8. #include <bootstage.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <irq.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <p2sb.h>
  15. #include <acpi/acpi_s3.h>
  16. #include <asm/intel_pinctrl.h>
  17. #include <asm/io.h>
  18. #include <asm/intel_regs.h>
  19. #include <asm/msr.h>
  20. #include <asm/msr-index.h>
  21. #include <asm/pci.h>
  22. #include <asm/arch/cpu.h>
  23. #include <asm/arch/systemagent.h>
  24. #include <asm/arch/fsp_bindings.h>
  25. #include <asm/arch/fsp/fsp_configs.h>
  26. #include <asm/arch/fsp/fsp_s_upd.h>
  27. #include <dm/uclass-internal.h>
  28. #include <linux/bitops.h>
  29. #define PCH_P2SB_E0 0xe0
  30. #define HIDE_BIT BIT(0)
  31. int fsps_update_config(struct udevice *dev, ulong rom_offset,
  32. struct fsps_upd *upd)
  33. {
  34. struct fsp_s_config *cfg = &upd->config;
  35. ofnode node;
  36. if (IS_ENABLED(CONFIG_HAVE_VBT)) {
  37. void *buf;
  38. int ret;
  39. ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL);
  40. if (ret)
  41. return log_msg_ret("Cannot find VBT", ret);
  42. if (*(u32 *)buf != VBT_SIGNATURE)
  43. return log_msg_ret("VBT signature", -EINVAL);
  44. /*
  45. * Load VBT before devicetree-specific config. This only
  46. * supports memory-mapped SPI at present.
  47. */
  48. cfg->graphics_config_ptr = (ulong)buf;
  49. }
  50. node = dev_read_subnode(dev, "fsp-s");
  51. if (!ofnode_valid(node))
  52. return log_msg_ret("fsp-s settings", -ENOENT);
  53. return fsp_s_update_config_from_dtb(node, cfg);
  54. }
  55. /* Configure package power limits */
  56. static int set_power_limits(struct udevice *dev)
  57. {
  58. msr_t rapl_msr_reg, limit;
  59. u32 power_unit;
  60. u32 tdp, min_power, max_power;
  61. u32 pl2_val;
  62. u32 override_tdp[2];
  63. int ret;
  64. /* Get units */
  65. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
  66. power_unit = 1 << (rapl_msr_reg.lo & 0xf);
  67. /* Get power defaults for this SKU */
  68. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
  69. tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
  70. pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  71. min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
  72. max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  73. if (min_power > 0 && tdp < min_power)
  74. tdp = min_power;
  75. if (max_power > 0 && tdp > max_power)
  76. tdp = max_power;
  77. ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
  78. ARRAY_SIZE(override_tdp));
  79. if (ret)
  80. return log_msg_ret("tdp-pl-override-mw", ret);
  81. /* Set PL1 override value */
  82. if (override_tdp[0])
  83. tdp = override_tdp[0] * power_unit / 1000;
  84. /* Set PL2 override value */
  85. if (override_tdp[1])
  86. pl2_val = override_tdp[1] * power_unit / 1000;
  87. /* Set long term power limit to TDP */
  88. limit.lo = tdp & PKG_POWER_LIMIT_MASK;
  89. /* Set PL1 Pkg Power clamp bit */
  90. limit.lo |= PKG_POWER_LIMIT_CLAMP;
  91. limit.lo |= PKG_POWER_LIMIT_EN;
  92. limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
  93. PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
  94. /* Set short term power limit PL2 */
  95. limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
  96. limit.hi |= PKG_POWER_LIMIT_EN;
  97. /* Program package power limits in RAPL MSR */
  98. msr_write(MSR_PKG_POWER_LIMIT, limit);
  99. log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
  100. 100 * (tdp % power_unit) / power_unit);
  101. log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
  102. 100 * (pl2_val % power_unit) / power_unit);
  103. /*
  104. * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
  105. * instead of MMIO, so disable LIMIT_EN bit for MMIO
  106. */
  107. writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
  108. writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
  109. return 0;
  110. }
  111. int p2sb_unhide(void)
  112. {
  113. struct udevice *dev;
  114. int ret;
  115. ret = uclass_find_first_device(UCLASS_P2SB, &dev);
  116. if (ret)
  117. return log_msg_ret("p2sb", ret);
  118. ret = p2sb_set_hide(dev, false);
  119. if (ret)
  120. return log_msg_ret("hide", ret);
  121. return 0;
  122. }
  123. /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
  124. static void set_sci_irq(void)
  125. {
  126. /* Skip this for now */
  127. }
  128. int arch_fsps_preinit(void)
  129. {
  130. struct udevice *itss;
  131. int ret;
  132. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  133. if (ret)
  134. return log_msg_ret("no itss", ret);
  135. /*
  136. * Clear the GPI interrupt status and enable registers. These
  137. * registers do not get reset to default state when booting from S5.
  138. */
  139. ret = pinctrl_gpi_clear_int_cfg();
  140. if (ret)
  141. return log_msg_ret("gpi_clear", ret);
  142. return 0;
  143. }
  144. int arch_fsp_init_r(void)
  145. {
  146. bool s3wake;
  147. struct udevice *dev, *itss;
  148. int ret;
  149. if (!ll_boot_init())
  150. return 0;
  151. s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
  152. gd->arch.prev_sleep_state == ACPI_S3;
  153. /*
  154. * This must be called before any devices are probed. Put any probing
  155. * into arch_fsps_preinit() above.
  156. *
  157. * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
  158. * force PCI to be probed.
  159. */
  160. ret = fsp_silicon_init(s3wake, false);
  161. if (ret)
  162. return ret;
  163. ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
  164. if (ret)
  165. return log_msg_ret("no itss", ret);
  166. /*
  167. * Restore GPIO IRQ polarities back to previous settings. This was
  168. * stored in reserve_arch() - see X86_IRQT_ITSS
  169. */
  170. irq_restore_polarities(itss);
  171. /* soc_init() */
  172. ret = p2sb_unhide();
  173. if (ret)
  174. return log_msg_ret("unhide p2sb", ret);
  175. /* Set RAPL MSR for Package power limits*/
  176. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
  177. if (ret)
  178. return log_msg_ret("Cannot get northbridge", ret);
  179. set_power_limits(dev);
  180. /*
  181. * FSP-S routes SCI to IRQ 9. With the help of this function you can
  182. * select another IRQ for SCI.
  183. */
  184. set_sci_irq();
  185. return 0;
  186. }