p1010si-post.dtsi 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P1010 Silicon/SoC Device Tree Source (post include)
  4. *
  5. * Copyright 2020 NXP
  6. */
  7. &soc {
  8. #address-cells = <1>;
  9. #size-cells = <1>;
  10. device_type = "soc";
  11. compatible = "fsl,p1010-immr", "simple-bus";
  12. bus-frequency = <0>;
  13. mpic: pic@40000 {
  14. interrupt-controller;
  15. #address-cells = <0>;
  16. #interrupt-cells = <4>;
  17. reg = <0x40000 0x40000>;
  18. compatible = "fsl,mpic";
  19. device_type = "open-pic";
  20. big-endian;
  21. single-cpu-affinity;
  22. last-interrupt-source = <255>;
  23. };
  24. espi0: spi@7000 {
  25. compatible = "fsl,mpc8536-espi";
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. reg = <0x7000 0x1000>;
  29. fsl,espi-num-chipselects = <1>;
  30. status = "disabled";
  31. };
  32. /include/ "pq3-i2c-0.dtsi"
  33. /include/ "pq3-i2c-1.dtsi"
  34. /include/ "pq3-etsec2-0.dtsi"
  35. enet0: ethernet@b0000 {
  36. queue-group@b0000 {
  37. fsl,rx-bit-map = <0xff>;
  38. fsl,tx-bit-map = <0xff>;
  39. };
  40. };
  41. /include/ "pq3-etsec2-1.dtsi"
  42. enet1: ethernet@b1000 {
  43. queue-group@b1000 {
  44. fsl,rx-bit-map = <0xff>;
  45. fsl,tx-bit-map = <0xff>;
  46. };
  47. };
  48. /include/ "pq3-etsec2-2.dtsi"
  49. enet2: ethernet@b2000 {
  50. queue-group@b2000 {
  51. fsl,rx-bit-map = <0xff>;
  52. fsl,tx-bit-map = <0xff>;
  53. };
  54. };
  55. };
  56. /* controller at 0x9000 */
  57. &pci1 {
  58. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  59. law_trgt_if = <1>;
  60. #address-cells = <3>;
  61. #size-cells = <2>;
  62. device_type = "pci";
  63. bus-range = <0x0 0xff>;
  64. };
  65. /* controller at 0xa000 */
  66. &pci0 {
  67. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  68. law_trgt_if = <2>;
  69. #address-cells = <3>;
  70. #size-cells = <2>;
  71. device_type = "pci";
  72. bus-range = <0x0 0xff>;
  73. };