kmtegr1.dts 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ABB PGGA TEGR1 Device Tree Source
  4. *
  5. * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
  6. *
  7. */
  8. /dts-v1/;
  9. / {
  10. model = "KMTEGR1";
  11. compatible = "ABB,kmpbec8309";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. aliases {
  15. ethernet0 = &enet_zynq;
  16. ethernet1 = &enet_piggy2;
  17. serial0 = &serial0;
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8309@0 {
  23. device_type = "cpu";
  24. reg = <0x0>;
  25. d-cache-line-size = <32>; // 32 bytes
  26. i-cache-line-size = <32>; // 32 bytes
  27. d-cache-size = <16384>; // L1, 16K
  28. i-cache-size = <16384>; // L1, 16K
  29. timebase-frequency = <66000000>;
  30. bus-frequency = <264000000>;
  31. clock-frequency = <264000000>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <0x00000000 0x10000000>;
  37. };
  38. soc: soc8309@e0000000 {
  39. #address-cells = <1>;
  40. #size-cells = <1>;
  41. device_type = "soc";
  42. compatible = "simple-bus";
  43. ranges = <0x0 0xe0000000 0x00100000>;
  44. reg = <0xe0000000 0x00000200>;
  45. bus-frequency = <264000000>;
  46. i2c@3000 {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. cell-index = <0>;
  50. compatible = "fsl,mpc8313-i2c","fsl-i2c";
  51. reg = <0x3000 0x100>;
  52. interrupts = <14 0x8>;
  53. interrupt-parent = <&ipic>;
  54. clock-frequency = <400000>;
  55. mux@70 {
  56. compatible = "nxp,pca9547";
  57. reg = <0x70>;
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. i2c@1 {
  61. reg = <1>;
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. /*
  65. * Inventory EEPROM of the
  66. * unit itself
  67. */
  68. ivm@50 {
  69. label = "MAIN_CTRL";
  70. compatible = "dummy";
  71. reg = <0x50>;
  72. };
  73. };
  74. i2c@2 {
  75. reg = <2>;
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. /* Temperature sensors */
  79. temp@48 {
  80. label = "front";
  81. compatible = "national,lm75";
  82. reg = <0x48>;
  83. };
  84. temp@49 {
  85. label = "board";
  86. compatible = "national,lm75";
  87. reg = <0x49>;
  88. };
  89. temp@4a {
  90. label = "power";
  91. compatible = "national,lm75";
  92. reg = <0x4a>;
  93. };
  94. temp@4b {
  95. label = "bottom";
  96. compatible = "national,lm75";
  97. reg = <0x4b>;
  98. };
  99. };
  100. i2c@6 {
  101. reg = <6>;
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. };
  105. i2c@5 {
  106. reg = <5>;
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. };
  110. i2c@7 {
  111. reg = <7>;
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. };
  115. i2c@3 {
  116. reg = <3>;
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. };
  120. };
  121. };
  122. serial0: serial@4500 {
  123. cell-index = <0>;
  124. device_type = "serial";
  125. compatible = "fsl,ns16550", "ns16550";
  126. reg = <0x4500 0x100>;
  127. clock-frequency = <264000000>;
  128. interrupts = <9 0x8>;
  129. interrupt-parent = <&ipic>;
  130. };
  131. dma@82a8 {
  132. #address-cells = <1>;
  133. #size-cells = <1>;
  134. compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
  135. reg = <0x82a8 4>;
  136. ranges = <0 0x8100 0x1a8>;
  137. interrupt-parent = <&ipic>;
  138. interrupts = <71 8>;
  139. cell-index = <0>;
  140. dma-channel@0 {
  141. compatible = "fsl,mpc8309-dma-channel",
  142. "fsl,elo-dma-channel";
  143. reg = <0 0x80>;
  144. interrupt-parent = <&ipic>;
  145. interrupts = <71 8>;
  146. };
  147. dma-channel@80 {
  148. compatible = "fsl,mpc8309-dma-channel",
  149. "fsl,elo-dma-channel";
  150. reg = <0x80 0x80>;
  151. interrupt-parent = <&ipic>;
  152. interrupts = <71 8>;
  153. };
  154. dma-channel@100 {
  155. compatible = "fsl,mpc8309-dma-channel",
  156. "fsl,elo-dma-channel";
  157. reg = <0x100 0x80>;
  158. interrupt-parent = <&ipic>;
  159. interrupts = <71 8>;
  160. };
  161. dma-channel@180 {
  162. compatible = "fsl,mpc8309-dma-channel",
  163. "fsl,elo-dma-channel";
  164. reg = <0x180 0x28>;
  165. interrupt-parent = <&ipic>;
  166. interrupts = <71 8>;
  167. };
  168. };
  169. ipic: pic@700 {
  170. #address-cells = <0>;
  171. #interrupt-cells = <2>;
  172. compatible = "fsl,pq2pro-pic", "fsl,ipic";
  173. interrupt-controller;
  174. reg = <0x700 0x100>;
  175. device_type = "ipic";
  176. };
  177. gpio1: gpio-controller@c00 {
  178. #gpio-cells = <2>;
  179. compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
  180. reg = <0xc00 0x100>;
  181. interrupts = <75 0x8>;
  182. interrupt-parent = <&ipic>;
  183. gpio-controller;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. };
  187. gpio2: gpio-controller@d00 {
  188. #gpio-cells = <2>;
  189. compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
  190. reg = <0xd00 0x100>;
  191. interrupts = <75 0x8>;
  192. interrupt-parent = <&ipic>;
  193. gpio-controller;
  194. interrupt-controller;
  195. #interrupt-cells = <2>;
  196. };
  197. spi@7000 {
  198. cell-index = <0>;
  199. compatible = "fsl,spi";
  200. reg = <0x7000 0x1000>;
  201. interrupts = <16 0x8>;
  202. interrupt-parent = <&ipic>;
  203. mode = "cpu";
  204. #address-cells = <1>;
  205. #size-cells = <0>;
  206. /* GPIO_15 chipselect for ZYNQ flash */
  207. gpios = <&gpio1 15 0>;
  208. zynq_flash@0 {
  209. #address-cells = <1>;
  210. #size-cells = <1>;
  211. compatible = "spansion,m25p80";
  212. reg = <0>;
  213. spi-max-frequency = <4000000>;
  214. m25p,fast-read;
  215. partition@0 {
  216. label = "bootloader";
  217. reg = <0x0 0x01000000>;
  218. };
  219. };
  220. };
  221. };
  222. qe: qe@e0100000 {
  223. #address-cells = <1>;
  224. #size-cells = <1>;
  225. device_type = "qe";
  226. compatible = "fsl,qe";
  227. ranges = <0x0 0xe0100000 0x00100000>;
  228. reg = <0xe0100000 0x480>;
  229. brg-frequency = <0>;
  230. bus-frequency = <396000000>;
  231. fsl,qe-num-snums = <32>;
  232. muram@10000 {
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. compatible = "fsl,qe-muram", "fsl,cpm-muram";
  236. ranges = <0x0 0x00010000 0x00004000>;
  237. data-only@0 {
  238. compatible = "fsl,qe-muram-data",
  239. "fsl,cpm-muram-data";
  240. reg = <0x0 0x4000>;
  241. };
  242. };
  243. /* ZYNQ (UCC1, MDIO 0x10, MII) */
  244. enet_zynq: ethernet@2000 {
  245. device_type = "network";
  246. compatible = "ucc_geth";
  247. cell-index = <1>;
  248. reg = <0x2000 0x200>;
  249. interrupts = <32>;
  250. interrupt-parent = <&qeic>;
  251. local-mac-address = [ 00 00 00 00 00 00 ];
  252. /*id=0, full-dup, 100M, no-pause, no-asym_p*/
  253. fixed-link = <0 1 100 0 0>;
  254. rx-clock-name = "clk9";
  255. tx-clock-name = "clk10";
  256. phy-connection-type = "mii";
  257. };
  258. /* Piggy2 (UCC3, MDIO 0x00, RMII) */
  259. enet_piggy2: ucc@2200 {
  260. device_type = "network";
  261. compatible = "ucc_geth";
  262. cell-index = <3>;
  263. reg = <0x2200 0x200>;
  264. interrupts = <34>;
  265. interrupt-parent = <&qeic>;
  266. local-mac-address = [ 00 00 00 00 00 00 ];
  267. rx-clock-name = "none";
  268. tx-clock-name = "clk12";
  269. phy-handle = <&phy_piggy2>;
  270. phy-connection-type = "rmii";
  271. };
  272. mdio@2320 {
  273. #address-cells = <1>;
  274. #size-cells = <0>;
  275. reg = <0x2320 0x38>;
  276. compatible = "fsl,ucc-mdio";
  277. /* Piggy2 (UCC3, MDIO 0x00, RMII) */
  278. phy_piggy2: ethernet-phy@0 {
  279. reg = <0x0>;
  280. device_type = "ethernet-phy";
  281. };
  282. /* Explicitly set the tbi-phy to a non-zero address
  283. * so that it does not conflict with phy_piggy2 that
  284. * is unfortunately at address 0
  285. */
  286. tbi1: tbi-phy@1 {
  287. reg = <0x1>;
  288. device_type = "tbi-phy";
  289. };
  290. };
  291. qeic: interrupt-controller@80 {
  292. interrupt-controller;
  293. compatible = "fsl,qe-ic";
  294. #address-cells = <0>;
  295. #interrupt-cells = <1>;
  296. reg = <0x80 0x80>;
  297. big-endian;
  298. interrupts = <32 8 33 8>;
  299. interrupt-parent = <&ipic>;
  300. };
  301. bootcount@0x13ff8 {
  302. device_type = "bootcount";
  303. compatible = "u-boot,bootcount";
  304. reg = <0x13ff8 0x08>;
  305. };
  306. };
  307. localbus@e0005000 {
  308. #address-cells = <2>;
  309. #size-cells = <1>;
  310. compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
  311. "simple-bus";
  312. reg = <0xe0005000 0xd8>;
  313. ranges = <0 0 0xf0000000 0x04000000
  314. 1 0 0xe8000000 0x01000000
  315. 2 0 0xe0000000 0x10000000
  316. 3 0 0xb0000000 0x10000000>;
  317. flash@0,0 {
  318. compatible = "cfi-flash";
  319. reg = <0 0x00000000 0x04000000>;
  320. bank-width = <2>;
  321. nornand = "nor";
  322. #address-cells = <1>;
  323. #size-cells = <1>;
  324. use-advanced-sector-protection;
  325. partition@0 { /* 768KB */
  326. label = "u-boot";
  327. reg = <0 0xc0000>;
  328. };
  329. partition@c0000 { /* 256KB */
  330. label = "qe-fw";
  331. reg = <0xc0000 0x40000>;
  332. };
  333. partition@100000 { /* 128KB */
  334. label = "env";
  335. reg = <0x100000 0x20000>;
  336. };
  337. partition@120000 { /* 128KB */
  338. label = "envred";
  339. reg = <0x120000 0x20000>;
  340. };
  341. partition@140000 { /* 64256KB */
  342. label = "ubi0";
  343. reg = <0x140000 0x3EC0000>;
  344. };
  345. };
  346. };
  347. };
  348. #include "km8309-uboot.dtsi"